IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 32, NO.
2, FEBRUARY 1997
A Rail-to-Rail, Constant Gain, Buffered
Op-Amp for Real Time Video Applications
Laszlo Moldovan and Hua Harry Li, Member, IEEE
Abstract—Inspired by Hogervorst et al.’s current switch idea,
a buffered output stage operational amplifier was designed,
which has high frequency, high dc gain, and rail-to-rail constant
transconductance (Gm ). This operational amplifier is the output
stage of an analog/digital system which implements a Gabor
convolution for real-time dynamic image processing and it is
designed to interface the external analog-to-digital converter
(ADC) with a very heavy load. The op amp was fabricated by
the MOSIS service in a 2-m, n-well CMOS, double polysilicon,
double metal technology. The fabricated circuit operates from
a single 5 V power supply and dissipates 10 mW. The open
loop1gain of the fabricated circuit, Avol , was measured as 67.2
dB for a 163
k33 pF load. Other dc and ac characteristics were the currently active input transistor pair while keeping the
measured for a 50
k33 pF load. The unity gain-bandwidth
(GBW) was measured to be 11.4 MHz, the rising slew rate
(SR+) 20.4 V/s, the falling slew rate (SR0) 18.8 V/s, and the
offset voltage (Vo ) 1 mV. The output swings with an amplitude
of 3.24 V between 0.88 V and 4.12 V, which matches the input
signal specifications of the ADC. In addition to rail-to-rail output
voltage swing, the opamp has a constant Gm over the whole
common mode (CM) voltage range.
Index Terms—Current switch, op-amp, video application.
I. INTRODUCTION
D ESIGN of analog or hybrid circuits for lower power
dissipation and high speed operation applications [4]–[7],
[9]–[11] poses a very challenging task, especially in the
areas of video processing, dynamic image processing, and
multimedia computing. Many existing circuit structures are
unusable and have to be redesigned. In particular, in the area
of op amp design, new techniques have to be developed to keep
the transistors of the output stage in the saturation region with
lower voltage overhead in order to gain large output operating
range. In this paper, we describe the design of an operational
amplifier as an output buffering stage of a mixed analog-digital
microchip which is designed to perform a real-time Gabor
convolution for dynamic image processing.
In order to drive a common mode input voltage from rail
to rail, we utilize a complementary input stage [8] which
Manuscript received March 3, 1996; revised July 16, 1996. This work is
supported in part by the Office of Naval Research under Grant N00014-94-1-
0077.
L. Moldovan was with the Department of Computer Science, College of
Engineering, Texas Tech University, Lubbock, TX 79409-3104 USA. He is
now with Intel, Santa Clara, CA 95051 USA.
H. H. Li was with the Department of Computer Science, College of
Engineering, Texas Tech University, Lubbock, TX 79409-3104 USA. He is
now with the Computer Engineering Department, College of Engineering, San
Jose State University, San Jose, CA 95192 USA.
Publisher Item Identifier S 0018-9200(97)01131-1.
0018–9200/97$10.00  1997 IEEE
169
consists of a parallel combination of an n-type and a p-type
differential pair of transistors. This structure maximizes the
output voltage swing, but introduces a big variation of the
overall transconductance by a factor of two [2], which, in
turn, impedes optimal frequency compensation, as it is well
know that the unity gain-bandwidth (GBW) of an op-amp is
proportional to the transconductance of its input stage. In order
to solve this problem, inspired by Hogervorst et al.’s current
switch idea [3], we utilized a double current switch and a
current mirror combination to compensate the tail current of
transconductance constant.
We improved the heavy load driving capability by using a
current-driven common-source output stage described in [1],
which provides a good solution that does not degrade the
output voltage swing. With this buffer, the output voltage slews
on a heavy load of 50 35 pF and uses 82% of the total
swinging capability. The price paid by using this configuration
is the big ratio of the output transistors. Under this load,
the op-amp has an of 66 dB, a GBW of 12 MHz, a phase
margin (PM) of 74 , and a power dissipation of 10 mW.
II. DESIGN METHODOLOGY
A. Input Stage
When the supply voltage is small, using a single input dif-
ferential pair becomes impractical, due to the small common-
mode input voltage range. This range, which was reduced by a
threshold voltage and a saturation voltage, represents 70% of
the total input. To maximize the input voltage range, we used
the double pair, complementary differential input stage shown
in Fig. 1. A p-channel pair (M1–M2), in parallel with an n-
channel pair (M5–M6) is used so that the whole common mode
input range can be covered, with at least one pair conducting.
This circuit has three operating regions with respect to
the input CM voltage range. When the CM input voltage
is a threshold voltage ( V) plus a saturation voltage (a
few hundreds of millivolts) above the negative power supply
(VSS), only the p-channel transistor pair is on. When the CM
input voltage is a threshold voltage and a saturation voltage
below the positive voltage supply (VDD), only the n-channel
input pair is on. For CM input voltages between these two
limits, both transistor pairs are on. This circuit provides a rail-
to-rail CM input range, but it also introduces a major problem.
In the region where both pairs are on, the transconductance of
170
Fig. 1. Input stage.
the input stage is twice as big as in the regions where only
one pair ( - or -) is on. The transconductance is given by
(1)
where is the transconductance parameter and is the
saturation drain current of the transistor. This makes optimal
frequency compensation very difficult, since the GBW of an
op-amp is proportional to the transconductance of its input
stage.
The input stage is biased by transistors M8, M9, M4,
and M40 with a 38 A current. The tail currents for the
intermediate CM input voltage range of the differential pairs
was set respectively to 200 A. The input pairs were sized
as m m and m m
respectively.
The transconductance of the input stage is desired to be large
in order to improve the op-amp gain and signal-to-noise ratio.
Therefore, the input transistors need to be biased in strong
inversion. In this operating region, the transconductance is
proportional to the square root of the tail current. So, when one
of the transistor pairs is off, the tail current of the pair which
is on needs to be increased by a factor of four. Thus,
is increased by a factor of two in the regions adjacent to the
power supplies, making the overall transconductance constant
through the whole CM input voltage range. Transistors M20
and M23 act as current switches, and transistors M21–M22
and M24–M25 are 1 : 3 current mirrors. The gate of M20
is biased approximately a few hundreds millivolts below a
threshold voltage and a saturation voltage. Therefore, M20 will
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 32, NO. 2, FEBRUARY 1997
be on (and M23 off) when M1 and M2 are off, rerouting the
tail current flowing through M3 to the 1 : 3 current amplifier
M21–M22. The drain current of M22 gets added to the tail
current of the pair M5–M6 (currently on), which results in a
tail current four times larger, which means an increased
by a factor of two. When M20 turns off, M1–M2 switches
on. This process is identically repeated when the CM input
voltage drops below a few hundreds of millivolts more than
a threshold voltage and a saturation voltage. This current
switching mechanism keeps the transconductance constant.
This process is illustrated in Fig. 2.
Fig. 2 contains the currents supplied by the compensation
mechanism to the tail currents of the two input pairs. The
-axis represents the CM input voltage. These currents are
added to the currents flowing through transistors M7 and M3,
respectively. The tail current of both input pairs was set to
200 A, and it is shown that the value of these currents
necessary to compensate for a constant is 600 A. In
Fig. 3 the effect of the current compensation mechanism on
the sum of the tail currents is shown. The -axis represents
the CM input voltage.
It can be noticed that the sum of the tail currents is equal to
800 A at the ends of the CM input range, and equal to 200 A
in the intermediate region. Also, it can be noticed that the
relatively low output impedance of the simple current mirrors
(M21–M22 and M24–M25) introduces a slight variation in the
sum of the tail currents, which is reflected as a variation in the
input stage transconductance. This can be improved by using a
current mirror with a very large output impedance made with
super MOS transistors [8]. The value of is 196 A/V in
MOLDOVAN AND LI: A RAIL-TO-RAIL, CONSTANT GAIN, BUFFERED OP-AMP
Fig. 2. Tail current compensation.
the intermediate region of the common mode input voltage and
202.5 A/V in the region close to the power supplies. With
this compensation circuit, the op-amp transconductance varies
only by a factor of maximum 1.033, which is a significant
improvement over [1] (which reported a variation of
and [2] (a factor of two).
Transistors M30 and M31 are biased and sized in such a way
that they let equal currents flow through the - and -parts
of the cascode stage, thus providing symmetrical operation.
The -part (M26–M29) and -part (M32–M35) of the cascode
stage sum the currents from the input stage and act as driving
current sources for the output buffering stage.
B. Circuit Description
The input circuit described in the last section needs to be
further improved in order to drive heavy loads as the one
consisting of the input impedance of the analog-to-digital
converter (ADC) (50 35 pF). Therefore, an output buffering
stage is required, which would drive a relatively large current
into the load impedance. In low voltage design, the choices for
a suitable structure are limited to the common-source topology
171
because the source follower has an inadmissible low output
voltage swing. We employ the current-driven common-source
output buffer. The complete schematic of the buffered op-amp
is shown in Fig. 4.
The output stage is biased in class AB and has a very
low quiescent current. Transistors M36 and M37 bias the two
output MOS devices (M38 and M39) in such a way that they
conduct only in one half of the common-mode voltage range,
minimizing the power consumption. In order to provide at least
45 phase margin, capacitors CC1 and CC2 have to be used.
For a 5 pF compensation, the simulation results show a PM
of 74 for a 50 35 pF load.
III. SIMULATION RESULTS
The designed buffered op-amp meets all the specifications
for our application. For the specified load, it has an output
voltage swing of 82% of the common-mode voltage. This is
shown in Fig. 5.
V2 represents the CM input voltage swept from 0 to 5
V and V(3) is the output voltage. Also, it exhibits a dc
gain of 66 dB and a GBW of 12 MHz at a PM of 74 .
172 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 32, NO. 2, FEBRUARY 1997

Fig. 3. Sum of the tail currents.

Fig. 4. Complete op-amp schematic.

MOLDOVAN AND LI: A RAIL-TO-RAIL, CONSTANT GAIN, BUFFERED OP-AMP 173

Fig. 5. Unity-gain transfer characteristic.

These characteristics are illustrated in Fig. 6, which represent TABLE I

the open-loop frequency and phase characteristics of the op- SIMULATED DC AND AC CHARACTERISTICS OF THE BUFFERED OP-AMP
amp. Load 50
k35 pF 1 M
k1 pF
The vertical axis is scaled in both decibels and degrees. Supply voltage 5V 5V
Compensation capacitor 5 pF 5 pF
Trace db(v(3)) is the open loop frequency characteristic and
DC gain 66 dB 103 dB
vp(3) is the open loop phase characteristic. The op-amp char- GBW 12 MHz 29 MHz
acteristics for a heavy (50 35 pF) and a light (1 M 11 pF) Phase margin 74 58
load, from PSPICE simulations, are summarized in Table I. Slew rate 0 12 V/s 9 V/s
Slew rate + 12 V/s 9 V/s
Vo 1 mV 3.4 mV
IV. TESTING RESULTS OF THE FABRICATED CHIP Vout + 4.5 V 5V
Vout 0 0.4 V 0V
The op-amp was fabricated through the MOSIS service CMRR (DC) 105 dB 105 dB
in a 2- m, n-well, double metal, double polysilicon CMOS CMRR (1 MHz) 82 dB 82 dB
process. The layout is illustrated in Fig. 7. Power dissip. 10 mW 10 mW

A photograph of the die with four prototypes of the op-amp

is shown in Fig. 8. Fig. 9 depicts the photograph of a single
buffered op-amp.
The two pairs of input transistors were implemented using
the interdigitized technique [7]. The two, class AB, common
source transistors dominate the layout of the circuit. Their
size is due to the high current required to drive the 50
35 pF input impedance of an analog-to-digital converter
(ADC).
Most of the dc characteristics were tested with the op-
amp connected in a voltage follower configuration. The output
voltage swings for a 50 33 pF and a 1 M 1 pF are
illustrated by the unity gain transfer characteristics for these
two cases (Figs. 10 and 11). For the first load, the output
swings between 0.88 V and 4.12 V with an amplitude of
3.24 V, and for the second load, between the two rails.
174 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 32, NO. 2, FEBRUARY 1997

Fig. 6. Open-loop frequency and phase characteristics (50

k35 pF).

Fig. 7. VLSI layout of the buffered op-amp.

MOLDOVAN AND LI: A RAIL-TO-RAIL, CONSTANT GAIN, BUFFERED OP-AMP 175

Fig. 10. Unity gain transfer characteristic of the buffered op-amp for a
50
k33pF load.

Fig. 8. Photograph of the die with four buffered op-amps.

Fig. 11. Unity gain transfer characteristic of the buffered op-amp for a
1 M
k1 pF load.

Fig. 9. Photograph of a single buffered op-amp.

The large and small signal transient responses are illustrated

in Figs. 12 and 13.
The ac characteristics were measured with a negative feed-
back network consisting of a 3 M resistor between the
output and the inverting input and a 2.2 nF capacitor between Fig. 12. Large signal transient response of the buffered op-amp for a
the ground and the inverting input. The open-loop gain was 50
k33 pF load.
measured for a 163 33 pF load. We were unable to measure
the open loop gain with a 50 resistor, because the op- results. The unity GBW was determined by extrapolating a
amp was self-oscillating. For this load, the open-loop gain was Bode plot obtained by measuring for frequency values
measured to be 67.2 dB, which agrees with the simulation between 100 kHz and 5 MHz. The value for the GBW was
176 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 32, NO. 2, FEBRUARY 1997

[2] J. A. Fisher and R. Koch, “A highly linear CMOS buffer amplifier,”

IEEE J. Solid-State Circuits, vol. SC-22, pp. 330–334, June 1987.
[3] R. Hogervorst, R. J. Wiegerink, P. de Jong, J. Fonderie, R. Wasse-
naar, and J. Juijsing, “CMOS low-voltage operational amplifiers with
constant-gm, rail-to-rail input stage,” in Proc. IEEE Int. Symp. Circuits
Systems, 1992, pp. 2876–2879.
[4] J. H. Huijsing and D. Linebarger, “Low-voltage operational amplifier
with rail-to-rail input and output ranges,” IEEE J. Solid-State Circuits,
vol. SC-20, pp. 1144–1150, Dec. 1985.
[5] T. Fiez et al., “A family of high-swing CMOS operational amplifiers,”
IEEE J. Solid-State Circuits, vol. 24, pp. 1683–1687, Dec. 1989.
[6] R. L. Geiger et al., VLSI Design Techniques for Analog and Digital
Circuits. New York: McGraw-Hill, 1990.
[7] R. E. Vallee and E. I. El-Masry, “A very high frequency CMOS
complementary folded cascode amplifier,” IEEE J. Solid-State Circuits,
vol. 29, pp. 130–133, Feb. 1994.
[8] M. Ismail and T. Fiez, Analog VLSI Signal and Information Processing.
New York: McGraw-Hill, 1994.
[9] J. Lloyd and H.-S. Lee, “A CMOS opamp with fully-differential gain-
enhancement,” IEEE Trans. Circuits Syst.-II, vol. 41, pp. 241–243, Mar.
1994.
[10] E. Sackinger and W. Guggenbuhl, “A high-swing, high-impedance MOS
Fig. 13. Small signal transient response of the buffered op-amp for a
k
50
33 pF load.
cascode circuit,” IEEE J. Solid-State Circuits, vol. 25, pp. 289–297, Feb.
1990.
[11] K. R. Laker and W. M. C. Sansen, Design of Analog Integrated Circuits
TABLE II and Systems. New York: McGraw-Hill, 1994.
MEASURED DC AND AC CHARACTERISTICS OF THE BUFFERED OP-AMP
Supply voltage 5V
k
DC gain (163
33 pF load) 67.2 dB
GBW 11.4 MHz
k
SR+ (50
33 pF load) 20.4 v/s
Laszlo Moldovan was born in Tirgu Mures, Ro-
0 k
SR (50
33 pF load) 18.8 v/s
mania. He graduated from the Technical University
of Timisoara in 1991. In December 1993 he re-
Vo 1 mV ceived the Master’s degree in electrical engineering
Vout + 4.12 V from Texas Tech University, Lubbock. His area
Vout 0 0.88 V of research consisted of amorphous silicon and
Power dissip. 10 mW amorphous carbon thin films using chemical vapor
deposition. In May 1996, he received the Master’s
degree in computer science from the same uni-
found to be 11.4 MHz, which also agrees with the simulation versity, building an analog microchip for real-time
results. The experimental values for the buffered op-amp are image processing.
displayed in Table II. He is currently working for Intel Corporation in Santa Clara, CA.

V. SUMMARY
This paper presents a buffered, high-frequency/gain, rail-
to-rail input and output ranges with a constant transcon-
ductance over the whole common-mode voltage range. This
was achieved by using a tail current compensation circuit,
composed of a pair of current switch-current mirror combi-
nation. With this circuit, the transconductance of the input
stage varies only by a factor of maximum 1.033, which is a
significant improvement over the previously reported op-amps
with similar performances. The op-amp also exhibits improved
frequency and gain performance with a slight increase in the
power dissipation (10 mW). This circuit is capable of driving
an off-chip ADC with an input impedance of 50 35 pF up
to 64.8% of the rails. This operational amplifier is a part of the
analog/digital system which implements a Gabor convolution
for real-time dynamic image processing.
ACKNOWLEDGMENT
The authors would like to thank Dr. Kristiansen and Dr.
Giesselmann for lending their equipment for the chip testing.
REFERENCES
[1] W.-C. S. Wu et al., “Digital-compatible high-performance operational
amplifier with rail-to-rail input and output ranges,” IEEE J. Solid-State
Circuits, vol. 29, pp. 63–66, Jan. 1994.
Hua Harry Li (S’86–M’89) received the B.S. de-
gree in electronics engineering from Tianjin Univer-
sity, China, in 1982, and the M.S. and Ph.D. degrees
in electrical and computer engineering from The
University of Iowa, Iowa City, in 1984 and 1989,
respectively.
He is an Associate Professor of the Computer
Engineering Department, College of Engineering,
San Jose State Universtiy, CA. Before joining San
Jose State University, he held a tenured Associate
Professor position at the Computer Science Depart-
ment, College of Engineering, Texas Tech University. His current research
includes video processing and compression, computer vision, neural networks,
and their hardware, VLSI implementations. His work in the above mentioned
fields was published in IEEE TRANSACTIONS, IEEE Circuits and Devices,
IEEE Macro, IEE Electronics Letters, Journal of Applied Artificial Intelligence,
Journal of Artificial Intelligence and Pattern Recognition, etc. He is a coauthor
(with C. Koch) of an edited book, Vision Chips: Visual Computing with Analog
VLSI Circuits, (IEEE CS Press), and he is an author (with M. Gupta) of the
book, Fuzzy Logic and Intelligent Systems, (Kluwer) and (with S. Sun and
H. Derin) of the edited book Video Compression for Multimedia Computing
(Kluwer) to appear in 1996.
Some of Dr. Li’s research work and a prototype system was given an
Industrial Neural Network Award in 1994 World Congress Neural Network
Conference in San Diego, CA. He has been given Halliburton Award for the
excellence in teaching by the College of Engineering at Texas Tech University.
He was a guest editor for the special section on Neural Networks, Fuzzy Logic,
and their Applications in Electronics Manufacturing Technology for IEEE
TRANSACTIONS ON COMPONENTS, HYBRIDS, AND MANUFACTURING TECHNOLOGY
in 1994 and 1995.