Sony CXA7000R LCD Driver Chip Optimizes Display Performance

CXA7000R
LCD Driver
Description
The CXA7000R is a driver IC developed for use 64 pin LQFP (Plastic)
with Sony polycrystalline silicon TFT LCD panels. It
supports 10-bit digital input, and the input data is
analog demultiplexed into 6 phases and output. The
CXA7000R can directly drive an LCD panel, and the
VCOM setting circuit and precharge pulse waveform
generator are also on-chip.
Features
• Supports 10-bit input
• Supports signals up to XGA
• Low output deviation by on-chip output offset cancel circuit
• On-chip timing generator with ECL
• VCOM voltage generation circuit
• Precharge pulse waveform generation circuit
Applications
LCD projectors and other video equipment
Absolute Maximum Ratings (VSS = 0V)

• Supply voltage VCC 16 V
VDD 5.5 V
• Operating temperature Topr –20 to +70 °C
• Storage temperature Tstg –65 to +150 °C
• Allowable power dissipation PD 1250 mW
Recommended Operating Conditions

• Supply voltage VCC 15.0 to 15.5 V
VDD 4.75 to 5.25 V
• Operating temperature Topr –20 to +70 °C
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E01821A22
CXA7000R
Block Diagram
VCOM_OFST
VCOM_OUT
SID_OUT
F/H_CNT
VREF_O
PRG_LV
SL_DAT
VREF_I
SID_LV
VCC15
DIRC
VDD5
GND
GND
PRG
PS
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
VCOM_Gen.
TEST 49 SID_Gen. 32 PVCC
Vref Gen.
STATUS 50 31 SH_OUT1
Line inv.
D_IN9 51 Offset Cancel
30 NC
D_IN8 52 29 SH_OUT2
Line inv.
D_IN7 53 S/H S/H S/H 28 NC
Offset Cancel
D_IN6 54 27 SH_OUT3
S/H S/H S/H
Line inv.
D_IN5 55 Offset Cancel
26 GND
S/H S/H S/H
GND 56 25 PGND
D/A
GND 57 S/H S/H S/H 24 PGND
D_IN4 58 Line inv. 23 GND

S/H S/H S/H Offset Cancel
D_IN3 59 22 SH_OUT4
S/H S/H S/H Line inv.
D_IN2 60 21 NC
Offset Cancel
D_IN1 61 20 SH_OUT5
D_IN0 62 Line inv. 19 NC

Offset Cancel
MCLK 63 18 SH_OUT6
FRP Offset Cancel Control
TG CAL_PLS
MCLKX 64 17 PVCC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
FRP
SHST
POSCNT0
POSCNT1
POSCNT2
POSCNT3
SHTEST
GND
GND
NC
SIG.C
SIG_OFST
CAL_L
CAL_H
GND
DCFBOFF
–2–
CXA7000R
Pin Description
Pin
Symbol I/O Standard Equivalent circuit Description
No. voltage level
VDD
50k LCD panel AC drive inversion
timing input.
High: ≥2.0V 192
High: inverted
1 FRP I 1
Low: ≤0.8V Low: non-inverted
See the Timing Chart.
GND
Internal sample-and-hold timing

VDD
circuit reset pulse input.
50k
This pin is also used as the
High: ≥2.0V 192 offset cancel level insertion
2 SHST I 2
Low: ≤0.8V timing input.
A reset is applied to the internal
timing generator at the falling
GND edge.
VDD
Output phase adjustment.
3 50k
3 POSCNT0 The output phase is adjusted in
4 POSCNT1 High: ≥2.0V 4
192
MCLK period units when
I
5 POSCNT2 Low: ≤0.8V 5 SL_DAT is high, and in
6 POSCNT3 1/2 MCLK period units when
6
SL_DAT is low.
GND
VDD VCC
20µ Signal center voltage (inversion
30k folded voltage) adjustment input.
11 SIG.C I 1 to 5.0V 11 The SH_OUT output center
voltage can be adjusted in the
range from 7.0 to 8.0V.
GND
VDD VCC Output signal offset adjustment

10µ from signal center voltage.
30k The SH_OUT output 100%
12 SIG_OFST I 0 to 5.0V 12 white level (at 3FF input) voltage
can be adjusted in the range
from 0 to 1V from the center
GND voltage.
VCC
40µ 1k
Level output for canceling the
offset between channels.
13 CAL_L 3.0 to 6.0V 145 Connect the CAL_L and
I/O 13
14 CAL_H 9.0 to 12.0V CAL_H, between ICs when
14 using two CXA7000R.
GND
–3–
CXA7000R
Pin
No. voltage level
VDD
Offset cancel function off.
24k 24k Normally connect to GND to
145 use with the offset cancel
16 DCFBOFF I GND 16 function on.
High (offset cancel function off)
when open.
GND
PVCC
18
18 300 20
20 22
Demultiplexed output of AC
SH_OUT6 inverse driven video signals.
22
to O 1.5 to 13.5V 300
27
Can be connected directly to
27
SH_OUT1 29 the LCD panel.
29
31 31
GND
VCC
80µ
LCD panel common voltage
output.
100k 500 145 Can be set in the range from
33 VCOM_OUT O 5.0 to 8.0V 33 the SH_OUT center potential
500
Vsig.c to Vsig.c – 2V by
VCOM_OFST.
GND
VDD VCC
LCD panel common voltage
80µ adjustment.
2k VCOM_OUT can be set in the
34 VCOM_OFST I 0 to 5.0V 34 range from the SH_OUT center
100 potential Vsig.c to Vsig.c – 2V
by inputting 0 to 5V.
GND
VCC
100k
Precharge waveform output.
0.2p
145 These pins cannot directly drive
36 SID_OUT O 1.5 to 13.5V 36 the LCD panel, so input to the
100k LCD panel with an external
buffer.
0.2p
GND
–4–
CXA7000R
Pin
No. voltage level
VDD VCC
29µ Precharge level setting.
Adjusts the SID_OUT and
SID_OUTX output potential.
37 PRG_LV 50k
I 1.0 to 5.0V 37 PRG_LV is reflected when the
38 SID_LV PRG input pin (Pin 60) is high,
50k
38 and SID_LV is reflected when
PRG is low.
GND
VDD VCC
100k
Timing pulse input for switching
10k
High: ≥2.0V 39
the Pin 36 output levels.
39 PRG I
Low: ≤0.8V (See PRG_LV (Pin 37) and
50µ
SID_LV (Pin 38).)
GND
VDD
70µ 10µ
Internal D/A converter reference
voltage input.
44 VREF_I I 3.2V 44
1k 33.3k Normally connect directly to
VREF_O.
280µ
GND
VDD
2k
Reference voltage output.
45 Normally connect directly to
45 VREF_O O 3.2V VREF_I, and connect to GND
20k
20µ through a 0.5 to 1.0µF capacitor.
12.4k
GND
VDD
50k
SH_OUT output timing selection.
High: SH_OUT1 to SH_OUT3
High: ≥2.0V 192 and SH_OUT4 to SH_OUT6
46 F/H_CNT I Low: ≤0.8V 46
are output at different timing.
Open: Low Low: SH_OUT1 to SH_OUT6
200k
are output at the same timing.
GND
VDD
50k Scan direction setting.
High: output as a time series in
192
High: ≥2.0V 47
ascending order of output pin
47 DIRC I
Low: ≤0.8V symbol (in order from SH_OUT1
to SH_OUT6)
Low: output in descending order
GND
–5–
CXA7000R
Pin
No. voltage level
VDD
50k Digital input mode switch setting.
High: ≥2.0V 192 High: when using master/slave
48 SL_DAT I Low: ≤0.8V 48 mode two CXA7000R.
Open: Low 200k
Low: when using normal mode
one CXA7000R.
GND
VDD Master/slave setting when using

50k two CXA7000R.
200k
High: master IC. Offset cancel
High: ≥2.0V 192
level is output.
50 STATUS I 50
Low: ≤0.8V Low: slave IC. This pin is left
open (high) when using one
GND CXA7000R.
VDD
51 50k
to
192
55 D_IN9 to High: ≥2.0V 51 to 55
I Digital data input.
58 D_IN0 Low: ≤0.8V
58 to 62
to
62
GND
VDD
PECL 8k 140k
140k Dot clock input.
differential
1k PECL differential input or TTL
(amplitude 63
63 MCLK I 0.4V or more input. For TTL input, input to
1k
64 MCLKX between MCLK and connect MCLKX to
64
VDD to 2V) GND through a capacitor.
60k 100µ 60k
or TTL input
GND
VDD
70k
Test.
42 PS I 5V 42
Normally connect to VDD.
180k
30µ
GND
24, 25 PGND GND Power GND.

17, 32 PVCC 15.5V Power VCC.
35 VCC15 15.5V 15V power supply.
43 VDD5 5V 5V power supply.
–6–
CXA7000R
Pin
No. voltage level
8, 9, 15,
23, 26,
GND GND GND.
40, 41,
56, 57
10, 19, NC.
21, 28, NC These pins are not connected to
30 anything.
VDD
20k 20k
250k 20k
20k
192 Test.
7 SHTEST I 2.5V 7 Leave open.
250k
10µ 10µ
GND
VDD
1µ 2k
192
49 DAC output monitor test.
49 TEST O 1.7 to 3.2V Normally connect to VDD.
20µ
GND
–7–
CXA7000R
Electrical Characteristics Measurement Circuit
1µ
VDD
VCC
47p
VCOM_OFST
A A
VCOM_OUT
SID_OUT
F/H_CNT
VREF_O
PRG_LV
SL_DAT
VREF_I
SID_LV
VCC15
DIRC
VDD5
GND
GND
PRG
PS
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
VDD 49 32
TEST PVCC
50 31
STATUS SH_OUT1
51 30 270p
D_IN9 NC
52 29
D_IN8 SH_OUT2
53 28 270p
D_IN7 NC
54 27
D_IN6 SH_OUT3
55 26 270p
D_IN5 GND
56 25
GND PGND
57 24
GND PGND
58 23
D_IN4 GND
59 22
D_IN3 SH_OUT4
60 21 270p
D_IN2 NC
61 20
D_IN1 SH_OUT5
62 19 270p
D_IN0 NC
63 18
MCLK SH_OUT6
64 17 270p
MCLKX PVCC
A
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
FRP
SHST
POSCNT0
POSCNT1
POSCNT2
POSCNT3
SHTEST
GND
GND
NC
SIG.G
SIG_OFST
CAL_L
CAL_H
GND
DCFBOFF
VCC
VCC VDD
15.5V 5V
–8–
CXA7000R
Electrical Characteristics
Measurement
No. Item Symbol Measurement conditions Min. Typ. Max. Unit
points
Digital input
1 n — 10 — bit
resolution
Digital input SHST and D_IN[9:0] minimum setup
2 TS 2 — — ns
setup time time relative to MCLK input.
Digital input SHST and D_IN[9:0] minimum hold
3 TH 3 — — ns
hold time time relative to MCLK input.
MCLK input SL_DAT: 5V; maximum frequency at
4 frequency fMCLK1 which the internal timing generator 60 — 100 MHz
range 1 and D/A converter operate normally.
MCLK input SL_DAT: 0V; maximum frequency at
5 frequency fMCLK2 which the internal timing generator 30 — 80 MHz
range 2 and D/A converter operate normally.
VREF_I input VREF_I input voltage range at which
6 VVREF_I 2.7 3.2 3.5 V
voltage range the D/A converter operate normally.
VREF_O output Measure the VREF_O (Pin 45)
7 VVREF_O 3.1 3.2 3.3 V
voltage range voltage.
SH_OUT Measure the SH_OUT1 voltage
8 VSHOUTp-p VOUT1 4.39 4.5 4.64 V
amplitude difference at D_IN[9:0]: 000h and 3FFh.
Lower the VREF_I voltage and adjust
SH_OUT
the amplitude; minimum amplitude at V
9 minimum VOUTMINp-p VOUT1 3.9 — —
which SH_OUT1 can be output at
amplitude
D_IN[9:0]: 000h and 3FFh.
Load capacitance = 270pF; measure
slew rate at 10 to 90% of output
SH_OUT VOUT1 to
10 SROUT waveform rise and fall when D_IN[9:0] 150 150 — V/µs
slew rate VOUT6
is varied from 000h to 3FFh and from
3FFh to 000h.
SH_OUT Minimum voltage at which sample-
VOUT1 to
11 minimum VMIN and-hold outputs VOUT1 to VOUT6 can 1.5 — — V
VOUT6
output voltage be output.
SH_OUT Maximum voltage at which sample-
VOUT1 to
12 maximum VMAX and-hold outputs VOUT1 to VOUT6 can — — 13.5 V
VOUT6
output voltage be output.
Output deviation Value obtained by subtracting minimum
VOUT1 to
13 between DOUT1 VOUT1 to VOUT6 value from maximum — 3 10 mVp-p
VOUT6
channels 1 VOUT1 to VOUT6 value at D_IN[9:0]: 200h.
Value obtained by subtracting minimum
Output deviation
VOUT1 to VOUT1 to VOUT6 value from maximum
14 between DOUT2 — 10 40 mVp-p
VOUT6 VOUT1 to VOUT6 value at D_IN[9:0]: 000h
channels 2
or 3FFh.
Output deviation VOUT1 to VOUT1 to VOUT6 value from maximum
15 DIC1 — 10 — mVp-p
between ICs 1 VOUT6 VOUT1 to VOUT6 value at D_IN[9:0]: 200h.
(when using two CXA7000R)
–9–
CXA7000R
Measurement
No. Item Symbol points Measurement conditions Min. Typ. Max. Unit

Output deviation VOUT1 to VOUT1 to VOUT6 value from maximum
16 DIC2 — 20 — mVp-p
between ICs 2 VOUT6 VOUT1 to VOUT6 value at D_IN[9:0]: 000h
or 3FFh. (when using two CXA7000R)
PRG: 0V; measure VSID_LV and VSID at
SID output VSID_LV
17 ASID1 FRP: 0V, and VSID_LV at FRP: 5V. 1.9 2 2.1 times
gain 1 VSID
Calculate as ASID1 = VSID/VSID_LV.
PRG: 5V; measure VPRG_LV and VSID at
SID output VPRG_LV
18 ASID2 FRP: 0V, and VPRG_LV at FRP: 5V. 1.9 2 2.1 times
gain 2 VSID
Calculate as ASID2 = VSID/VPRG_LV.
Load capacitance = 47pF, PRG: 0V;
input a repeating high/low pulse to FRP
SID output (Pin 1), and apply DC input voltage so
19 SRSID VSID 27 50 — V/µs
slew rate that VSID is 4V/10V.
Measure slew rate at 10 to 90% of
output waveform rise and fall.
Signal center VOUT1 center voltage when SIG.C
20 VSIG VOUT1 7 — 8 V
adjustable range (Pin 11) is varied from 0 to 5V.
D_IN[9:0]: 3FFh, FRP: 0V; value
SH_OUT offset obtained by subtracting VOUT1 from
21 VSIGOFST VOUT1 0 — 1 V
adjustable range VOUT1 center voltage when SIG_OFST
(Pin 12) is varied from 0 to 5V.
VCOM VCOM_OUT voltage when VCOM_OFST Vc –
22 VCOM VCOM — Vc V
adjustable range (Pin 34) is varied from 0 to 5V. 2.5
VDD current
23 IDD IVDD IDD = IVDD — 52 — mA
consumption
VCC current IVCC1
24 ICC ICC = IVCC1 + IVCC2 — 18 — mA
consumption IVCC2
Current
IVDD
consumption in GND (Pin 42),
25 IPS IVCC1 — 28 — mA
power saving ICC = IVDD + IVCC1 + IVCC2
IVCC2
mode
Differential VVREF_I = 3.2V
26 DLE — –0.5 0.7 LSB
linearity error
Integral linearity
27 ILE — VVREF_I = 3.2V –1.5 0.4 LSB
error
– 10 –
CXA7000R
Description of Operation
The flow of internal operations is described below.

The digital signals input to D_IN0 to D_IN9 are internally D/A converted into approximately 1.5V (at VREF_I:
3.2V) analog signals. After that, the signal that has been demultiplexed into 6 phases is amplified by a factor of
three times, inverted at the signal center potential according to FRP, and output.
The output level relative to the digital input changes according to the following settings.
A: SIG_OFST voltage
B: VREF_I voltage
VCC
C: SIG.C voltage
A
Signal Center
A
1023
C
B
512
0 GND
Digital IN SH_OUT
1. Digital input block
The CXA7000R can be set to master/slave mode, single mode and left/light inversion. This makes it possible to
support various systems.
In master/slave mode, the even and odd data is internally selected respectively and input to the D/A converter.
2. D/A converter block
The internal D/A converter has two systems for odd-numbered and even-numbered outputs. The voltage input
from VREF_I becomes the 100% white level potential of the analog converted signal, and this amplitude is a
maximum 1.5Vp-p with respect to input data of 000h to 3FFh.
3. Sample-and-hold (S/H) block
The D/A converter outputs are input to the sample-and-hold blocks, respectively. The signals are converted from
time series signals into 6-phase cyclic parallel signals by the sample-and-hold group which is appropriately
controlled by the internal timing generator. For forward scan, the signals are output in the ascending order of
SH_OUT1, SH_OUT2, SH_OUT3 ... SH_OUT6. For reverse scan, this order is inverted and the signals are
output in descending order. Connect the signals to the LCD panel according to the order used. The timing of
each sample-and-hold pulse is shown on the following pages. These pulses are not output and are used only
inside the IC.
– 11 –
CXA7000R
Master/slave mode
Selector
D_IN1 DAC
10bit L
D_IN2 DAC_O
D_IN[9:0] D D H D S/H
D
STATUS
MCLK
MCLK/2
D_IN[9:0] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29
MCLK
D_IN1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29
D_IN2 1 3 5 7 9 11 13 15 17 19 21 23 25 27
1 3
DAC_O
DIRC: H
SH1_1
SH1_2
SH1_3
SH1_4
SH1_5
SH1_6
SH2_1_3
SH2_4_6
F/H_CNT: L CH1 to CH6 simultaneous output timing
SH3A_1_6
F/H_CNT: H CH1 to CH3 simultaneous output timing
SH3B_1_3
CH4 to CH6 simultaneous output timing
SH3B_4_6
DIRC: L
SH1_1
SH1_2
SH1_3
SH1_4
SH1_5
SH1_6
SH2_1_3
SH2_4_6
SH3A_1_6
SH3B_1_3
SH3B_4_6 CH4 to CH6 simultaneous output timing
– 12 –
CXA7000R
Single mode
DAC
10bit D_IN1 D_IN2 DAC_O
D_IN[9:0] D D S/H
D
MCLK
D_IN[9:0] –1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
MCLK
D_IN1 –2 –1 0 1 2 3 4 5 6 7 8 9 10 11 12 13
D_IN2 –3 –2 –1 0 1 2 3 4 5 6 7 8 9 10 11 12
DAC_O –1 0
1
DIRC: H
SH1_1
SH1_2
SH1_3
SH1_4
SH1_5
SH1_6
SH2_1_3
SH2_4_6
SH3A_1_6
F/H_CNT : H CH1 to CH3 simultaneous output timing
SH3B_1_3
SH3B_4_6
DIRC: L
SH1_1
SH1_2
SH1_3
SH1_4
SH1_5
SH1_6
SH2_1_3
SH2_4_6
SH3A_1_6
SH3B_1_3
SH3B_4_6
– 13 –
CXA7000R
4. Timing generator (TG) block
The internal timing generator operates by one pair of differential clock inputs (MCLK, MCLKX) and a horizontal sync
signal input (SHST), and generates the timing pulses needed by the demultiplexer block, dot inversion control pulse
and output deviation cancel circuit. The various operating modes can be designated by the pin settings.
The SHST and FRP inputs should satisfy the relationship shown in the figure below with the MCLK and
MCLKX input period as 1clk.
SHST
FRP
30clk or more 1µs or more
The CXA7000R can select various operating modes according to the timing generator block settings. These
settings are described below.
• SL_DAT (Pin 48)

Operation mode selection. Master/slave mode is selected which is common with digital input of two ICs when
set to high level, and single mode is selected with one IC when set to low level. In case of the former, connect
10-bit input as short as possible between two ICs and select which data of odd or even is obtained by STATUS
(Pin 50).
• DIRC (Pin 47)

Scan direction settings. Output is ascending order when DIRC is set to high level, and inverted to descending
order (SH_OUT1 to SH_OUT6) when set to low level. Also, the output is varied as shown below in combination
with STATUS (Pin 50).
D_IN[9:0] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SL_DAT: L
DIRC: L DIRC: H
SH_OUT1: 6 SH_OUT1: 1
SL_DAT: H
DIRC: L DIRC: H
STATUS: L
STATUS: H SH_OUT4: 6 SH_OUT4: 7
– 14 –
CXA7000R
• F/H_CNT (Pin 46)

SH_OUT output timing phase setting. When set to low level, all SH_OUT outputs are output at the same
timing. When set to high level, SH_OUT1 to SH_OUT3 and SH_OUT4 to SH_OUT6 are output at phases
offset by 1/2 clock period from each other.
SH_OUT4 to 6
SH_OUT4 to 6
SH_OUT1 to 3 SH_OUT1 to 3
GND GND
F/H_CNT: L F/H_CNT: H
• Output phase setting

The phase of each SH_OUT output can be adjusted by POSCNT[3:0] (Pins 3 to 6). The phase can be set in 16
ways by 4-bit digital input. The output phase shifts backward by the clock period units when SL_DAT is high or 1/2
clock period units when SL_DAT is low each time this setting is increased by one bit.
– 15 –
CXA7000R
5. Calibration level generator block
The CXA7000R has a built-in offset cancel circuit and generates the reference with a calibration level generator
in order to minimize the deviation between channels at the center level.
The 200h output level is generated at both the AC output high and low sides respectively when STATUS (Pin 50)
is high level, and these levels are DC output from CAL_H and CAL_L and at the same time, these are used
internally. When STATUS (Pin 50) is low level, CAL_H and CAL_L are input pins and the external offset cancel
level is input. The 200h data is forcibly inserted into the video signal while the video blanking period SHST
pulse is low level, and feedback is applied so that the output levels of all SH_OUT channels conform to CAL_H
and CAL_L during this period.
Video signal replacement period

SHST
FRP
200ns
CAL_PLS
(internal pulse) Offset cancel operation
000h
200h
SH_OUT Delayed by sample-and-hold Signal center
200h
000h
6. SID signal generator block
This circuit generates the precharge signal waveform used by the LCD panel.
The voltage input from PRG_LV (Pin 37) and SID_LV (Pin 38) is switched by the PRG pulse (Pin 39). The
PRG_LV voltage is selected when PRG is high, and the SID_LV voltage is selected when PRG is low. This
signal is then further amplified by a factor of two times and folded by the FRP pulse. The folded center voltage
is the SH_OUT center voltage (voltage set by the SIG.C pin). SID_OUT (Pin 36) is inverted when FRP is high,
and non-inverted when FRP is low.
SID_OUT cannot directly drive the precharge signal input of the LCD panel, so they should be connected via a
buffer having sufficient current supply capability.
7. VCOM potential generator block
This block sets the DC common potential for the LCD panel.
VCOM_OFST (Pin 33) sets the deviation relative to the SH_OUT center potential, which is set by SIG.C.
– 16 –
CXA7000R
Example of Representative Characteristics (VCC = 15.5V, VDD = 5.0V, Ta = 25°C)
VREF_I voltage vs. SH_OUT voltage white-black amplitude Input data vs. SH_OUT voltage
4.8 14
SH_OUT white-black amplitude voltage [V]
4.7 <Measurement conditions>

12
SIG.C = 3.75V
4.6 FRP = High
SIG_OFST = 3.6V
10
SH_OUT voltage [V]

4.5
4.4
8
4.3
6
4.2
FRP = Low
4.1 4
<Measurement conditions>
4.0
SIG.C = 3.75V
2
3.9 SIG_OFST = 3.6V
3.8 0
2.8 2.9 3.0 3.1 3.2 3.3 000h 100h 200h 300h 3FFh
VREF_I voltage [V] Input data (10 bits)
SIG.C voltage vs. SH_OUT center voltage SIG_OFST voltage vs. SH_OUT voltage
9.0 12
8.5 11
SIG_OFST = 3.6V
SH_OUT center voltage [V]
8.0 10
FRP = High
SH_OUT voltage [V]
9
7.5
8
7.0
7
6.5
6
6.0 <Measurement conditions>
5
SIG.C = 3.75V FRP = Low
5.5 4 DATA = 200h
5.0 3
2.5 3.0 3.5 4.0 4.5 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
SIG.C voltage [V] SIG_OFST voltage [V]
VCOM_OFST voltage vs. VCOM_OUT voltage

7.5
7.0 SIG.C = 3.75V
VCOM_OUT voltage [V]
6.5
6.0
5.5
5.0
4.5
0.0 1.0 2.0 3.0 4.0 5.0
VCOM_OFST voltage [V]
– 17 –
CXA7000R
SID_LV voltage vs. SID_OUT voltage PRG_LV voltage vs. SID_OUT voltage
16 16
<Measurement conditions> <Measurement conditions>
14 SIG.C = 3.75V 14 SIG.C = 3.75V
12 12
SID_OUT voltage [V]
SID_OUT voltage [V]

FRP = High FRP = High
10 10
8 8
6 6
FRP = Low FRP = Low
4 4
2 2
0 0
0 1 2 3 4 0 1 2 3 4
SID_LV voltage [V] PRG_LV voltage [V]
– 18 –
CXA7000R
Application Circuit 1 (to SVGA Panel)
VDD
20kΩ Buffer
DSD 1 Psig
CXD3526GG VDD VDD
1µF 0.1µF VDD

20kΩ 20kΩ
10Ω 20kΩ
PRG 45
VDD 0.1µF
10Ω
RGT 2 0.1µF
VCC
1Ω
47µF
24 COM
VDD 47µF
VCOM_OFST
VDD
VCOM_OUT
SID_OUT
F/H_CNT
VREF_O
PRG_LV
PVCC
SL_DAT
VREF_I
SID_LV
VCC15
DIRC
VDD5
GND
GND
PRG
PS
VDD
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
10kΩ
TEST PVCC
49 32 1Ω
STATUS SH_OUT1
50 31 7 Vsig1
10Ω D_IN9 NC
ROUT9 38 51 30 1Ω
10Ω D_IN8 SH_OUT2
ROUT8 39 52 29 5 Vsig2
10Ω D_IN7 NC
ROUT7 40 53 28 1Ω
10Ω D_IN6 SH_OUT3
ROUT6 36 54 27 3 Vsig3
10Ω D_IN5 GND
ROUT5 79 55 26
GND PGND
56 25 LCD Panel
GND PGND
57 CXA7000R 24 LCX026
10Ω D_IN4 GND
ROUT4 80 58 23 1Ω
10Ω D_IN3 SH_OUT4
ROUT3 81 59 22 2 Vsig4
10Ω D_IN2 NC
ROUT2 35 60 21 1Ω
10Ω D_IN1 SH_OUT5
ROUT1 78 61 20 4 Vsig5
10Ω D_IN0 NC
ROUT0 113 62 19 1Ω
10Ω MCLK SH_OUT6
CLKOUT 28 63 18 6 Vsig6
MCLKX PVCC
64 17
0.1µF 0.1µF 47µF
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
FRP
SHST
POSCNT0
POSCNT1
POSCNT2
POSCNT3
SHTEST
GND
GND
NC
SIG.C
SIG_OFST
CAL_L
CAL_H
GND
DCFBOFF
1µF
OPEN
10Ω VDD
FRP 118 1µF
10Ω
SHST 119
0.1µF
20kΩ
VDD
PVCC VCC VDD
0.1µF
20kΩ
15.5V 15.5V 5V
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
– 19 –
CXA7000R
Application Circuit 2 (to XGA Panel) VDD
20kΩ Buffer
DSD 1 Psig
CXD3526GG VDD VDD
1µF 0.1µF VDD

20kΩ 20kΩ
10Ω 20kΩ
PRG 45
VDD 0.1µF
10Ω
RGT 2 0.1µF
VCC
1Ω
47µF
31 COM
VDD 47µF
VCOM_OFST
VDD
VCOM_OUT
SID_OUT
F/H_CNT
VREF_O
PRG_LV
PVCC
SL_DAT
VREF_I
SID_LV
VCC15
DIRC
VDD5
GND
GND
PRG
PS
VDD
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
10kΩ
TEST PVCC
49 32 1Ω
STATUS SH_OUT1
50 31 3 Vsig1
10Ω D_IN9 NC
ROUT9 38 51 30 1Ω
10Ω D_IN8 SH_OUT2
ROUT8 39 52 29 5 Vsig3
10Ω D_IN7 NC
ROUT7 40 53 28 1Ω
10Ω D_IN6 SH_OUT3
ROUT6 36 54 27 7 Vsig5
10Ω D_IN5 GND
ROUT5 79 55 26
GND PGND
56 25
GND PGND
57 CXA7000R 24
10Ω D_IN4 GND
ROUT4 80 58 23 1Ω
10Ω D_IN3 SH_OUT4
ROUT3 81 59 22 9 Vsig7
10Ω D_IN2 NC
ROUT2 35 60 21 1Ω
10Ω D_IN1 SH_OUT5
ROUT1 78 61 20 11 Vsig9
10Ω D_IN0 NC
ROUT0 113 62 19 1Ω
10Ω MCLK SH_OUT6
MCLKX PVCC
64 17
0.1µF 0.1µF 47µF
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
FRP
SHST
POSCNT0
POSCNT1
POSCNT2
POSCNT3
SHTEST
GND
GND
NC
SIG.C
SIG_OFST
CAL_L
CAL_H
GND
DCFBOFF
10Ω
FRP 118 LCD Panel
10Ω
SHST 119 LCX029
OPEN
0.47µF 0.47µF
VDD
VDD
1µF
20kΩ 0.1µF
VCC
47µF
VDD VDD VDD VDD

VCOM_OFST
VCOM_OUT
SID_OUT
F/H_CNT
VREF_O
PRG_LV
PVCC
SL_DAT
VREF_I
SID_LV
VCC15
DIRC
VDD5
GND
GND
PRG
PS
VDD
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
10kΩ
TEST PVCC
49 32 1Ω
STATUS SH_OUT1
50 31 4 Vsig2
D_IN9 NC
51 30 1Ω
D_IN8 SH_OUT2
52 29 6 Vsig4
D_IN7 NC
53 28 1Ω
D_IN6 SH_OUT3
54 27 8 Vsig6
D_IN5 GND
55 26
GND PGND
56 25
GND PGND
57 CXA7000R 24
D_IN4 GND
58 23 1Ω
D_IN3 SH_OUT4
59 22 10 Vsig8
D_IN2 NC
60 21 1Ω
D_IN1 SH_OUT5
61 20 12 Vsig10
D_IN0 NC
62 19 1Ω
MCLK SH_OUT6
63 18 14 Vsig12
MCLKX PVCC
64 17
47µF
0.1µF 0.1µF
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
FRP
SHST
POSCNT0
POSCNT1
POSCNT2
POSCNT3
SHTEST
GND
GND
NC
SIG.C
SIG_OFST
CAL_L
CAL_H
GND
DCFBOFF
VDD
OPEN
20kΩ
0.1µF
0.47µF
VDD
0.47µF PVCC VCC VDD
20kΩ
15.5V 15.5V 5V
0.1µF
– 20 –
CXA7000R
VDD
Application Circuit 3 (to SXGA Panel)
20kΩ Buffer
DSD 1 Psig
CXD3511Q VDD VDD
1µF 0.1µF VDD

20kΩ 20kΩ
10Ω 20kΩ
PRG 161
VDD 0.1µF 2 COMR
10Ω
RGT 136 0.1µF
VCC 21 COML
1Ω
47µF
32 COM
VDD 47µF
VCOM_OFST
VDD
VCOM_OUT
SID_OUT
F/H_CNT
VREF_O
PRG_LV
PVCC
SL_DAT
VREF_I
SID_LV
VCC15
DIRC
VDD5
GND
GND
PRG
PS
VDD
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
10kΩ
TEST PVCC
49 32 1Ω
STATUS SH_OUT1
50 31 3 Vsig1
10Ω D_IN9 NC
R1OUT9 122 51 30 1Ω
10Ω D_IN8 SH_OUT2
R1OUT8 121 52 29 5 Vsig3
10Ω D_IN7 NC
R1OUT7 120 53 28 1Ω
10Ω D_IN6 SH_OUT3
R1OUT6 119 54 27 7 Vsig5
10Ω D_IN5 GND
R1OUT5 118 55 26
GND PGND
56 25
GND PGND
57 CXA7000R 24
10Ω D_IN4 GND
R1OUT4 117 58 23 1Ω
10Ω D_IN3 SH_OUT4
R1OUT3 116 59 22 9 Vsig7
10Ω D_IN2 NC
R1OUT2 113 60 21 1Ω
10Ω D_IN1 SH_OUT5
R1OUT1 112 61 20 11 Vsig9
10Ω D_IN0 NC
R1OUT0 111 62 19 1Ω
10Ω MCLK SH_OUT6
MCLKX PVCC
64 17
0.1µF 0.1µF 47µF
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
FRP
SHST
POSCNT0
POSCNT1
POSCNT2
POSCNT3
SHTEST
GND
GND
NC
SIG.C
SIG_OFST
CAL_L
CAL_H
GND
DCFBOFF
10Ω
FRP 157 LCD Panel
10Ω
SHST 159 LCX028
OPEN
0.47µF 0.47µF
VDD
VDD
1µF
20kΩ 0.1µF
VCC
47µF
VDD VDD VDD VDD

VCOM_OFST
VCOM_OUT
SID_OUT
F/H_CNT
VREF_O
PRG_LV
PVCC
SL_DAT
VREF_I
SID_LV
VCC15
DIRC
VDD5
GND
GND
PRG
PS
VDD
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
10kΩ
TEST PVCC
49 32 1Ω
STATUS SH_OUT1
50 31 4 Vsig2
10Ω D_IN9 NC
R2OUT9 110 51 30 1Ω
10Ω D_IN8 SH_OUT2
R2OUT8 109 52 29 6 Vsig4
10Ω D_IN7 NC
R2OUT7 108 53 28 1Ω
10Ω D_IN6 SH_OUT3
R2OUT6 107 54 27 8 Vsig6
10Ω D_IN5 GND
R2OUT5 106 55 26
GND PGND
56 25
GND PGND
57 CXA7000R 24
10Ω D_IN4 GND
R2OUT4 105 58 23 1Ω
10Ω D_IN3 SH_OUT4
R2OUT3 104 59 22 10 Vsig8
10Ω D_IN2 NC
R2OUT2 103 60 21 1Ω
10Ω D_IN1 SH_OUT5
R2OUT1 99 61 20 12 Vsig10
10Ω D_IN0 NC
R2OUT0 98 62 19 1Ω
MCLK SH_OUT6
63 18 14 Vsig12
MCLKX PVCC
64 17
47µF
0.1µF 0.1µF
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
FRP
SHST
POSCNT0
POSCNT1
POSCNT2
POSCNT3
SHTEST
GND
GND
NC
SIG.C
SIG_OFST
CAL_L
CAL_H
GND
DCFBOFF
VDD
OPEN
20kΩ
0.1µF
0.47µF
VDD
0.47µF PVCC VCC VDD
20kΩ
15.5V 15.5V 5V
0.1µF
– 21 –
CXA7000R
Notes on Operation
The CXA7000R has high power consumption, so be sure to take the following radiation measures.
• Use four-layer substrate.
• GND lines connected to Pins 8, 9, 24, 25, 40, 41, 56 and 57 should be as thick as possible.
– 22 –
CXA7000R
Package Outline Unit: mm
64PIN LQFP (PLASTIC)
12.0 ± 0.2
∗ 10.0 ± 0.1
48 33
49 32
(11.0)
0.5 ± 0.2
A
64 17
(0.22)
1 16
0.5
b
0.13 M + 0.2
1.5 – 0.1
0.1
0.1 ± 0.1
b = 0.18 ± 0.03 0.125 ± 0.04

0.5 ± 0.2
0˚ to 10˚
DETAIL B: PALLADIUM
DETAIL A NOTE: Dimension “∗” does not include mold protrusion.
PACKAGE STRUCTURE
PACKAGE MATERIAL EPOXY RESIN
SONY CODE LQFP-64P-L01 LEAD TREATMENT PALLADIUM PLATING
EIAJ CODE P-LQFP64-10x10-0.5 LEAD MATERIAL COPPER ALLOY
JEDEC CODE PACKAGE MASS 0.3g
– 23 – Sony Corporation

Sony CXA7000R LCD Driver Chip Optimizes Display Performance

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Sony CXA7000R LCD Driver Chip Optimizes Display Performance

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CXA7000R

Absolute Maximum Ratings (VSS = 0V)

Recommended Operating Conditions

D_IN4 58 Line inv. 23 GND

D_IN0 62 Line inv. 19 NC

Internal sample-and-hold timing

VDD VCC Output signal offset adjustment

VDD Master/slave setting when using

24, 25 PGND GND Power GND.

Electrical Characteristics Measurement Circuit

Value obtained by subtracting minimum

The flow of internal operations is described below.

1. Digital input block

2. D/A converter block

3. Sample-and-hold (S/H) block

4. Timing generator (TG) block

30clk or more 1µs or more

• SL_DAT (Pin 48)

• DIRC (Pin 47)

• F/H_CNT (Pin 46)

• Output phase setting

5. Calibration level generator block

Video signal replacement period

SH_OUT Delayed by sample-and-hold Signal center

6. SID signal generator block

7. VCOM potential generator block

Example of Representative Characteristics (VCC = 15.5V, VDD = 5.0V, Ta = 25°C)

4.7 <Measurement conditions>

SH_OUT voltage [V]

VCOM_OFST voltage vs. VCOM_OUT voltage

SID_OUT voltage [V]

Application Circuit 1 (to SVGA Panel)

1µF 0.1µF VDD

Application Circuit 2 (to XGA Panel) VDD

1µF 0.1µF VDD

VDD VDD VDD VDD

1µF 0.1µF VDD

VDD VDD VDD VDD

Package Outline Unit: mm

64PIN LQFP (PLASTIC)

b = 0.18 ± 0.03 0.125 ± 0.04

DETAIL A NOTE: Dimension “∗” does not include mold protrusion.

SONY CODE LQFP-64P-L01 LEAD TREATMENT PALLADIUM PLATING

EIAJ CODE P-LQFP64-10x10-0.5 LEAD MATERIAL COPPER ALLOY

JEDEC CODE PACKAGE MASS 0.3g

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