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Transistor Bias
Circuits
By: Syed Akhmal
Objectives
• Objectives
• Introduction
• DC operating point
• Voltage-divider bias
• Other bias methods
– Base bias
– Emitter bias
– Collector-feedback bias
• Troubleshooting
• Summary
Introduction
The term biasing is used for application of dc voltages
to establish a fixed level of current and voltage.
Transistor must be properly biased with dc voltage to
operate as a linear amplifier.
If amplifier is not biased with correct dc voltages on
input and output, it can go into saturation or cutoff when
the input signal applied.
There are several methods to establish DC operating
point.
We will discuss some of the methods used for biasing
transistors.
DC OPERATING POINT
The DC Operating Point
• The goal of amplification in most cases is to increase the
amplitude of an ac signal without altering it.
• Improper biasing can cause distortion in the output signal.
The DC Operating Point
The purpose of biasing a circuit is to establish a proper stable
dc operating point (Q-point). The dc operating point between
saturation and cutoff is called the Q-point. The goal is to set
the Q-point such that that it does not go into saturation or
cutoff when an ac signal is applied.
• Q-point of a circuit: dc operating point of amplifier
specified by voltage and current values (VCE and IC).
These values are called the coordinates of Q-point.
• Refer to figure a, given IB = 200μA and βDC=100. IC=βDCIB so
IC=20mA and
VCE VCC I C RC 10V (20mA )(220) 10 4.4 5.6V
• Figure b, VBB is increased to produce IB of 300μA and IC of
30mA.
VCE VCC I C RC 10V (30mA )(220) 10 6.6 3.4V
• Figure c, VBB is increased to produce IB of 400μA and
IC=40mA. So, VCE is:
• VCE VCC I C RC 10V (40mA )(220) 10 8.8 1.2V
DC Operating Point-DC load line
•Recall that the collector characteristic curves graphically show the
relationship of collector current and VCE for different base currents.
• When IB increases, IC increases and VCE decreases or vice-versa. Each
separate Q-point is connected through dc load line. At any point along line,
values of IB, IC and VCE can be picked off the graph.
•Dc load line intersect VCE axis at 10V, where VCE=VCC. This is cutoff point
because IB and IC zero. Dc load line also intersect IC axis at 45.5mA ideally.
This is saturation point because IC is max and VCE=0.
DC Operating Point-Linear operation
•Region between saturation and cutoff is linear region of
transistor’s operation. The output voltage is ideally linear
reproduction of input if transistor is operated in linear region.
•Let’s look at the effect a superimposed ac voltage has on the
circuit. IB vary sinusoidally 100μA above and below Q-point of
300μA. IC vary up and down 10mA of its Q-point(30mA). VCE
varies 2.2V above and below its Q-point of 3.4V.
•However, as you might already know, applying too much ac
voltage to the base would result in driving the collector current
into saturation or cutoff resulting in a distorted or clipped
waveform.
•When +ve peak is limited, transistor is in cutoff. When –ve peak
is limited, transistor is in saturation.
Variations in IC and VCE as a result of variation in IB.
Graphical load line illustration of transistor being driven into
saturation or cutoff
Graphical load line for transistor in saturation and cutoff
Example 1
• Determine Q-point in figure below and find the maximum
peak value of base current for linear operation. Assume
βDC=200.
Solution
• Q-point is defined by values of IC and VCE.
VBB VBE 10 0.7
IB 198A
RB 47k
I C DC I B 200(198 ) 39.6mA
VCE VCC I C RC 20V (39.6mA )(330) 6.93V
R2 5.6k
VB VCC 10V 3.59V
R1 R 2 15.6 k
3. So, emitter voltage
4. VE current
And emitter VB VBE 3.59 0.7 2.89V
V E 2.89
IE 5.16mA
5. Thus, RE 560
6. And VCEI Cis 5.16mA
VCE VCC I C ( RC RE ) 10 5.16m(1.56k ) 1.95V
Thevenin’s Theorem Applied to
Voltage-Divider Bias
Analysis of voltage bias for npn
transistor
• Refer to slide 27 (c)
R2
• Thevenin’s voltage VTH VCC
R R
1 2
• Thevenin’s resistance
R1 R2
RTH
R1 R2
• By KVL around BE loop,
VTH VRTH VBE VRE 0
I C DC I B
IC I E
Analysis of voltage bias for npn
transistor
• Thus,
VTH VBE
IB
RTH DC RE
VTH VBE
IE
RE ( RTH / DC )
Voltage-Divider Bias for pnp
Transistor
Pnp transistor has opposite polarities from npn. To obtain
pnp, required negative collector supply voltage or with a
positive emitter supply voltage. The analysis of pnp is
basically the same as npn.
Analysis of voltage bias for pnp
transistor
• Base voltage R1
VB VEE
R1 R2 DC RE
• Emitter voltage
VE VB VBE
• By Ohm’s Law,
V EE V E
IE
RE
• And, VC I C RC
V EC V E VC
Thevenin’s Theorem Applied to
Voltage-Divider Bias
• Refer to slide 30, (a)
• Thevenin’s voltage R2
VTH VCC
R1 R2
• Thevenin’s resistance
R1 R2
RTH
R1 R2
• By KVL around BE loop,
VTH VE VEB VRTH 0
I C DC I B
IC I E
Analysis of voltage bias for pnp
transistor
• Thus,
VTH VEB
IB
RTH DC RE
VTH VEB
IE
RE ( RTH / DC )
Thevenin’s Theorem Applied to
Voltage-Divider Bias
• Refer to slide 30, (b)
• Thevenin’s voltage R2
VTH VCC
R1 R2
• Thevenin’s resistance
R1 R2
RTH
R1 R2
• By KVL around BE loop,
VTH VEE VRE VEB VRTH 0
I C DC I B
IC I E
Analysis of voltage bias for pnp
transistor
• Thus,
VEE VTH VEB
IB
RTH DC RE
BASE BIAS
EMITTER BIAS
COLLECTOR-FEEDBACK BIAS
Other bias methods - Base Bias
• KVL apply on base circuit.
VCC – VRB – VBE = 0 or VCC – IBRB – VBE =0
• Solving for IB,
VCC V BE
IB
RB