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04.10.08
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Portable audio • Industrial wireless • Portable video • Visual robotic development • Embedded in ED

Portable
Media Keeps
Playing and
41
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TECHNOLOGY REPORT

p| Invisible Links Revolutionize

Industrial Communications

ENGINEERING ESSENTIALS

47

and...
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Starts With A Balanced Design

DESIGN SOLUTION

p| 64 Mixed-Signal Processors Can Aid

Visual Robotic Development

Tune in to E NGINEERING TV. COM IC

C designers find innovative
ways
ay ttoo extend battery life in
portable
rtabl media players and
ltim
multimedia phones.
34
April 10, 2008 Vol. 56, No. 7

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 techview

MicroSemi’s PD64001 PSE controller sup-
Only Bud offers the ports current levels up to 720 mA (36 W at
full range of cabinets: the input to the CAT5 cable, 30 W at the PD,
Low Cost to Fully assuming 50 V at the PSE) using 802.11at
Featured to two-event classification. Designs requiring up
Customizable.
to 60 W can use a four-pair architecture using
two devices. The PD64001 was sampling in
February, and it will be in production by the
end of the quarter.
The Akros AS1135 is a PD controller imple-
menting the two-event physical-layer classifi-
cation functionality of the 802.3at standard.
Two-event classification allows the PD to
recognize whether it is connected to Type
1 (802.3af/13W) or Type 2 (802.3at/30W)
power sourcing equipment. It also informs
the PSE that it’s safe to increase power deliv-
ered to the PD from 13 to 30 W.
Furthermore, the AS1135 provides “AT
Detect” functionality on a logic output pin.
This enables the system microcontroller
to self-configure the networked appliance
based on the power delivery capability of the
network. It’s possible to set the switching
frequency of the integrated dc-dc controller
anywhere between 100 and 500 kHz. It is
currently sampling as well.
The availability of real PoE Plus chips poses
at least two interesting questions. The first
is how enthusiastic PD OEMs will be about
implementing a scheme that requires them to
write additional application software to com-
municate status information to the PSE—for
example, “My user will/will not require video-
screen operation for this call, so give me my
full power allotment now.” The second is
how enthusiastic IT managers will be about
supporting a phone system whose power
capabilities were sized based on statistical
analyses of usage.
Answering the first question, Akros
CEO Simon Prutton says that the company is
dealing with video-over-IP OEMs that
are now developing products that will use
the new chips. With respect to the second,
he says that Ethernet switch makers are going
forward with product development, although
they seem to be hedging their bets by
building in a robust safety factor when they
size their power supplies.
DON TUITE
AKROS SILICON • www.akrossilicon.com
MICROSEMI • www.microsemi.com
ED ONLINE 18558

SERDES IP Releases Tackle Top Speeds

High-speed design and serial buses used for chip-to-chip communications seem to
go hand in hand nowadays. Whether you’re talking signal integrity, printed-circuit
board (PCB) routability, or a slew of other factors, it just makes sense. Therefore, the
ready availability of reliable serializaer/deserializer (SERDES) intellectual property
(IP) is imperative.

Avago SERDES Offerings From eSilicon

Data rate 90 nm1 65 nm2
Protocol standards
(Gbits/s) (G, G-OD) (G+, G+OD)
Gigabit Ethernet 1.25 * *
PCI Express Gen 1 and 2 2.5 and 5.0 * *
10GBase-CX4 3.125 (x4 lanes) * *
XAUI/10GBase-KX4 3.125 (x4 lanes) * *
6.25 (LR and SR;
CEI-6G * *
MR)
XFI (10-Gbit Ethernet) 10.3125 *
Fibre Channel 1.0626, 2.125,
* *
(8x, 4x, 2x, 1x) 4.25, 8.5
Fibre Channel
TEL: 440-946-3200 10.51875 *
(10GFC Serial)
FAX: 440-951-4015
5.0, 6.25, 7.5,
saleseast@budind.com Chip-to-Chip/Backplane *
10.3125
www.budind.com/3
1. Frequencies higher than 6.25G require G-OD process 2. Frequencies higher than 7.5G require G+OD process

READER SERVICE 86 04.10.08 ELECTRONIC DESIGN

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 techview

TX RX

Data Lane 0 TX SERDES data 0 Data Lane 0 RX SERDES data 0 SLE’s Interlaken
Format MUX Format MUX
Control Lane 1 TX SERDES data 1 Control Lane 1 RX SERDES data 1 IP core scales
Statistics Lane 2 TX SERDES data 2 Statistics Lane 2 RX SERDES data 2 from one to 24
… … … …
lanes, with each
Lane N TX SERDES data N Lane N RX SERDES data N lane capable
Debug Debug Debug Debug of raw data
Flow-control clk Flow-control clk
Flow control Flow-control Flow-control sync Flow control Flow-control rates between
Flow-control sync
format Flow-control data format Flow-control data 3.125 and 6.375
Config Gbits/s.

Interrupt Config

Tundra Semiconductor’s Silicon Logic Engineering (SLE)
division addresses this need with an Interlaken IP core capable
of 150 Gbits/s (see the figure). Originally developed by Cortina
Systems, the Interlaken protocol is a royalty-free specification
that combines the SPI-4.2 and XAUI architectures, which have
seen high adoption rates in networking systems.
SLE’s core is fully scalable, making it a good fit for future net-
work equipment designs, such as switches, routers, and storage
devices. Each one of its 24 lanes is capable of 3.125 to 6.375
Gbits/s. When all 24 lanes are chugging at full speed, the raw
Never before could you get high performance in such
a small package. A precision timing crystal and a CMOS
oscillator in a ceramic SMD, just 3.2 x 1.5 x1.0mm.
• 5.5V to 1.2V operation for reliable
operation – even on low battery
• Max. current: 0.5μA @ 3.0V
• Short start-up time of 0.5sec max.
• RoHS Compliant; 100% lead-free
• Ideal for cell phones, smart phones,
GPS, PDAs, and portable instruments
READER SERVICE 116
data rate equals just over 150 Gbits/s, which is the fastest rate
possible according to SLE.
Other features include support for up to 64k channels, a con-
tinuous meta frame for programming frequency allowing for
lane alignment, and 64B/67B data encoding and scrambling.
SLE’s Interlaken IP core should pop into just about any ASIC,
and it works with off-the-shelf SERDESs from most vendors.
It’s available through SLE’s sales channel.
If network storage is your game, then you realize that data
bandwidth and processing expectations have skyrocketed over
the past few years, with power con-
sumption and form factor expected to
remain constant. Again, the trend is to
include a high-speed SERDES to help
meet these requirements.
Recently, eSilicon partnered with
Avago to license its embedded SERDES
cores targeted at the network storage,
communications, and high-perfor-
mance computing markets. The multi-
tude of SERDES offerings includes 90-
and 65-nm CMOS processes available
from TSMC.
This sixth-generation suite of offer-
ings has been road tested in many
OV-7604-C7
Low-Power products. Avago offers its cores at rates
Clock Oscillator
from 1.0625 to 10.51875 Gbits/s, and
the company claims they provide strong
signal integrity and jitter performance.
Other features include an adaptive feed-
back equalizer in the receiver, program-
mable transmitter pre-emphasis, and a
bit error rate of less than 10-17. A broad
Call: 847-818-XTAL (9825) selection of Avago SERDES cores over
email: sales @microcrystal.com a range of data rates and protocol stan-
www.microcrystal.com dards is available from eSilicon (see the
table). DANIEL HARRIS
SILICON LOGIC ENGINEERING
siliconlogic.com/asic_fpga_interlaken_
core.asp
ESILICON
esilicon.com/offerings/avago.php
ED ONLINE 18559

04.10.08 ELECTRONIC DESIGN

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