Вы находитесь на странице: 1из 95

UNIVERSIDAD NACIONAL MAYOR DE SAN MARCOS

FACULTAD DE INGENIERIA DE SISTEMAS E INFORMATICA

TEMA : REGISTROS, CONTADORES…

CURSO: CIRCUITOS DIGITALES

ING. ARMANDO FERMIN PEREZ

CIUDAD UNIVERSITARIA DE SAN MARCOS


Registros y Contadores

Introducción
Registros de almacenamiento. Banco de registros
Registros de desplazamiento
Contadores asíncronos
Contadores síncronos
Contadores módulo N
Registros y Contadores

A partir de los biestables estudiados en el tema


anterior,se realizarán circuitos secuenciales más
complejos:
• registros (biestables D)
• contadores (biestables J-K)
de amplio uso en sistemas digitales en general
y arquitectura de computadores en particular.
Registros y Contadores
• Las operaciones más frecuentes en sistemas
digitales son el almacenamiento y la transferencia
de información.
• Registros de almacenamiento.
• Registros de desplazamiento serie o paralelo.
• Otros circuitos básicos son los contadores.
• Dependiendo del mecanismo de activación se
clasifican en: contadores asíncronos o
contadores síncronos.
• Dentro de cada clasificación, dependiendo del
número de biestables y la forma en que se
conecten contarán un secuencia distinta.
Registros de Almacenamiento

• Se forman a partir de biestables de tipo D


conectados en cascada
• Un registro con n biestables es capaz de
almacenar n bits
• Son circuitos síncronos, y todos los biestables
están gobernados por la misma señal de reloj
Registros de Almacenamiento de 4 bits
Registros de Almacenamiento de 4 bits
Group of storage elements read/written as a unit

4-bit register constructed from 4 D FFs


Shared clock and clear lines

Schematic Shape

171
Q3 9
12 CLK
Q3 10
13 CLR
Q2 7
Q2 6
11 D3 Q1 2
5 D2 Q1 3
4 D1 Q0 1
14 D0 Q0 15

TTL 74171 Quad D-type FF with Clear


(Small numbers represent pin #s on package)
Banco de Registros: Definición
Banco de Registros: Escritura
Banco de Registros: Ejemplo de Escritura
Banco de Registros: Lectura
Banco de Registros: Ejemplo de Lectura
Banco de Registros Completo
Banco de Registros: Abstracción
Banco de Registros: Abstracción
Memoria: Diagrama de Bloques
Memoria: Símbolo Lógico
Registros de Desplazamiento
• Son circuitos síncronos que cuando se activan, se
desplazan los bits de sus biestables “hacia la
derecha” o “hacia la izquierda”
• Clasificación:
• Entrada Serie y Salida Paralelo.
• Entrada Serie y Salida Serie.
• Entrada Paralelo y Salida Paralelo.
• Entrada Paralelo y Salida Serie.
• Registros Universales.
• Entrada serie: entra un bit en cada pulso de reloj
• Salida serie: sale un bit en cada pulso de reloj
• Entrada paralelo: entran todos los bits del dato en el
mismo pulso de reloj
• Salida paralelo: salen todos los bits del dato en el
mismo pulso de reloj
Registros de Desplazamiento
Storage + ability to circulate data among storage elements

Q1 Q2 Q3 Q4

1 0 0 0
Shift
0 1 0 0
Shift
0 0 1 0
Shift
0 0 0 1

Shift from left storage


element to right neighbor
on every hi-to-lo transition
on shift signal

Wrap around from rightmost


element to leftmost element
Master Slave FFs: sample inputs while
clock is high; change outputs on
falling edge
Registro de Desplazamiento Genérico
Parallel in (Y)
Parallel out (X)

Serial in n-Bit shift Serial out


register

Preset control
Shift pulse
Clear control
(a)

Parallel in (Y) Parallel out (X)

Serial out Serial in n-Bit shift


n-Bit shift
register register

Preset control
Shift pulse Shift pulse

Clear control Clear control


(b) (c)
Registros de Desplazamiento SISO
(9)
Clear
(8)
Clock
(1)
Serial A Clear Clear Clear Clear Clear Clear Clear Clear
R QA R QB R QC R QD R QE R QF R QG R QH
inputs B
(2) CK CK CK CK CK CK CK CK
S QA S QB S QC S QD S QE S QF S QG S QH

(3) (4) (5) (6) (10) (11) (12) (13)


Output Output Output Output Output Output Output Output
QA QB QC QD QE QF QG QH
(a) (Serial output)

Clear
Serial A
inputs B
Clock
QA
QB
QC
Outputs QD
QE
QF
QG
Clear Clear
(b)
Registros de Desplazamiento
Registros de Desplazamiento SIPO
Registros de Desplazamiento
Conversión de Paralelo a Serial

Parallel Parallel
Inputs Outputs

Serial
transmission

Shifters well suited for serial-to-parallel conversions,


such as terminal to computer communications
Contadores

• Un contador de n bits se implementa utilizando n


biestables de tipo T

• Clasificación de los contadores:


• Asíncronos y síncronos
• Ascendentes y descendentes
• Módulo n
Contadores Asíncronos: Implementación
Contadores Asíncronos: Ascendente de 4 bits
Contadores Asíncronos: Descendente de 4 bits
Contadores Asíncronos: Asc/Des de 4 bits
Contadores Asíncronos: Asc/Des de 4 bits
Contadores Síncronos: Implementación

• La señal externa de reloj está conectada a todos los


biestables, por lo tanto, los activa a todos de manera
simultánea

• Implementación:
• La entrada de reloj al contador se conecta a las
entradas de reloj de todos los biestables
• La entradas de datos (J-K ó T) del biestable de
menor peso se conecta a un “1” fijo
• Se precisan puertas adicionales para implementar
la lógica que indique cuando deben voltear su
estado los biestables
Contadores Síncronos: Ejemplo
Contadores Módulo N

• El módulo de un contador es el número de cuentas


distintas que realiza dicho contador

• Para implementar un contador de módulo N, se elige


un contador con n bits (ascendente o descendente,
según proceda), siendo 2(n-1)<N<2(n) y se eliminan las
cuentas sobrantes, añadiendo lógica combinacional

• Por ejemplo, para implementar un contador asíncrono


módulo diez ascendente o contador de décadas, que
cuente los diez dígitos decimales se necesita:
un contador ascendente de cuatro bits, ya que
2(4-1)<10<2(4), y se añade la lógica combinacional
requerida
Contador Módulo N: Asíncrono mod-10
Contador Asíncrono Ascendente Módulo 10
Diagrama de bloques de un Timer Digital
Minutes Seconds

1 Pulse/hour 1 Pulse/minute

¸6 ¸ 10 ¸6 ¸ 10

Clear

Start/Stop
¸5 ¸ 12

Pulse
generator 1 Pulse/second

Power line
Counter Design Procedure
Introduction
This procedure can be generalized to implement ANY finite state
machine

Counters are a very simple way to start:


no decisions on what state to advance to next
current state is the output

Example: 3-bit Binary Upcounter

Decide to implement with


Toggle Flipflops

What inputs must be


presented to the T FFs
to get them to change
to the desired state bit?

This is called
"Remapping the Next
State Function"
Counter Design Procedure
Example Continued

K-maps for Toggle Resulting Logic Circuit:


Inputs: +
C
CB
A 00 01 11 10

0 1 1 1 1

1 1 1 1 1 QA QB QC
TS Q T S Q T S Q
B CLK Q CLK Q CLK Q
TA = 1 R R R
\Reset
C
CB
Count
A 00 01 11 10

0 0 0 0 0
Timing Diagram:
1 1 1 1 1
100
B
TB = A \Reset

CB
C QC
A 00 01 11 10
QB
0 0 0 0 0
QA
1 0 1 1 0
Count
B
TC = A • B
Counter Design Procedure
More Complex Count Sequence

Step 1: Derive the State Transition Diagram


Count sequence: 000, 010, 011, 101, 110

Step 2: State Transition Table

Note the Don't Care conditions


Counter Design Procedure
More Complex Count Sequence

Step 3: K-Maps for Next State Functions


Counter Design Procedure
More Complex Count Sequence

Step 3: K-Maps for Next State Functions


Counter Design Procedure
More Complex Counter Sequencing
Step 4: Choose Flipflop Type for Implementation
Use Excitation Table to Remap Next State Functions

Toggle Excitation
Table

Remapped Next State


Functions
Counter Design Procedure
More Complex Counter Sequencing
Remapped K-Maps

TC = A C + A C = A xor C

TB = A + B + C

TA = A B C + B C
Counter Design Procedure
More Complex Counter Sequencing

Resulting Logic:
5 Gates
10 Literals +
Flipflop connections

Timing Waveform:
100

Count
\Reset
0 0 0 0 1 1 0
C
B 0 0 1 1 0 1 0

A 0 0 0 1 1 0 0
Self-Starting Counters
Start-Up States
At power-up, counter may be in any possible state

Designer must guarantee that it (eventually) enters a valid state

Especially a problem for counters that validly use a subset of states

Self-Starting Solution:
Design counter so that even the invalid states
eventually transition to valid state

Two Self-Starting State Transition Diagrams


for the Example Counter
Self-Starting Counters
Deriving State Transition Table from Don't Care Assignment
Implementation with Different Kinds of FFs
R-S Flipflops
Continuing with the 000, 010, 011, 101, 110, 000, ... counter example

RS Excitation Table

Remapped Next State Functions


Implementation with Different Kinds of FFs
RS FFs Continued
CB CB
A 00 01 11 10 A 00 01 11 10
0 0

1 1

RC SC RC =
CB CB SC =
A 00 01 11 10 A 00 01 11 10
0 0 RB =
1 1 SB =
RB SB RA =
CB CB SA =
A 00 01 11 10 A 00 01 11 10
0 0

1 1

RA SA
Implementation with Different Kinds of FFs
RS FFs Continued

RC = A

SC = A

RB = A B + B C

SB = B

RA = C

SA = B C
Implementation with Different Kinds of FFs
RS FFs Continued

C B A
\A R Q RB R Q C R Q
CLK CLK CLK
A S Q \B S Q SA S Q
\C \B \A
Count

A
RB B SA
C
B \C

Resulting Logic Level Implementation:


3 Gates, 9 Literals + Flipflop connections
using RB = B (A + C)

Could be 4 Gates, 10 Literals + FF connections


Implementation with Different Kinds of FFs
J-K FFs

J-K Excitation Table

Remapped Next State Functions


Implementation with Different Kinds of FFs
J-K FFs Continued
CB CB
A 00 01 11 10 A 00 01 11 10
0 0

1 1
JC =
JC KC
KC =
CB CB
A 00 01 11 10 A 00 01 11 10
JB =
0 0

1 1
KB =

JB KB JA =

KA =
CB CB
A 00 01 11 10 A 00 01 11 10
0 0

1 1

JA KA
Implementation with Different Kinds of FFs
J-K FFs Continued

JC = A

KC = A

JB = 1

KB = A + C

JA = B C

KA = C
Implementation with Different Kinds of FFs
J-K FFs Continued
+

C B A
A J Q J Q JA J Q
CLK CLK CLK
\A K Q KB K Q C K Q
\C \B \A
Count

A B JA
C KB \C

Resulting Logic Level Implementation:


2 Gates, 7 Literals + Flipflop Connections
Implementation with Different Kinds of FFs
D FFs
Simplest Design Procedure: No remapping needed!

DC = A

DB = A C + B

DA = B C

C B A
A D Q DB D Q DA D Q

CLK Q CLK Q CLK Q


\C \B \A
Count

\C
DB B
\A \C DA
\B

Resulting Logic Level Implementation:


3 Gates, 6 Literals + Flipflop connections
Implementation with Different Kinds of FFs
Comparison

T FFs well suited for straightforward binary counters

But yielded worst gate and literal count for this example!

No reason to choose R-S over J-K FFs: it is a proper subset of J-K

R-S FFs don't really exist anyway

J-K FFs yielded lowest gate count

Tend to yield best choice for packaged logic where gate count is key

D FFs yield simplest design procedure

Best literal count

D storage devices very transistor efficient in VLSI

Best choice where area/literal count is the key


Asynchronous vs. Synchronous Counters
Ripple Counters
Deceptively attractive alternative to synchronous design style

Count signal ripples from left to right

State transitions are not sharp!


Can lead to "spiked outputs" from combinational logic
decoding the counter's state  No use practically!
Asynchronous vs. Synchronous Counters
Cascaded Synchronous Counters with Ripple Carry Outputs

First stage RCO


enables second stage
for counting
RCO asserted
soon after stage
enters state 1111

also a function
of the T Enable

Downstream stages
lag in their 1111 to
0000 transitions

Affects Count period


and decoding logic
Asynchronous vs. Synchronous Counters
The Power of Synchronous Clear and Load
Starting Offset Counters:
e.g., 0110, 0111, 1000, 1001, 1010, 1011, 1100, 1101, 1111, 0110, ...
100

D C B A
Clock
Load
R Q Q QQ D
1 C D CBA L C
6 O C O C
3 L B
A L
P T K DCBA D R A

+ + Load 0 1
Use RCO signal to trigger Load of a new state
0110
is the state Since 74163 Load is synchronous, state changes
to be loaded only on the next rising clock edge
Asynchronous vs. Synchronous Counters
Offset Counters Continued
Ending Offset Counter:
e.g., 0000, 0001, 0010, ..., 1100, 1101, 0000

CLR

D C B A

Clear signal takes effect on the rising count edge


1 R Q Q Q Q
D C B A L
6 CC
O O C
3 L A L
P T K DCBA D R

1
0

Decode state to
determine when to Replace '163 with '161, Counter with Async Clear
reset to 0000 Clear takes effect immediately!
Moore and Mealy Machine
Definitions
State
Register
Moore Machine

Xi Combinational
Comb. Outputs are function
Inputs Logic for
Logic for
solely of the current
state
Outputs
Next State
(Flip-flop Zk

Outputs change
Inputs) Outputs

Clock synchronously with


state changes
state
feedback

Mealy Machine
Xi Zk
Combinational Outputs
Outputs depend on
Inputs
Logic for
Outputs and state AND inputs
Next State
Input change causes
State an immediate output
State Register Clock Feedback
change
Asynchronous outputs
Moore and Mealy Machine
State Diagram Equivalents

Moore N D + Reset
Reset/0
(N D + Reset)/0
Mealy
Machine Reset
0¢ 0¢ Machine
[0]
Reset Reset/0
N N/0
5¢ 5¢
ND D N D/0 D/0
[0]
N N/0
10¢ 10¢
D D/1
[0] ND N D/0
N+D N+D/1
15¢ 15¢

[1] Reset Reset/1

Outputs are associated Outputs are associated


with State with Transitions
Moore and Mealy Machine

States vs. Transitions


Mealy Machine typically has fewer states than Moore Machine
for same output sequence
0
Asserts its output 0 0/0
whenever at least two 0
1’s in sequence [0]
0/0 1/0
Same I/O behavior
0 1
0 1
1
Different # of states 1/1
[0]
1
2

[1] 1
F F

T T

F F

T T

F Equivalent
ASM Charts
Basic Design Approach
Example: Vending Machine FSM
General Machine Concept:
deliver package of gum after 15 cents deposited

single coin slot for dimes (10 cents), nickels (5 cents)

no change

Step 1. Understand the problem:


Draw a picture!

Block Diagram N
Coin
Vending Open Gum
Sensor D
Machine Release
Reset FSM Mechanism

Clk
Vending Machine Example
Step 2. Map into more suitable abstract representation

Tabulate typical input sequences:


three nickels
nickel, dime Reset
dime, nickel S0
two dimes
two nickels, dime
N D
Draw state diagram:
S1 S2
Inputs: N, D, reset

Output: open N D
D N

S3 S4 S5 S6

[open] [open] [open]


N D

S7 S8
[open] [open]
Vending Machine Example
Step 3: State Minimization
Present Inputs Next Output
Reset

State D N State Open
0¢ 0 0 0¢ 0
N 0 1 5¢ 0

1 0 10¢ 0
D 1 1 X X
5¢ 0 0 5¢ 0
N 0 1 10¢ 0
10¢ 1 0 15¢ 0
D 1 1 X X
N, D 10¢ 0 0 10¢ 0
15¢
0 1 15¢ 0
1 0 15¢ 0
[open]
1 1 X X
15¢ X X 15¢ 1
reuse states
whenever Symbolic State Table
possible
Vending Machine Example
Step 4: State Encoding
Present State Inputs Next State Output
Q1 Q0 D N D1 D0 Open
0 0 0 0 0 0 0
0 1 0 1 0
1 0 1 0 0
1 1 X X X
0 1 0 0 0 1 0
0 1 1 0 0
1 0 1 1 0
1 1 X X X
1 0 0 0 1 0 0
0 1 1 1 0
1 0 1 1 0
1 1 X X X
1 1 0 0 1 1 1
0 1 1 1 1
1 0 1 1 1
1 1 X X X
Vending Machine Example
Step 5. Choose FFs for implementation
D FF easiest to use

D1 D0 Open

Q1
D D1 Q1
D Q

Q0 CLK \ Q1
RQ
N
\reset
D1 = Q1 + D + Q0 N
N
\ Q0 OPEN
D0 = N Q0 + Q0 N + Q1 N + Q1 D
Q0
\N
D0 D Q0
Q1
Q OPEN = Q1 Q0
CLK \ Q0
N RQ
Q1 \reset
D
8 Gates
Vending Machine Example
Step 5. Choosing FF for Implementation
J-K FF

Present State Inputs Next State J1 K1 J0 K 0


Q1 Q0 D N D1 D0
0 0 0 0 0 0 0 X 0 X
0 1 0 1 0 X 1 X
1 0 1 0 1 X 0 X
1 1 X X X X X X
0 1 0 0 0 1 0 X X 0
0 1 1 0 1 X X 1
1 0 1 1 1 X X 0
1 1 X X X X X X
1 0 0 0 1 0 X 0 0 X
0 1 1 1 X 0 1 X
1 0 1 1 X 0 1 X
1 1 X X X X X X
1 1 0 0 1 1 X 0 X 0
0 1 1 1 X 0 X 0
1 0 1 1 X 0 X 0
1 1 X X X X X X

Remapped encoded state transition table


Vending Machine Example
Implementation:

J1 = D + Q0 N

K1 = 0

J0 = Q0 N + Q1 D

K0 = Q1 N

N
Q0 J Q Q1
D \ Q1
CLK K RQ
\ Q0

N
OPEN
Q1

D Q0
J Q
\ Q1 CLK
\ Q0
KR Q
N

\reset 7 Gates
Problems

Four Case Studies:

Finite String Pattern Recognizer

Complex Counter with Decision Making

Traffic Light Controller

Digital Combination Lock

We will use state diagrams and ASM Charts


Finite String Pattern Recognizer
A finite string recognizer has one input (X) and one output (Z).
The output is asserted whenever the input sequence …010…
has been observed, as long as the sequence 100 has never been
seen.

Step 1. Understanding the problem statement

Sample input/output behavior:


X: 00101010010
Z: 00010101000

X: 11011010010
Z: 00000001000
Finite String Recognizer
Step 2. Draw State Diagrams/ASM Charts for the strings that must be
recognized. I.e., 010 and 100.

Moore State Diagram


Reset signal places
FSM in S0

Outputs 1 Loops in State


Finite String Recognizer
Exit conditions from state S3:
if next input is 0 then have …0100 (state S6)
if next input is 1 then have …0101 (state S2)
Finite String Recognizer
Exit conditions from S1: recognizes strings of form …0 (no 1 seen)
loop back to S1 if input is 0

Exit conditions from S4: recognizes strings of form …1 (no 0 seen)


loop back to S4 if input is 1
Finite String Recognizer
S2, S5 with incomplete transitions

S2 = …01; If next input is 1, then string could be prefix of (01)1(00)


S4 handles just this case!

S5 = …10; If next input is 1, then string could be prefix of (10)1(0)


S2 handles just this case!

Final State Diagram


Finite String Recognizer
Review of Process:

Write down sample inputs and outputs to understand specification

Write down sequences of states and transitions for the sequences


to be recognized

Add missing transitions; reuse states as much as possible

Verify I/O behavior of your state diagram to insure it functions


like the specification
Complex Counter
A sync. 3 bit counter has a mode control M. When M = 0, the counter
counts up in the binary sequence. When M = 1, the counter advances
through the Gray code sequence.

Binary: 000, 001, 010, 011, 100, 101, 110, 111


Gray: 000, 001, 011, 010, 110, 111, 101, 100

Valid I/O behavior:


Mode Input M Current State Next State (Z2 Z1 Z0)
0 000 001
0 001 010
1 010 110
1 110 111
1 111 101
0 101 110
0 110 111
Complex Counter
One state for each output combination
Add appropriate arcs for the mode control
S0 000

S1 001
H.Z 0

0 1
M

S2 010 S3 011
H.Z 1 H.Z 1
H.Z 0

0
M
1
M
1
0
S6 110
H.Z 2 S4 100
H.Z 1 H.Z 2

1
S7 111 M
H.Z 2 0
H.Z 1
H.Z 0
S5 101
H.Z 2
H.Z 0
0 1
M

0 1
M
Traffic Light Controller

A busy highway is intersected by a little used farmroad. Detectors


C sense the presence of cars waiting on the farmroad. With no car
on farmroad, light remain green in highway direction. If vehicle on
farmroad, highway lights go from Green to Yellow to Red, allowing
the farmroad lights to become green. These stay green only as long
as a farmroad car is detected but never longer than a set interval.
When these are met, farm lights transition from Green to Yellow to
Red, allowing highway to return to green. Even if farmroad vehicles
are waiting, highway gets at least a set interval as green.

Assume you have an interval timer that generates a short time pulse
(TS) and a long time pulse (TL) in response to a set (ST) signal. TS
is to be used for timing yellow lights and TL for green lights.
Traffic Light Controller
Picture of Highway/Farmroad Intersection:

Farmroad

C
HL
FL
Highway

Highway

FL
HL C

Farmroad
Traffic Light Controller
Tabulation of Inputs and Outputs:
Input Signal Description
reset place FSM in initial state
C detect vehicle on farmroad
TS short time interval expired
TL long time interval expired

Output Signal Description


HG, HY, HR assert green/yellow/red highway lights
FG, FY, FR assert green/yellow/red farmroad lights
ST start timing a short or long interval

Tabulation of Unique States: Some light configuration imply others


State Description
S0 Highway green (farmroad red)
S1 Highway yellow (farmroad red)
S2 Farmroad green (highway red)
S3 Farmroad yellow (highway red)
Traffic Light Controller
Refinement of ASM Chart:
Start with basic sequencing and outputs:

S0 S3
H.HG H.HR
H.FR H.FY

S1 S2
H.HY H.HR
H.FR H.FG
Traffic Light Controller
Determine Exit Conditions for S0:
Car waiting and Long Time Interval Expired- C · TL

S0 S0
H.HG H.HG
H.FR H.FR

C · TL
0 0
TL TL •  C

1 1
0
C H.ST

H.ST S1
H.HY
H.FR
S1
H.HY
H.FR

Equivalent ASM Chart Fragments


Traffic Light Controller
S1 to S2 Transition:
Set ST on exit from S0
Stay in S1 until TS asserted
Similar situation for S3 to S4 transition

S1 S2
H.HY H.ST H.HR
H.FR H.FG

0 1
TS
Traffic Light Controller
S2 Exit Condition: no car waiting OR long time interval expired

S0 S3
H.HG H.HR
H.FR H.ST H.FY

0 1 0
TL  • C  TS

H.ST H.ST

S1 S2
H.HY H.ST H.HR
H.FR H.FG

0 1 0
TS TL + C
1

Complete ASM Chart for Traffic Light Controller


Traffic Light Controller
Compare with state diagram:
TL + C
Reset
S0: HG
S0
TL•C/ST TS/ST S1: HY
TS
S2: FG
S1 S3

TS S3: FY
TS/ST
TL + C/ST
S2

TL • C

Advantages of ASM Charts:

Concentrates on paths and conditions for exiting a state

Exit conditions built up incrementally, later combined into


single Boolean condition for exit

Easier to understand the design as an algorithm


Digital Combination Lock

"3 bit serial lock controls entry to locked room. Inputs are RESET,
ENTER, 2 position switch for bit of key data. Locks generates an
UNLOCK signal when key matches internal combination. ERROR
light illuminated if key does not match combination. Sequence is:
(1) Press RESET, (2) enter key bit, (3) Press ENTER, (4) repeat (2) &
(3) two more times."

Problem specification is incomplete:


how do you set the internal combination?
exactly when is the ERROR light asserted?

Make reasonable assumptions:


hardwired into next state logic vs. stored in internal register
assert as soon as error is detected vs. wait until full combination
has been entered

Our design: registered combination plus error after full combination


Digital Combination Lock
Understanding the problem: draw a block diagram
RESET

Operator Data ENTER UNLOCK


KEY-IN
Combination
Lock FSM ERROR
L0
Internal
Combination L1
L2

Inputs: Outputs:
Reset Unlock
Enter Error
Key-In
L0, L1, L2
Digital Combination Lock
Enumeration of states:

what sequences lead to opening the door?


error conditions on a second pass
START state plus three key COMParison states

START
START entered on RESET

Exit START when ENTER is pressed


1
Reset

0
Enter
0
1
COMP0

Continue on if Key-In matches L0


N
KI = L0
Y
Digital Combination Lock
COMP0 IDLE1

Path to unlock:

N 0
KI = L 0 Enter
Y 1
IDLE0 COMP2
Wait for
Enter Key press

0 N
Enter KI = L2

1 Y
COMP1 DONE

H.Unlock

N 0
Compare Key-IN KI = L1 Reset

Y 1

START
Digital Combination Lock
Now consider error paths

Should follow a similar sequence as UNLOCK path, except


asserting ERROR at the end:

IDLE0' IDLE1' ERROR3


H.Error

0 0 0
Enter Enter Reset

1 1 1
ERROR1 ERROR2

START

COMP0 error exits to IDLE0'

COMP1 error exits to IDLE1'

COMP2 error exits to ERROR3


Reset + Enter
Digital Combination Lock Reset
Start

Reset • Enter

Comp0
KI = L0 KI ° L0

Enter Enter
Idle0 Idle0'

Enter Enter

Comp1 Error1
Equivalent State Diagram KI ° L1
KI = L1
Enter
Enter
Idle1 Idle1'

Enter Enter

Comp2 Error2

KI = L2 KI ° L2

Reset Reset
Done Error3
[Unlock] [Error]

Reset Reset

Start Start