Dept.

of ECE, Bharati Vidyapeeth’s College of Engineering-New Delhi

MINI PROJECT SYNOPSYS (Automatic car parking system using VHDL)
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Vivesh Singh(07711502816); Yatender Kumar (07811502816); Prashant Singh (41111502816);
Ujjwal Gupta (42211502816) .
Automatic Car Parking System using VHDL
Proposed Project Summary: (font 13 times new roman)
Gone are the days when we were seeing only a few number of vehicles on road. Out of them, the
number of cars can be equated to almost to a very small number. But with increasing
urbanization and population, in the last few decades, there has been a considerable and enormous
rise in the number of vehicles. Also, there has been a substantial rise in the number of four-
wheelers. Due to this increased number, the problem of parking has come out to be an important
issue. In huge malls, educational institutes, organizations the limited parking space and increased
vehicles have led parking problems. People usually waste huge time in parking vehicles at such
places. In order to cater to this problem here is an attempt to design the system known as
“Automatic Car Parking System”. The system automatically checks the availability of free slots
and parks customer vehicles. Also, it tells the customer to remember the number of parking slot
at which their vehicle is parked so that it can find their vehicle and remove it from the parked
place. In order to design the proposed circuit, a Verilog HDL code is implemented which is then
further synthesized on FPGA to get the required design.
Problem Statement: (font 13 times new roman)
The main cause of parking problems worldwide is ever increasing population and with it the
number of vehicles. The place available for parking is limited but the number of vehicles
increasing on road daily has no check. According to the recent trends, there has been an
exponential rise in the sale of cars. The number of cars sold worldwide increased tremendously
from 39.2 million in 1999 to 81.57 million in 2018. In 20 years the sales were raised by a value
as high as approximately equal 40 million
Expected Project Outcomes: (font 13 times new roman)
The primary aim of this project is to solve the problem of parking and to avoid time wastage of
people visiting big organization and congested places. For designing this system and for
hardware synthesis, a code is written in Verilog HDL. This is then converted to hardware design
or synthesized using Xilinx ISE. The code written makes use of certain useful special features of
Verilog Language such as functions, tasks, blocking and unblocking statements, fork join, repeat,
etc. Use of these features makes a coding a lot more generalized and helps in executing complex
statements.
Project Tasks Description: (font 13 times new roman)
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Date Date

S.No Task Methodology Resource Required Start Expected End

Date Date

I. STUDENT 1- VIVESH SINGH 07711502816

1 Object Xiling IDE,
detection
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II. STUDENT 2- YATENDER KUMAR 07811502816
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III. STUDENT 3 – PRASHANT SINGH 41111502816
1 Font size 11
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IV. STUDENT 4-
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References:
[1] Bhavana Chendika et al. Int. Journal of Engineering Research and Applications ISSN:
2248-9622, Vol. 5, Issue 7, (Part - 3) July 2015, pp.01-03

[2] Hua-Chun Tan; Jie Zhang; Xin-Chen Ye; Hui-Ze Li; Pei Zhu; Qing-Hua Zhao;(2009) ,
"Intelligent car-searching system for large park," Machine Learning and Cybernetics, 2009
International Conference on , vol.6, no., pp.3134-3138.

[3] Srikanth, S.V.; Pramod, P.J.; Dileep, K.P.; Tapas, S.; Patil, M.U.; Sarat, C.B.N.;(2009) , "Design and
Implementation of a Prototype Smart PARKing (SPARK) System Using Wireless Sensor Networks,"
Advanced Information Networking and Applications Workshops, 2009. WAINA '09. International
Conference on , pp.401406.

[4] Gongjun Yan; Olariu, S.; Weigle, M.C.; Abuelela, M.; (2008) "SmartParking: A Secure and Intelligent
Parking System Using NOTICE," Intelligent Transportation Systems, 2008. ITSC 2008 11th International
IEEE Conference

[5] Insop Song; Gowan, K.; Nery, J.; Han, H.; Sheng, T.; Li, H.; Karray, F.; ,(2006) "Intelligent Parking
System Design Using FPGA," Field Programmable Logic and Applications, 2006. FPL '06. International
Conference on, pp.1-6.
Guide Name : DC WALA
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