Advanced Digital System Design

Question Bank for CAT - 1

1) What are different data objects used in VHDL? Explain with suitable
example.

2) Write short notes on : (i) Architecture (ii) Entity (iii) Package

3) Discuss various levels of abstractions in VHDL

4) What are the advantages of VHDL over other conventional programming

languages ?

5) Explain the different design units with their syntax in brief

6) Explain in brief history of VHDL and give its advantages

7) Explain VHDL development flow with suitable flow chart

8) Explain different approaches in VHDL

9) Differentiate between conditional and selected signal assignment

statements

10) What do you mean by Port mapping? What are the types? Explain each
with syntax

11) All VHDL Codes based on Conditional Signal Assignment, Selected

Signal Assignment, Structural, Generate statement, Testbench,
Case statement