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CORDIC Algorithm

Prof. Kris Gaj

Outlines

Introduction

Basic Idea

CORDIC Principles

Hardware Implementation

FPGA & ASIC Results

Conclusion

Introduction

CORDIC (COordinate Rotation DIgital

Computer)

Introduced in 1959 by Jack E. Volder

Efficient to compute sin, cos, tan, sinh,

cosh, tanh

Its an Hardware Efficient Algorithm

Iterative Algorithm for Circular Rotation

No Multiplication

Delay/Hardware cost comparable to

division or square rooting.

Why CORDIC ?

• Table lookup

• Polynomial approximations

• CORDIC

a clear winner when :

• Hardware Multiplier is unavailable (eg. microcontroller)

• You want to save the gates required to implement

(eg. FPGA)

Basic Ideas

Embedding of elementary function

evaluation as a generalized rotation

operation.

Decompose rotation operation into

successive basic rotations.

Each basic rotation can be realized

with shift-and-add arithmetic

operations.

CORDIC Principles Y

Rotate (1,0) by φ degrees φ X

to get (x,y): x=cos(φ), y=sin(φ) cos φ

x′ = x. cos(φ ) − y. sin(φ ) (x’,y’)

(x,y)

y′ = y. cos(φ ) + x. sin(φ ) φ

X

• Rearrange as:

x′ = cos(φ ).[x − y. tan(φ )] sin(φ )

Note : = tan(φ )

y′ = cos(φ ).[ y + x. tan(φ )] cos(φ )

Key Idea

step is of size

Expansion Vector K

K = ∏cosφ depends on rotation

angle φ1, φ2 , φ3 …… φn

always K is a constant that can be

pre-computed

K = 1.646760258121

Iterative rotations

Zi is introduced to keep track of the angle that

has been rotated (z0 = φ)

di = -1 if zi < 0

= 1 otherwise

Example: Rewriting Angles in Terms of αi

Y

45°

Find αi such that tan(αi)=2-i : (or,

αi=tan-1(2-i) )

Example: φ=30.0° 30°

• Start with α0 = 45.0 (> 30.0)

• 45.0 – 26.6 = 18.4 (< 30.0)

• 18.4 + 14.0 = 32.4 (> 30.0)

• 32.4 – 7.1 = 25.3 (< 30.0)

• 25.3 + 3.6 = 28.9 (< 30.0) X

• 28.9 + 1.8 = 30.7 (> 30.0)

• ...

φ = 30.0

≈ 45.0 – 26.6 + 14.0 – 7.1 + 3.6

+ 1.8 – 0.9 + 0.4 – 0.2 + 0.1

= 30.1

Sequential/Iterative CORDIC

Cont..

Maximum number of Clock Cycles to

calculate output

certain FPGA’s due to high Fan-in

Parallel/Cascaded CORDIC

Parallel CORDIC Cont..

Combinational circuit

More Delay, but processing time is

reduced as compared to iterative

circuit.

Shifters are of fixed shift, so they

can be implemented in the wiring.

Constants can be hardwired instead

of requiring storage space.

Pipeline Architecture

32

Bit

Parallel Pipelined CORDIC

Parallel CORDIC can be pipelined by inserting

registers between the adders stages.

In most FPGA architectures there are already

registers present in each logic cell, so pipeline

registers has no hardware cost.

Number of stages after which pipeline register is

inserted can be modeled, considering clock

frequency of system.

When operating at greater clock period power

consumption in later stages reduces due to lesser

switching activity in each clock period.

Redundant Addition

Main delay in critical path of the

CORDIC iteration is that of the

adder.

To reduce this delay we can use

redundant adders.

In signed digit number system

addition becomes carry free.

Example

r = 10 , digit set [0,9]

5 7 8 2 4 9

+ 6 2 9 3 8 9

11 9 17 5 12 18 [0,18]

11 9 16 5 12 16 [0,16]

0 0 1 0 0 2 [0,2]

11 10 16 5 14 16 [0,16]

Example

r = 2, digit set [-1,0,1]

1 0 0 -1 7 in decimal

1 0 -1 0 6 in decimal

1 0 -1 0 Ci

0 0 0 1 -1 Ui

1 0 -1 1 -1 13 in decimal

Language, Platform, Tools

Language – Verilog HDL

Platform

• Xilinx FPGA

• ASIC – TSMC LibraryAldec Active-HDL

Tools

• Aldec Active-HDL, Synplify Pro, Xilinx ISE

(Windows Platform)

• Cadence – Verilog-XL & Simvision

• Synopsys Design Analyzer (Unix Platform)

FPGA(3s200ft256) Results

LUT 597 864 867

Gate 5833 10371 14536

Count

Path 9.7 9.7

Delay

ASIC (TSMC) Results

Sequential Parallel Pipeline Parallel

– SD

Adder

Area 9138 39019 62937 356015

W W

Arrival 9.7 28.3 9.7 7.82

Time

Clock Frequency

FPGA – 85 MHz

ASIC – 150Mhz

Application

CORDIC sine/cosine generators in satellite data

processing systems – attitude determination

Cordic modules has been proposed for calculation of

Legendre Polynomials. Increase in speed 40% compared to s/w

running on 333Mhz Pentium

frequency based upon an original reference

frequency.

Verification

C code was used to generate test vectors

360○= 232

1○ = 232 = (0B60B60)16

360○

i.e 30○ = 232 x 30 =(15555555)16

360

Isreal Koren

Output Waveform - Parallel

Output Waveform - Pipeline

Status of Design

Written – 100 %

Functional Simulation – 100%

Timing Simulation – 50%

Analyzed for Speed and Area – 80%

Further Optimization

Area Optimized – If adders are

shared.

CORDIC algorithm

Problem

Difficulty in implementation of

Redundant Adders.

Conclusion

A trade- off speed/area will determine

the right structural approach to

CORDIC FPGA implementation for an

application

References

Computer Arithmetic – B. Parhami

Digital Arithmetic – Milos.E

FPGA based computers – R.Andraka

FPGA Implementation of Sine and

Cosine Generators using the CORDIC

algorithm.

Computer Arithmetic – I.Koren

(SD Adder)

Thank You !

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