Vostro 1450 Dell Inspiron 14 n4050 Intel dv14hrmb PDF

5 4 3 2 1
Enrico Caruso 14
D
Muxless/UMA Schematics Document D
Sandy Bridge
Intel PCH
2011-04-07
C C
REV : A00
DY : None Installed
UMA: UMA ONLY installed
PSL: KBC795 PSL circuit for 10mW solution installed.
B
10mW: External circuit for 10mW solution installed. B
DIS: MUXLESS solution installed.

Surge: For GO Rural config stuff.
GIGA: For GIGA LAN config stuff.
HDMI: For HDMI config stuff.
DIS_CRT: Pure DIS install
A <Core Design> A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Cover Page
Size Document Number Rev
A3
Enrico Caruso 14 A00
Date: Wednesday, April 13, 2011 Sheet 1 of 105
5 4 3 2 1
5 4 3 2 1
##OnMainBoard Block Diagram SYSTEM DC/DC

INPUTS
APL5916
OUTPUTS
48
CPU DC/DC
VT1316+1314
INPUTS OUTPUTS
42~44
VRAM gDDR3 900NHz

(Discrete/UMA co-lay) DCBATOUT 0D85V_S0 DCBATOUT
SYSTEM DC/DC
VCC_CORE
TPS51218 45
1GB (128Mx16x4) Project code: 91.4IU01.001 INPUTS OUTPUTS
4
512MB (64Mx16x4)
D
88,89,90,91
PCB P/N : 48.4IU16.0SC DCBATOUT 1D05V_VTT
D
gDDR3 Revision : 10315-SC SYSTEM DC/DC

TPS51125 41
900MHz Intel CPU INPUTS OUTPUTS
DDRIII 1066/1333 Channel A 5V_AUX_S5
DDRIII Slot 0 3D3V_AUX_S5
15 DCBATOUT 5V_S5
Sandy Bridge 1066/1333
Seymou-XT S3 PCIe x 8
3D3V_S5
15V_S5
(Discrete only)
DDRIII 1066/1333 Channel B DDRIII Slot 1 SYSTEM DC/DC
14 46
1066/1333 TPS51216R
83.84,85,86,87 INPUTS OUTPUTS
1D5V_S3
4,5,6,7,8,9,10 DCBATOUT 0D75V_S0
10/100 /1000 LOM RJ45 DDR_VREF_S3
PCIE x 1
Realtek RTL8111E (Giga LAN) CONN 59 GFX DC/DC
31 44
FDIx4x2 DMIx4 Realtek RTL8105E (10M/100M) VT1316+1317
C
1GB/s 802.11a/b/g INPUTS OUTPUTS C
PCIE x 1 Mini-Card DCBATOUT VCC_GFXCORE

WLAN+BT3.064
PCIE VGA
CRT CRT RT8208B 92
50
Intel 100MHz
INPUTS OUTPUTS
2.5Gbps
LCD LVDS
PCH USB 2.0 x 1 DCBATOUT VGA_CORE
49
Cougar Point TI CHARGER
BQ24707 40
HDMI HDMI 14 USB 2.0/1.1 ports USB 2.0 USB 2.0 x 1 CAMERA INPUTS OUTPUTS
51 49 +DC_IN_S5
ETHERNET (10/100/1000Mb) 480Mbps +PBATT DCBATOUT
High Definition Audio
SD/MMC/MS/ CardReader SATA ports (6) M/B
SYSTEM DC/DC
USB2.0 USB 2.0 x 1 APW7153B 47
MS Pro 74 Realtek PCIE ports (8) USB x1 (Left) 61
32 INPUTS OUTPUTS
RTS5138 LPC I/F
LPC Bus
B ACPI 1.1 3D3V_S5 1D8V_S0 B
33MHz USB 2.0 x 2 I/O board
Audio board Azalia USB x2 (Right) 82 SYSTEM DC/DC
AZALIA G9731 93
CODEC 24MHz 17,18,19,20,21,22,23,24,25 KBC INPUTS OUTPUTS
Internal Analog MIC
1D5V_S3 1V_VGA_S0
58
IDT 92HD87 NUVOTON 3D3V_S0 1D8V_VGA_S0
29 NPCE795BA0DX 27
Switches
INPUTS OUTPUTS
HP1 PS/2 PS/2
Thermal 1D5V_S3 1D5V_S0
82 5V_S5 5V_S0
ENE P2800
SPI
SATA
3Gbps
3D3V_S5 3D3V_S0
SATA
MIC IN 28
Touch Int.
PCB LAYER
PAD KB ENE P2793
L1:Top L4:Signal
2CH SPEAKER 69 69 Fan
28 L2:GND L5:VCC
Flash ROM L3:Signal L6:Bottom
58
A HDD ODD <Core Design> A
56 56 4MB 60
Wistron Corporation
Title
Block Diagram
A3 A00
Enrico Caruso 14
5 4 3 2 1
A B C D E
PCH Strapping Huron River Schematic Checklist Rev.0_7 Processor Strapping Huron River Schematic Checklist Rev.0_7
Name Schematics Notes Pin Name Strap Description Configuration (Default value for each bit is Default
SPKR Reboot option at power-up 1 unless specified otherwise) Value
Default Mode: Internal weak Pull-down.
- 10-k 
No Reboot Mode with TCO Disabled: Connect to Vcc3_3 with 8.2-k
weak pull-up resistor.
 CFG[2] PCI-Express Static 1: Normal Operation.
Lane Reversal 0: Lane Numbers Reversed 15 -> 0, 14 -> 1, ... 1
INIT3_3V# Weak internal pull-up. Leave as "No Connect".
Disabled - No Physical Display Port attached to
GNT3#/GPIO55 GNT[3:0]# functionality is not available on Mobile. CFG[4] 1: Embedded DisplayPort.
4 GNT2#/GPIO53 Mobile: Used as GPIO only
Enabled - An external Display Port device is
0 4
GNT1#/GPIO51 Pull-up resistors are not required on these signals. 0: connectd to the EMBEDDED display Port
If pull-ups are used, they should be tied to the Vcc3_3power rail.
CFG[6:5] PCI-Express 11 : x16 - Device 1 functions 1 and 2 disabled
Enable Danbury: Connect to Vcc3_3 with 8.2-k? weak pull-up resistor. Port Bifurcation 10 : x8, x8 - Device 1 function 1 enabled ;
SPI_MOSI function 2 disabled
Straps 11
Disable Danbury:Left floating, no pull-down required. 01 : Reserved - (Device 1 function 1 disabled ;
function 2 enabled)
00 : x8, x4, x4 - Device 1 functions 1 and 2
Enable Danbury: Connect to +NVRAM_VCCQ with 8.2-kohm enabled
weak pull-up resistor [CRB has it pulled up
NV_ALE with 1-kohm no-stuff resistor] CFG[7] PEG DEFER TRAINING 1: PEG Train immediately following xxRESETB de assertion
1
0: PEG Wait for BIOS for training
Disable Danbury:Leave floating (internal pull-down)
NC_CLE DMI termination voltage. Weak internal pull-up. Do not pull low.
Low (0) - Flash Descriptor Security will be overridden. Also, Voltage Rails
POWER PLANE VOLTAGE DESCRIPTION
when this signals is sampled on the rising edge of PWROK
then it will also disable Intel ME and its features. 5V_S0 5V
ACTIVE IN
SATA Table
HAD_DOCK_EN# High (1) - Security measure defined in the Flash Descriptor will be enabled. 3D3V_S0 3.3V
1D8V_S0 1.8V
/GPIO[33] Platform design should provide appropriate pull-up or pull-down depending on 1D5V_S0 1.5V SATA
3 the desired settings. If a jumper option is used to tie this signal to GND as 1D05V_VTT 1.05V
Pair Device
3
required by the functional strap, the signal should be pulled low through a weak 0D85V_S0 0.95 - 0.85V
0D75V_S0 0.75V
pull-down in order to avoid asserting HDA_DOCK_EN# inadvertently. VCC_CORE 0.35V to 1.5V
Note: CRB recommends 1-kohm pull-down for FD Override. There is an internal VCC_GFXCORE 0.4 to 1.25V S0 0 HDD1
pull-up of 20 kohm for DA_DOCK_EN# which is only enabled at boot/reset for 1D8V_VGA_S0 1.8V
3D3V_VGA_S0 3.3V CPU Core Rail 1 N/A
strapping functions. 1V_VGA_S0 1V Graphics Core Rail
2 N/A
HDA_SDO Weak internal pull-down. Do not pull high. Sampled at rising edge of RSMRST#. 3 N/A
5V_USBX_S3 5V
HDA_SYNC Weak internal pull-down. Do not pull high. Sampled at rising edge of RSMRST#. 1D5V_S3 1.5V S3 ODD
DDR_VREF_S3 0.75V
4
Low (1) - Intel ME Crypto Transport Layer Security (TLS) cipher suite with no 5 N/A
GPIO15 confidentiality High (1) - Intel ME Crypto Transport Layer Security (TLS) cipher BT+ 6V-14.1V AC Brick Mode only
suite with confidentiality DCBATOUT 6V-14.1V
Note : This is an un-muxed signal. 5V_S5 5V All S states
5V_AUX_S5 5V
This signal has a weak internal pull-down of 20 kohm which is enabled when PWROK is low. 3D3V_S5 3.3V
Sampled at rising edge of RSMRST#. 3D3V_AUX_S5 3.3V
CRB has a 1-kohm pull-up on this signal to +3.3VA rail.
3D3V_LAN_S5 3.3V WOL_EN Legacy WOL
GPIO8 on PCH is the Integrated Clock Enable strap and is required to be pulled-down
GPIO8 using a 1k +/- 5% resistor. When this signal is sampled high at the rising edge of
RSMRST#, Integrated Clocking is enabled, When sampled low, Buffer Through Mode is 3D3V_AUX_KBC 3.3V DSW, Sx ON for supporting Deep Sleep states
enabled.
2 Default = Do not connect (floating) 2
Powered by Li Coin Cell in G3
High(1) = Enables the internal VccVRM to have a clean supply for 3D3V_AUX_S5 3.3V G3, Sx and +V3ALW in Sx
GPIO27 analog rails. No need to use on-board filter circuit.
Low (0) = Disables the VccVRM. Need to use on-board filter
circuits for analog rails.
USB Table SMBus ADDRESSES

PCIE Routing
Pair Device
I 2 C / SMBus Addresses HURON RIVER ORB
0 X LANE1 X
Device Ref Des Address Hex Bus
1 USB Ext. port 2 (MB) LANE2 LAN
2 X EC SMBus 1 BAT_SCL/BAT_SDA
Battery BAT_SCL/BAT_SDA
3 X CHARGER BAT_SCL/BAT_SDA LANE3 X
EC SMBus 2 SML1_CLK/SML1_DATA
4 X PCH LANE4 Wireless
SML1_CLK/SML1_DATA
eDP SML1_CLK/SML1_DATA
5 CARD READER
6 X
PCH SMBus
SO-DIMMA (SPD) PCH_SMBDATA/PCH_SMBCLK LANE5 X
SO-DIMMB (SPD) PCH_SMBDATA/PCH_SMBCLK
7 X PCH_SMBDATA/PCH_SMBCLK
1
Digital Pot
G-Sensor PCH_SMBDATA/PCH_SMBCLK LANE6 X DN15ATI Whistler
1
8 USB Ext. port 3 MINI PCH_SMBDATA/PCH_SMBCLK
PCH_SMBDATA/PCH_SMBCLK
9 USB Ext. port 1 LANE7 X Wistron Corporation
10 X Taipei Hsien 221, Taiwan, R.O.C.
LANE8 X
11 Mini Card1 (WLAN+BT) Title
12 CAMERA Table of Content

13 X A3
5 4 3 2 1
SSID = CPU
Signal Routing Guideline:
PEG_ICOMPO keep W/S=12/15 mils and routing length less than 500 mils.
PEG_ICOMPI & PEG_RCOMPO keep W/S=4/15 mils and routing length less than 500 mils.
1D05V_VTT
CPU1A 1 OF 9
J22 PEG_IRCOMP_R R401 1 2 24D9R2F-L-GP
PEG_ICOMPI
Note:
19 DMI_TXN[3:0]
DMI_TXN0 B27
SANDY PEG_ICOMPO J21
H22
DMI_RX#0 PEG_RCOMPO
D Intel DMI supports both Lane DMI_TXN1
DMI_TXN2
B25
A25
DMI_RX#1 D
Reversal and polarity inversion DMI_TXN3 B24
DMI_RX#2
K33
but only at PCH side. This is DMI_RX#3 PEG_RX#0
19 DMI_TXP[3:0] PEG_RX#1 M35
enabled via a soft strap. DMI_TXP0 B28 DMI_RX0 PEG_RX#2 L34
DMI_TXP1 B26 J35
DMI_RX1 PEG_RX#3
DMI
DMI_TXP2 A24 J32
DMI_TXP3 DMI_RX2 PEG_RX#4
B23 DMI_RX3 PEG_RX#5 H34
19 DMI_RXN[3:0] PEG_RX#6 H31
DMI_RXN0 G21 G33
DMI_RXN1 DMI_TX#0 PEG_RX#7 PEG_RXN7
E22 DMI_TX#1 PEG_RX#8 G30 PEG_RXN7 83
DMI_RXN2 F21 F35 PEG_RXN6
DMI_TX#2 PEG_RX#9 PEG_RXN6 83
DMI_RXN3 D21 E34 PEG_RXN5
DMI_TX#3 PEG_RX#10 PEG_RXN5 83
E32 PEG_RXN4
19 DMI_RXP[3:0] PEG_RX#11 PEG_RXN4 83
DMI_RXP0 G22 D33 PEG_RXN3
DMI_TX0 PEG_RX#12 PEG_RXN3 83
DMI_RXP1 D22 D31 PEG_RXN2
PCI EXPRESS* - GRAPHICS

DMI_RXP2 F20 B33 PEG_RXN1
DMI_RXP3 C21 C32 PEG_RXN0
PEG_RX0 J33
PEG_RX1 L35
19 FDI_TXN[7:0] PEG_RX2 K34
FDI_TXN0 A21 H35
FDI_TXN1 FDI0_TX#0 PEG_RX3
H19 FDI0_TX#1 PEG_RX4 H32
Note: FDI_TXN2 E19 FDI0_TX#2 PEG_RX5 G34
FDI_TXN3 F18 G31
Intel(R) FDI
Intel FDI supports both Lane FDI0_TX#3 PEG_RX6
FDI_TXN4 B21 F33
Reversal and polarity inversion FDI_TXN5 C20
FDI1_TX#0 PEG_RX7
F30 PEG_RXP7
but only at PCH side. This is FDI1_TX#1 PEG_RX8 PEG_RXP7 83
FDI_TXN6 D18 E35 PEG_RXP6
FDI1_TX#2 PEG_RX9 PEG_RXP6 83
C enabled via a soft strap. FDI_TXN7 E17 FDI1_TX#3 PEG_RX10 E33
F32
PEG_RXP5
PEG_RXP4
PEG_RXP5 83
NOTE.
C
PEG_RX11 PEG_RXP4 83
D34 PEG_RXP3
19 FDI_TXP[7:0] FDI_TXP0 PEG_RX12 PEG_RXP2
PEG_RXP3 83 If PEG is not implemented, the RX&TX pairs can be left as No Connect
A22 FDI0_TX0 PEG_RX13 E31 PEG_RXP2 83
FDI_TXP1 G19 C33 PEG_RXP1
FDI0_TX1 PEG_RX14 PEG_RXP1 83
FDI_TXP2 E20 FDI0_TX2 PEG_RX15 B32 PEG_RXP0
PEG_RXP0 83 PEG Static Lane Reversal
FDI_TXP3 G18
FDI_TXP4 FDI0_TX3
B20 FDI1_TX0 PEG_TX#0 M29
FDI_TXP5 C19 M32
FDI_TXP6 FDI1_TX1 PEG_TX#1
D19 FDI1_TX2 PEG_TX#2 M31
FDI_TXP7 F17 L32
FDI1_TX3 PEG_TX#3
PEG_TX#4 L29
19 FDI_FSYNC0 J18 FDI0_FSYNC PEG_TX#5 K31
Note: 19 FDI_FSYNC1 J17 FDI1_FSYNC PEG_TX#6 K28
Lane reversal does not apply to PEG_TX#7 J30
H20 J28 PEG_C_TXN7 C409 1DIS 2 SCD22U10V2KX-1GP PEG_TXN7
FDI sideband signals. 19 FDI_INT FDI_INT PEG_TX#8
H29 PEG_C_TXN6 C410 1DIS 2 SCD22U10V2KX-1GP PEG_TXN6 PEG_TXN7 83
PEG_TX#9 PEG_C_TXN5 C411 SCD22U10V2KX-1GP PEG_TXN5 PEG_TXN6 83
19 FDI_LSYNC0 J19 FDI0_LSYNC PEG_TX#10 G27 1DIS 2 PEG_TXN5 83
H17 E29 PEG_C_TXN4 C412 1DIS 2 SCD22U10V2KX-1GP PEG_TXN4
19 FDI_LSYNC1 FDI1_LSYNC PEG_TX#11 PEG_TXN4 83
F27 PEG_C_TXN3 C413 1DIS 2 SCD22U10V2KX-1GP PEG_TXN3
PEG_TX#13 D28 1DIS 2 PEG_TXN2 83
F26 PEG_C_TXN1 C415 1DIS 2 SCD22U10V2KX-1GP PEG_TXN1
PEG_TX#15 E25 1DIS 2 PEG_TXN0 83
1D05V_VTT R402 1 2 24D9R2F-L-GP DP_COMP A18 EDP_COMPIO
A17 EDP_ICOMPO PEG_TX0 M28
1 R403 2 eDP_HPD B16 EDP_HPD PEG_TX1 M33
10KR2J-3-GP M30
DY PEG_TX2
L31
PEG_TX3
C15 EDP_AUX PEG_TX4 L28
D15 K30
B Signal Routing Guideline: EDP_AUX#
eDP PEG_TX5
PEG_TX6 K27 B
EDP_ICOMPO keep W/S=12/15 mils and routing PEG_TX7 J29
C17 J27 PEG_C_TXP7 C425 1DIS 2 SCD22U10V2KX-1GP PEG_TXP7
length less than 500 mils. F16
EDP_TX0 PEG_TX8
H28 PEG_C_TXP6 C426 1DIS 2 SCD22U10V2KX-1GP PEG_TXP6 PEG_TXP7 83
EDP_COMPIO keep W/S=4/15 mils and routing EDP_TX1 PEG_TX9 PEG_C_TXP5 C427 SCD22U10V2KX-1GP PEG_TXP5 PEG_TXP6 83
C16 EDP_TX2 PEG_TX10 G28 1DIS 2 PEG_TXP5 83
length less than 500 mils. G15 EDP_TX3 PEG_TX11 E28 PEG_C_TXP4 C428 1DIS 2 SCD22U10V2KX-1GP PEG_TXP4
PEG_TXP4 83
F28 PEG_C_TXP3 C429 1DIS 2 SCD22U10V2KX-1GP PEG_TXP3
PEG_TX12 PEG_C_TXP2 C430 SCD22U10V2KX-1GP PEG_TXP2 PEG_TXP3 83
C18 EDP_TX#0 CPU1 PEG_TX13 D27
PEG_C_TXP1 C431
1DIS 2
SCD22U10V2KX-1GP PEG_TXP1 PEG_TXP2 83
E16 EDP_TX#1 PEG_TX14 E26 1DIS 2 PEG_TXP1 83
D16 D25 PEG_C_TXP0 C432 1DIS 2 SCD22U10V2KX-1GP PEG_TXP0
EDP_TX#2 PEG_TX15 PEG_TXP0 83
NOTE. F15 EDP_TX#3
Processor strap CFG[4] should be pulled low to enable Embedded DisplayPort.
SANDY SKT-BGA989C470395-1H180
62.10055.421
Stuff to disable internal graphics 2nd = 62.10040.771
function for power saving.
NOTE:
Select a Fast FET similar to 2N7002E whose rise/

fall time is less than 6 ns. If HPD on eDP interface is
disabled, connect it to CPU VCCIO via a 10-k pull-Up
resistor on the motherboard.
DN15ATI Whistler
A A
Wistron Corporation
Title
CPU (PCIE/DMI/FDI)
A3
5 4 3 2 1
SSID = CPU CPU1B 2 OF 9 Disabling Guidelines:
If motherboard only supports external graphics:
SANDY Connect DPLL_REF_SSCLK on Processor to GND through
A28 1K +/- 5% resistor.
BCLK CLK_EXP_P 20
MISC
CLOCKS
18 H_SNB_IVB# C26 SNB_IVB# BCLK# A27 CLK_EXP_N 20 Connect DPLL_REF_SSCLK# on Processor to VCCP
1D05V_VTT through 1K +/- 5% resistorpower (~15 mW) may be
1 SKTOCC#_R AN34 RN502
wasted.
TPAD14-GP TP501 SKTOCC#
R501 A16 CLK_DP_P_R 4 1
H_PROCHOT# DPLL_REF_SSCLK
1 2 DPLL_REF_SSCLK# A15 CLK_DP_N_R 3 2 1D05V_VTT
D 62R2J-GP SRN1KJ-7-GP X01-0210 MergeR512 R514 D

1
1 H_CATERR# AL33
TPAD14-GP TP502 CATERR#
C502
SC47P50V2JN-3GP
2
THERMAL
1R502 2
AN33 R8 4K99R2F-L-GP SM_DRAMRST# 37
22,27 H_PECI PECI SM_DRAMRST#
CRB : 47pf
DDR3
MISC
CEKLT:43pf R513
H_PROCHOT#_R SM_RCOMP_0 R506 1
27,40,42 H_PROCHOT# 1 2 AL32 PROCHOT# SM_RCOMP0 AK1 2 140R2F-GP
A5 SM_RCOMP_1 R507 1 2 25D5R2F-GP
56R2J-4-GP SM_RCOMP1 SM_RCOMP_2 R508 1
SM_RCOMP2 A4 2 200R2F-L-GP
Connect EC to PROCHOT# through inverting OD buffer.
22,36,85 H_THERMTRIP# AN32 THERMTRIP#
Signal Routing Guideline:
SM_RCOMP keep routing length less than 500 mils.
AP29 XDP_PRDY# 1
PRDY# TP511 TPAD14-GP
AP27 XDP_PREQ# 1
PREQ# TP512 TPAD14-GP
11/16 remove TP for layout space
AR26 XDP_TCLK
TCK
PWR MANAGEMENT
XDP_TMS
JTAG & BPM

TMS AR27
AM34 AP30 XDP_TRST#
19 H_PM_SYNC PM_SYNC TRST#
22,36 H_CPUPWRGD 1R504 2H_CPUPWRGD_R TDI AR28 XDP_TDI

0R0402-PAD AP26 XDP_TDO
TDO 1D05V_VTT
1R503 2 AP33 UNCOREPWRGOOD 12/6 swap net for layout
10KR2J-3-GP
C X01-0127 Add C504 for noise couple. C5041 2
SCD1U10V2KX-5GP AL35 XDP_DBRESET# RN501 C
R505 2 VDDPWRGOOD DBR# XDP_TDI
19,37 PM_DRAM_PWRGD 1 V8 SM_DRAMPWROK 1 8
0R2J-2-GP XDP_TMS 2 7
DY AT28 XDP_BPM0 1 XDP_TDO 3 6
BPM#0 TP503 TPAD14-GP
37 VDDPWRGOOD AR29 XDP_BPM1 1 XDP_TCLK 4 5
AR30 XDP_BPM2 1
R510 1 2 BUF_CPU_RST# AR33 AT30 XDP_BPM3 1 SRN51J-1-GP
18,27,31,65,71,83 PLT_RST# RESET# BPM#3 TP506 TPAD14-GP
AP32 XDP_BPM4 1
1K5R2F-2-GP AR31 XDP_BPM5 1 XDP_TRST# R511 1 2 51R2J-2-GP
1
AT31 XDP_BPM6 1
R509 AR32 XDP_BPM7 1
1
750R2F-GP
C501 CPU1
DY SC220P50V2KX-3GP
2
62.10055.421
3D3V_S0
2nd = 62.10040.771
19 XDP_DBRESET# XDP_DBRESET# 1 2 R516

10KR2J-3-GP
B B
1D05V_VTT
3D3V_S0
1
R518
DY
1
75R2J-1-GP
Buffered reset to CPU DYC503
2
U501 SCD1U10V2KX-5GP
2
1 IN B VCC 5
2
18,27,31,65,71,83 PLT_RST# IN A DY
3 4 BUFO_CPU_RST# 1 2 BUF_CPU_RST#
GND OUT Y R517 DY43R2J-GP
1
74VHC1G09DFT2G-GP
73.01G09.AAH DYR515
0R2J-2-GP
2
A <Core Design>
A
Wistron Corporation
Title
CPU (THERMAL/CLOCK/PM )
A3
5 4 3 2 1
SSID = CPU
CPU1C 3 OF 9 CPU1D 4 OF 9
SANDY
AB6
SANDY AE2
M_A_DQ[63:0] SA_CLK0 M_A_DIM0_CLK_DDR0 15 M_B_DQ[63:0] SB_CLK0 M_B_DIM0_CLK_DDR0 14
15 M_A_DQ[63:0] SA_CLK#0 AA6 M_A_DIM0_CLK_DDR#0 15 14 M_B_DQ[63:0] SB_CLK#0 AD2 M_B_DIM0_CLK_DDR#0 14
M_A_DQ0 C5 V9 M_B_DQ0 C9 R9
M_A_DQ1 SA_DQ0 SA_CKE0 M_A_DIM0_CKE0 15 M_B_DQ1 SB_DQ0 SB_CKE0 M_B_DIM0_CKE0 14
D D5 SA_DQ1 A7 SB_DQ1 D
M_A_DQ2 D3 M_B_DQ2 D10
M_A_DQ3 SA_DQ2 M_B_DQ3 SB_DQ2
D2 SA_DQ3 C8 SB_DQ3
M_A_DQ4 D6 AA5 M_B_DQ4 A9 AE1
M_A_DQ5 SA_DQ4 SA_CLK1 M_A_DIM0_CLK_DDR1 15 M_B_DQ5 SB_DQ4 SB_CLK1 M_B_DIM0_CLK_DDR1 14
C6 SA_DQ5 SA_CLK#1 AB5 M_A_DIM0_CLK_DDR#1 15 A8 SB_DQ5 SB_CLK#1 AD1 M_B_DIM0_CLK_DDR#1 14
M_A_DQ6 C2 V10 M_B_DQ6 D9 R10
M_A_DQ7 SA_DQ6 SA_CKE1 M_A_DIM0_CKE1 15 M_B_DQ7 SB_DQ6 SB_CKE1 M_B_DIM0_CKE1 14
C3 SA_DQ7 D8 SB_DQ7
M_A_DQ8 F10 M_B_DQ8 G4
F8 SA_DQ9 F4 SB_DQ9
M_A_DQ10 G10 AB4 M_B_DQ10 F1 AB2
M_A_DQ11 SA_DQ10 SA_CLK2 M_B_DQ11 SB_DQ10 SB_CLK2
G9 SA_DQ11 SA_CLK#2 AA4 G1 SB_DQ11 SB_CLK#2 AA2
M_A_DQ12 F9 W9 M_B_DQ12 G5 T9
M_A_DQ13 SA_DQ12 SA_CKE2 M_B_DQ13 SB_DQ12 SB_CKE2
F7 SA_DQ13 F5 SB_DQ13
M_A_DQ14 G8 M_B_DQ14 F2
G7 SA_DQ15 G2 SB_DQ15
M_A_DQ16 K4 AB3 M_B_DQ16 J7 AA1
M_A_DQ17 SA_DQ16 SA_CLK3 M_B_DQ17 SB_DQ16 SB_CLK3
K5 SA_DQ17 SA_CLK#3 AA3 J8 SB_DQ17 SB_CLK#3 AB1
M_A_DQ18 K1 W10 M_B_DQ18 K10 T10
M_A_DQ19 SA_DQ18 SA_CKE3 M_B_DQ19 SB_DQ18 SB_CKE3
J1 SA_DQ19 K9 SB_DQ19
M_A_DQ20 J5 M_B_DQ20 J9
J4 SA_DQ21 J10 SB_DQ21
M_A_DQ22 J2 AK3 M_B_DQ22 K8 AD3
M_A_DQ23 SA_DQ22 SA_CS#0 M_A_DIM0_CS#0 15 M_B_DQ23 SB_DQ22 SB_CS#0 M_B_DIM0_CS#0 14
K2 SA_DQ23 SA_CS#1 AL3 M_A_DIM0_CS#1 15 K7 SB_DQ23 SB_CS#1 AE3 M_B_DIM0_CS#1 14
M_A_DQ24 M8 AG1 M_B_DQ24 M5 AD6
M_A_DQ25 SA_DQ24 SA_CS#2 M_B_DQ25 SB_DQ24 SB_CS#2
N10 SA_DQ25 SA_CS#3 AH1 N4 SB_DQ25 SB_CS#3 AE6
M_A_DQ26 N8 M_B_DQ26 N2
N7 SA_DQ27 N1 SB_DQ27
M_A_DQ28 M10 M_B_DQ28 M4
M9 SA_DQ29 SA_ODT0 AH3 M_A_DIM0_ODT0 15 N5 SB_DQ29 SB_ODT0 AE4 M_B_DIM0_ODT0 14
DDR SYSTEM MEMORY B

C M_A_DQ30 N9 AG3 M_B_DQ30 M2 AD4 C
M_A_DQ31
M_A_DQ32
M7
AG6
SA_DQ30
SA_DQ31 DDR SYSTEM MEMORY A SA_ODT1
SA_ODT2 AG2
AH2
M_A_DIM0_ODT1 15 M_B_DQ31
M_B_DQ32
M1
AM5
SB_DQ30
SB_DQ31
SB_ODT1
SB_ODT2 AD5
AE5
M_B_DIM0_ODT1 14
M_A_DQ33 SA_DQ32 SA_ODT3 M_B_DQ33 SB_DQ32 SB_ODT3

AG5 SA_DQ33 AM6 SB_DQ33
M_A_DQ34 AK6 M_B_DQ34 AR3
AK5 SA_DQ35 AP3 SB_DQ35
M_A_DQ36 AH5 M_A_DQS#[7:0] 15 M_B_DQ36 AN3 M_B_DQS#[7:0] 14
M_A_DQ37 SA_DQ36 M_A_DQS#0 M_B_DQ37 SB_DQ36 M_B_DQS#0
AH6 SA_DQ37 SA_DQS#0 C4 AN2 SB_DQ37 SB_DQS#0 D7
M_A_DQ38 AJ5 G6 M_A_DQS#1 M_B_DQ38 AN1 F3 M_B_DQS#1
M_A_DQ39 SA_DQ38 SA_DQS#1 M_A_DQS#2 M_B_DQ39 SB_DQ38 SB_DQS#1 M_B_DQS#2
AJ6 SA_DQ39 SA_DQS#2 J3 AP2 SB_DQ39 SB_DQS#2 K6
M_A_DQ40 AJ8 M6 M_A_DQS#3 M_B_DQ40 AP5 N3 M_B_DQS#3
AK8 SA_DQ41 SA_DQS#4 AL6 AN9 SB_DQ41 SB_DQS#4 AN5
M_A_DQ42 AJ9 AM8 M_A_DQS#5 M_B_DQ42 AT5 AP9 M_B_DQS#5
AK9 SA_DQ43 SA_DQS#6 AR12 AT6 SB_DQ43 SB_DQS#6 AK12
M_A_DQ44 AH8 AM15 M_A_DQS#7 M_B_DQ44 AP6 AP15 M_B_DQS#7
M_A_DQ45 SA_DQ44 SA_DQS#7 M_B_DQ45 SB_DQ44 SB_DQS#7
AH9 SA_DQ45 AN8 SB_DQ45
M_A_DQ46 AL9 M_B_DQ46 AR6
AL8 SA_DQ47 AR5 SB_DQ47
M_A_DQ48 AP11 M_A_DQS[7:0] 15 M_B_DQ48 AR9 M_B_DQS[7:0] 14
M_A_DQ49 SA_DQ48 M_A_DQS0 M_B_DQ49 SB_DQ48 M_B_DQS0
AN11 SA_DQ49 SA_DQS0 D4 AJ11 SB_DQ49 SB_DQS0 C7
M_A_DQ50 AL12 F6 M_A_DQS1 M_B_DQ50 AT8 G3 M_B_DQS1
M_A_DQ51 SA_DQ50 SA_DQS1 M_A_DQS2 M_B_DQ51 SB_DQ50 SB_DQS1 M_B_DQS2
AM12 SA_DQ51 SA_DQS2 K3 AT9 SB_DQ51 SB_DQS2 J6
M_A_DQ52 AM11 N6 M_A_DQS3 M_B_DQ52 AH11 M3 M_B_DQS3
AL11 SA_DQ53 SA_DQS4 AL5 AR8 SB_DQ53 SB_DQS4 AN6
M_A_DQ54 AP12 AM9 M_A_DQS5 M_B_DQ54 AJ12 AP8 M_B_DQS5
AN12 SA_DQ55 SA_DQS6 AR11 AH12 SB_DQ55 SB_DQS6 AK11
M_A_DQ56 AJ14 AM14 M_A_DQS7 M_B_DQ56 AT11 AP14 M_B_DQS7
M_A_DQ57 SA_DQ56 SA_DQS7 M_B_DQ57 SB_DQ56 SB_DQS7
AH14 SA_DQ57 AN14 SB_DQ57
M_A_DQ58 AL15 M_B_DQ58 AR14
B M_A_DQ59 SA_DQ58 M_B_DQ59 SB_DQ58 B
AK15 SA_DQ59 AT14 SB_DQ59
M_A_DQ60 AL14 M_B_DQ60 AT12
M_A_DQ61 SA_DQ60 M_A_A0 M_A_A[15:0] 15 M_B_DQ61 SB_DQ60 M_B_A0 M_B_A[15:0] 14
AK14 SA_DQ61 SA_MA0 AD10 AN15 SB_DQ61 SB_MA0 AA8
M_A_DQ62 AJ15 W1 M_A_A1 M_B_DQ62 AR15 T7 M_B_A1
M_A_DQ63 SA_DQ62 SA_MA1 M_A_A2 M_B_DQ63 SB_DQ62 SB_MA1 M_B_A2
AH15 SA_DQ63 SA_MA2 W2 AT15 SB_DQ63 SB_MA2 R7
W7 M_A_A3 T6 M_B_A3
SA_MA3 M_A_A4 SB_MA3 M_B_A4
SA_MA4 V3 SB_MA4 T2
V2 M_A_A5 T4 M_B_A5
SA_MA6 W3 SB_MA6 T3
15 M_A_BS0 AE10 W6 M_A_A7 14 M_B_BS0 AA9 R2 M_B_A7
SA_BS0 SA_MA7 M_A_A8 SB_BS0 SB_MA7 M_B_A8
15 M_A_BS1 AF10 SA_BS1 SA_MA8 V1 14 M_B_BS1 AA7 SB_BS1 SB_MA8 T5
15 M_A_BS2 V6 W5 M_A_A9 14 M_B_BS2 R6 R3 M_B_A9
SA_BS2 SA_MA9 M_A_A10 SB_BS2 SB_MA9 M_B_A10
SA_MA10 AD8 SB_MA10 AB7
V4 M_A_A11 R1 M_B_A11
SA_MA12 W4 SB_MA12 T1
15 M_A_CAS# AE8 CPU1 AF8 M_A_A13 14 M_B_CAS# AA10 CPU1 AB10 M_B_A13
SA_CAS# SA_MA13 M_A_A14 SB_CAS# SB_MA13 M_B_A14
15 M_A_RAS# AD9 SA_RAS# SA_MA14 V5 14 M_B_RAS# AB8 SB_RAS# SB_MA14 R5
15 M_A_WE# AF9 V7 M_A_A15 14 M_B_WE# AB9 R4 M_B_A15
SA_WE# SA_MA15 SB_WE# SB_MA15
SANDY SANDY
62.10055.421 62.10055.421
2nd = 62.10040.771 2nd = 62.10040.771
A DN15ATI Whistler A
Wistron Corporation
Title
CPU (DDR)
A3
5 4 3 2 1
5 4 3 2 1
SSID = CPU
CFG2
CPU1E 5 OF 9
1
PEG Static Lane Reversal
11/17 remove TP715 R702
1KR2J-1-GP 1: Normal Operation; Lane #
RSVD#L7 L7 DIS
RSVD#AG7 AG7 CFG2 definition matches socket pin map definition
AK28 SANDY AE7
2
CFG0 RSVD#AE7 0:Lane Reversed
AK29 CFG1 RSVD#AK2 AK2
CFG2 AL26 W8
CFG2 RSVD#W8
D AL27 CFG3 D
CFG4 AK26
CFG5 CFG4
AL29 CFG5 RSVD#AT26 AT26
CFG6 AL30 AM33
CFG6 RSVD#AM33
CFG7 AM31 CFG7 RSVD#AJ27 AJ27 11/17 change R703 to 1K but dummy
AM32 CFG4
CFG8
AM30 CFG9
AM28 CFG10
Display Port Presence Strap
1
AM26 CFG11
AN28 CFG12
R703 CFG4 1: Disabled; No Physical Display Port
1KR2F-3-GP
AN31 CFG13 RSVD#T8 T8 DY attached to Embedded Display Port
AN26 CFG14 RSVD#J16 J16
AM27 H16 0: Enabled; An external Display Port device is
2
CFG15 RSVD#H16
AK31 CFG16 RSVD#G16 G16 connected to the Embedded Display Port
AN29 CFG17
RSVD#AR35 AR35
AJ31 RSVD#AJ31 RSVD#AT34 AT34
AH31 RSVD#AH31 RSVD#AT33 AT33
AJ33 AP35 CFG5
RSVD#AJ33 RSVD#AP35
AH33 RSVD#AH33 RSVD#AR34 AR34
CFG6 PCIE Port Bifurcation Straps
1
AJ26
M3 - Processor Generated SO-DIMM VREF_DQ RSVD#AJ26
RESERVED
R701 R704 CFG[6:5] 11: x16 - Device 1 functions 1 and 2 disabled
DY DY
DY B4:VREF_DQ CHA B34 10: x8, x8 - Device 1 function 1 enabled ; function 2 disabled
R708 1 RSVD#B34 01: Reserved - (Device 1 function 1 disabled ; function 2 enabled)
C
M_VREF_DQ_DIMM0 DY 2 0R2J-2-GP M_VREF_DQ_DIMM0_C B4 A33 C
2
R709 1 RSVD#B4 RSVD#A33 00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
2 0R2J-2-GP M_VREF_DQ_DIMM1_C D1 A34
1KR2J-1-GP
1KR2J-1-GP
M_VREF_DQ_DIMM1 RSVD#D1 RSVD#A34
RSVD#B35 B35
D1:VREF_DQ CHB RSVD#C35 C35
1
F25 RSVD#F25
R711 R712 F24 CFG7
RSVD#F24
F23 RSVD#F23
1KR2F-3-GP 1KR2F-3-GP D24 RSVD#D24 RSVD#AJ32 AJ32 PEG DEFER TRAINING
1
M_VREF_CA_DIMM0 R707 1 DY 2 0R2J-2-GP G25 AK32
2
RSVD#G25 RSVD#AK32 R705

G24 RSVD#G24 1: PEG Train immediately following xxRESETB de assertion
R706 1 2 0R2J-2-GP 1KR2J-1-GP CFG7
M_VREF_CA_DIMM1 DY E23 RSVD#E23 DY
D23 0: PEG Wait for BIOS for training
RSVD#D23
C30 AH27
2
RSVD#C30 RSVD#AH27
A31 RSVD#A31
B30 RSVD#B30
B29 0702 Modify
RSVD#B29
D30 RSVD#D30 RSVD#AN35 AN35 TP713 1
20 mils B31 RSVD#B31 RSVD#AM35 AM35 TP714 1 TP713 TPAD14-GP
A30 TP714 TPAD14-GP
RSVD#A30
C29 RSVD#C29
J20 RSVD#J20
B18 RSVD#B18 RSVD#AT2 AT2
R710 1 DY 2 0R2J-2-GP H_VCCP_SEL A19 AT1
RSVD#A19 RSVD#AT1
RSVD#AR1 AR1
J15 RSVD#J15
B B
CPU1
62.10055.421
2nd = 62.10040.771
DN15ATI Whistler
A A
Wistron Corporation
Title
CPU (RESERVED)
A3
5 4 3 2 1
5 4 3 2 1
SSID = CPU
CPU1F POWER 6 OF 9
VCCIO Output Decoupling Recommendation:
2 x 330 uF (3 x 330 uF for 2012 capable designs)
5 x 22 uF & 5 x 0805 no-stuff at Bottom
VCC_CORE SANDY 7 x 22 uF & 2 x 0805 no-stuff at Top
12/28 Yellow mark for OPI change 1D05V_VTT
AG35 VCC PROCESSOR VCCIO: 8.5A
AG34 VCC VCCIO AH13
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
AG33 VCC VCCIO AH10
C805
C808
C809
C838
C839
C840
C841
SC10U6D3V3MX-GP
SC4D7U6D3V3KX-GP
D AG32 VCC VCCIO AG10 D
1
AG31 VCC VCCIO AC10
AG30 VCC VCCIO Y10 DY DY
AG29 U10
2
VCC VCCIO
AG28 VCC VCCIO P10
AG27 VCC VCCIO L10
AG26 VCC VCCIO J14
AF35 VCC VCCIO J13
AF34 VCC VCCIO J12
AF33 VCC VCCIO J11
AF32 VCC VCCIO H14
AF31 VCC VCCIO H12 12/23 stuff the capacities
PROCESSOR CORE POWER AF30 VCC VCCIO H11
AF29 VCC VCCIO G14
AF28 G13
53A VCC VCCIO
PEG AND DDR

VCC_CORE 11/15 change Caps to 78.22610.51L AF27 G12
VCC VCCIO
AF26 VCC VCCIO F14
AD35 VCC VCCIO F13 No-stuff sites outside the socket may be removed.
AD34 F12
VCC VCCIO No-stuff sites inside the socket cavity need to remain.
SC22U4V3MX-GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
AD33 VCC VCCIO F11

C804
C806
C807
AD32 VCC VCCIO E14

1
1D05V_VTT
C801
C802
C803
AD31 VCC VCCIO E12

AD30 VCC
AD29 E11
2
VCC VCCIO
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
AD28 VCC VCCIO D14
C829
C842
C843
C844
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
AD27 VCC VCCIO D13
1
C830
C845
AD26 VCC VCCIO D12
12/23 stuff the capacities AC35 VCC VCCIO D11
AC34 C14
2
VCC VCCIO
AC33 VCC VCCIO C13
AC32 VCC VCCIO C12
C AC31 VCC VCCIO C11 C
SC22U4V3MX-GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
AC30 VCC VCCIO B14

C820
C819
C818
C812
C811
AC29 VCC VCCIO B12

1
1
C817
AC28 VCC VCCIO A14

DY DY AC27 VCC VCCIO A13
AC26 A12
2
VCC VCCIO
AA35 VCC VCCIO A11
AA34 VCC
AA33 VCC VCCIO J23 11/16 follow DN13 to meet schematic check list
AA32 VCC
AA31 VCC
12/28 Yellow mark for OPI change AA30 These resistors need to close to power IC 1D05V_VTT
VCC
AA29 VCC
11/17 change part refernce R807 to R805
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-L2GP
SC22U6D3V5MX-2GP
AA28 VCC
AA27 VCC
C816
C821
C822
C823
C824
C825
C827
AA26 VCC
1
CORE SUPPLY
C826
Y35 VR_SVID_ALERT# R805 1 2 75R2J-1-GP

VCC
Y34 VCC
Y33
2
VCC H_CPU_SVIDCLK R806

Y32 VCC 1 DY 2 54D9R2F-L1-GP
Y31 VCC
Y30 H_CPU_SVIDDAT R804 1 2 130R2F-1-GP
VCC
Y29 VCC
Y28 VCC
Y27 VCC
Y26 VCC
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
V35 VCC
SVID
H_CPU_SVIDALRT# R803 2 43R2J-GP
SC22U6D3V5MX-L2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC10U6D3V5KX-1GP
V34 VCC VIDALERT# AJ29 1 VR_SVID_ALERT# 42

C834
C833
C831
V33 AJ30 H_CPU_SVIDCLK

VCC VIDSCLK H_CPU_SVIDCLK 42
1
1
C837
V32 AJ28 H_CPU_SVIDDAT

VCC VIDSOUT H_CPU_SVIDDAT 42
C836
C835
C832
C828
V31 VCC
B V30 B
2
VCC
V29 VCC
V28 VCC
V27 VCC
V26 VCC
U35 VCC
U34 VCC
U33 VCC
VCC Output Decoupling Recommendation: U32 VCC
4 x 470 uF at Bottom Socket Edge U31 VCC
U30
8 x 22 uF at Top Socket Cavity U29
VCC
8 x 22 uF at Top Socket Edge VCC
U28 VCC
8 x 22 uF at Bottom Socket Cavity U27 VCC_CORE
VCC
U26 VCC
R35 VCC
1
R34 VCC
11/4 add Caps to 28 location as vendor recommand. R33 VCC
R801
R32 100R2F-L1-GP-U
VCC
X01-0127 Stuff C812, C822, C831, C834 R31 VCC
R30
for VCC core noise issue.
2
VCC
R29 VCC
SENSE LINES
R28 VCC
X01-0217 Stuff C801=22uF R27 VCC VCC_SENSE AJ35 VCCSENSE 42
R26 AJ34 VSSSENSE 42
change C817 to 22uF P35
VCC VSS_SENSE
VCC
P34 VCC
1
P33 VCC
P32 B10 VCCIO_SENSE 45 R802
VCC VCCIO_SENSE 100R2F-L1-GP-U
P31 VCC VSSIO_SENSE A10 VSSIO_SENSE 45
P30 VCC
A P29 A
2
VCC
P28 VCC <Core Design>
P27 VCC
P26 VCC
CPU1 Wistron Corporation
Title
CPU (VCC_CORE)
SANDY Size Document Number Rev
Custom
62.10055.421 Enrico Caruso 14 A00
2nd = 62.10040.771 Date: Wednesday, April 13, 2011 Sheet 8 of 105
5 4 3 2 1
5 4 3 2 1
VAXG Output Decoupling Recommendation:

SSID = CPU 2 x 470 uF at Bottom Socket Edge
2 x 22 uF at Top Socket Cavity VCC_GFXCORE
4 x 22 uF at Top Socket Edge
2 x 22 uF at Bottom Socket Cavity
4 x 22 uF at Bottom Socket Edge
POWER
1
VCC_GFXCORE R906
CPU1G 7 OF 9 100R2F-L1-GP-U
PROCESSOR VAXG: 33A
SC4D7U6D3V5KX-3GP
2
SENSE
LINES
AT24 AK35 VCC_AXG_SENSE 42 VCC_AXG_SENSE
VAXG VAXG_SENSE VSS_AXG_SENSE
D AT23 AK34
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
VSS_AXG_SENSE 42 D
VAXG VSSAXG_SENSE
C902
C904
C905
C906
AT21 VAXG SANDY
1
AT20 VAXG
Refer to the latest Huron River Mainstream PDG
C901
DY AT18 R907
VAXG 100R2F-L1-GP-U
AT17 (Doc# 436735) for more details on S3 power
2
VAXG
AR24 VAXG reduction implementation.
AR23
2
VAXG
AR21 VAXG
AR20 +V_SM_VREF_CNT should have 10 mil trace width
VAXG
VREF
AR18 VAXG
12/28 Yellow mark for OPI AR17 VAXG
AP24 AL1 +V_SM_VREF_CNT
VAXG SM_VREF +V_SM_VREF_CNT 37
AP23 VAXG
AP21 VAXG
AP20
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
VAXG
AP18 VAXG
Routing Guideline:
C908
C920
C921
AP17 VAXG Power from DDR_VREF_S3 and +V_SM_VREF_CNT
1
AN24 1D5V_S0
VAXG should have 10 mils trace width.
DY AN23
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
VAXG
2 AN21
2
VAXG
AN20 PROCESSOR VDDQ: 10A
SC4D7U6D3V5KX-3GP
VAXG
DDR3 -1.5V RAILS

AN18 VAXG
AN17
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
VAXG
GRAPHICS
1D5V_S3
C909
C910
C911
C913
C914
AM24 AF7
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
VAXG VDDQ
1
C912
C907
C918
C919
C925
AM23 VAXG VDDQ AF4
TC901
DY DY DY DY
AM21 VAXG VDDQ AF1 DY DY DY
AM20 AC7
2
VAXG VDDQ
AM18 VAXG VDDQ AC4
AM17 VAXG VDDQ AC1
C AL24 Y7 ST330U2VDM-4-GP C
VAXG VDDQ
AL23 Y4
AL21
VAXG VDDQ
Y1
79.33719.20L
2nd = 77.C3371.13L
VAXG VDDQ
AL20 VAXG VDDQ U7 12/28 Yellow mark for OPI
AL18 VAXG VDDQ U4 VDDQ Output Decoupling Recommendation:
AL17 VAXG VDDQ U1 1 x 330 uF
AK24 P7
AK23
VAXG VDDQ
P4
6 x 10 uF
VAXG VDDQ 0D85V_S0
AK21 VAXG VDDQ P1
AK20 VAXG
AK18 VAXG PROCESSOR VCCSA: 6A
AK17 VAXG
AJ24
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
VAXG
C916
C915
C917
AJ23 VAXG
1
AJ21 VAXG
AJ20
DY
SCD1U50V3KX-GP
VAXG
AJ18
2
VAXG
EC902
AJ17 VAXG
AH24
SA RAIL
VAXG
AH23 VAXG
AH21 VAXG VCCSA M27 VCCSA Output Decoupling Recommendation:
AH20 VAXG VCCSA M26 1 x 330 uF
AH18 L26
Disabling Guidelines for External Graphics Designs: AH17
VAXG VCCSA
J26
2 x 10 uF at Bottom Socket Cavity
VAXG VCCSA 1 x 10 uF at Bottom Socket Edge
Can connect to GND if motherboard only supports external VCCSA J25
J24
graphics and if GFX VR is not stuffed. VCCSA
H26
Can be left floating (Gfx VR keeps VAXG rail from floating) VCCSA
VCCSA H25
if the VR is stuffed
1.8V RAIL
B B
1D8V_S0
11/16 Follow Annie team's schematic by power solution
PROCESSOR VCCPLL: 1.2A
B6 VCCPLL VCCSA_SENSE H23 VCCSA_SENSE 1R910 2 0D85V_S0 R910 close to pin H23.
MISC
A6 10R2J-2-GP
SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC10U6D3V5KX-1GP
VCCPLL
C923
C922
C924
A2 VCCPLL
1
C22 H_FC_C22
FC_C22 VCCSA_SEL
C24 VCCSA_SEL 48
2
VCCSA_VID1
CPU1
4
3
SANDY
DY RN901
62.10055.421 SRN1KJ-7-GP 11/ 17 dummy RN901
2nd = 62.10040.771
1
2
VCCPLL Output Decoupling Recommendation:
1 x 330 uF
2 x 1 uF
1 x 10 uF
A <Core Design> A
Wistron Corporation
Title
CPU (VCC_GFXCORE)
A3
5 4 3 2 1
5 4 3 2 1
SSID = CPU
CPU1H 8 OF 9 CPU1I 9 OF 9
AT35 VSS VSS AJ22

AT32 VSS VSS AJ19
AT29
AT27
VSS VSS AJ16
AJ13
T35
T34
VSS SANDY VSS F22
F19
VSS VSS VSS VSS
AT25 VSS VSS AJ10 T33 VSS VSS E30
D AT19 VSS VSS AJ4 T31 VSS VSS E24 D
AT13
AT10
VSS SANDY VSS AJ2
AJ1
T29
T28
VSS VSS E18
E15
VSS VSS VSS VSS
AT7 VSS VSS AH35 T27 VSS VSS E13
AT4 VSS VSS AH34 T26 VSS VSS E10
AT3 VSS VSS AH32 P9 VSS VSS E9
AR25 VSS VSS AH30 P8 VSS VSS E8
AR10 VSS VSS AH22 N35 VSS VSS E3
AR2 VSS VSS AH7 N32 VSS VSS D35
AP34 VSS VSS AH4 N31 VSS VSS D32
AP31 VSS VSS AG9 N30 VSS VSS D29
AP22 VSS VSS AF6 N27 VSS VSS D17
AP19 VSS VSS AF5 N26 VSS VSS C34
AP16 VSS VSS AF3 M34 VSS VSS C31
AP13 VSS VSS AF2 L33 VSS VSS C28
AP10 VSS VSS AE35 L30 VSS VSS C27
AN30 VSS VSS AE31 L6 VSS VSS C1
C AN27 AE30 L5 B22 C
VSS VSS VSS VSS
AN25 AE29 L4 B19
AN22
AN19
VSS
VSS
VSS
VSS VSS
VSS
VSS
AE28
AE27
L3
L2
VSS
VSS
VSS
VSS VSS
VSS
VSS
B17
B15
AN16 VSS VSS AE26 L1 VSS VSS B13
AN13 VSS VSS AE9 K35 VSS VSS B11
AN10 VSS VSS AD7 K32 VSS VSS B9
AN7 VSS VSS AC9 K29 VSS VSS B8
AN4 VSS VSS AC8 K26 VSS VSS B7
AM29 VSS VSS AC6 J34 VSS VSS B5
AM25 VSS VSS AC5 J31 VSS VSS B3
AM22 VSS VSS AC3 H33 VSS VSS B2
AM19 VSS VSS AC2 H30 VSS VSS A35
AM16 VSS VSS AB35 H27 VSS VSS A32
AM2 VSS VSS AB29 H10 VSS
AM1 VSS VSS AB28 H9 VSS
AL34 VSS VSS AB27 H8 VSS
AL31 VSS VSS AB26 H7 VSS
AL28 VSS VSS Y9 H6 VSS
B B
AL10 VSS VSS W35 G35 VSS
AK33 VSS VSS W31 G23 VSS
AK22 VSS VSS W27 F34 VSS
AK19 VSS CPU1 VSS W26 F31 VSS
AK16 VSS VSS U9 F29 VSS
AK13 VSS VSS U8
AK10 VSS VSS U6 CPU1
AK7 VSS VSS U5
AK4 VSS VSS U3
AJ25 VSS VSS U2
SANDY SANDY
62.10055.421 62.10055.421
2nd = 62.10040.771 2nd = 62.10040.771
Wistron Corporation
Title
CPU (VSS)
A3
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
Wistron Corporation
Title
XDP
A3
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
Wistron Corporation
Title
Reserved
A3
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
Wistron Corporation
Title
Reserved
A3
5 4 3 2 1
5 4 3 2 1
DM2
SSID = MEMORY M_B_A0 98 A0 NP1 NP1 3D3V_S0
M_B_A1 97 NP2
M_B_A2 A1 NP2
M_B_A[15:0] 6 96 A2
M_B_A3 95 110 M_B_RAS# 6
A3 RAS#
1
M_B_A4 92 113 M_B_WE# 6
M_B_A5 A4 WE# R1402
91 A5 CAS# 115 M_B_CAS# 6
DDR_VREF_S3 M_B_A6 90 10KR2J-3-GP
M_B_A7 A6
86 A7 CS0# 114 M_B_DIM0_CS#0 6
M_B_A8 89 121 SWAP SA0_DM1 and SA1_DIM1 each other
M_B_DIM0_CS#1 6
2
A8 CS1#
2
M_B_A9 85 for DM2 can't boot up issue(only DN15/DQ15)

R1405 M_B_A10 A9
107 A10/AP CKE0 73 M_B_DIM0_CKE0 6
0R0402-PAD M_B_A11 84 74 M_B_DIM0_CKE1 6
M_B_A12 A11 CKE1 SA1_DIM1
D 83 A12 D
M_VREF_CA_DIMM1 M_B_A13 119 101 M_B_DIM0_CLK_DDR0 6
1
M_B_A14 A13 CK0 SA0_DIM1

80 A14 CK0# 103 M_B_DIM0_CLK_DDR#0 6
M_B_A15 78 A15
6 M_B_BS2 79 A16/BA2 CK1 102 M_B_DIM0_CLK_DDR1 6
1
CK1# 104 M_B_DIM0_CLK_DDR#1 6
1
109 R1401
C1423 C1425 C1424 6 M_B_BS0 BA0 10KR2J-3-GP
DY 6 M_B_BS1 108 BA1 DM0 11
11/ 17 Change SMbus adress note
SCD1U10V2KX-5GP
SC2D2U10V3KX-1GP
SCD1U10V2KX-5GP
6 M_B_DQ[63:0] 28
2
M_B_DQ0 DM1
5 46
2
M_B_DQ1 DQ0 DM2
M_B_DQ2
7 DQ1 DM3 63 Note:
15 DQ2 DM4 136
M_B_DQ3 17 153 If SA0 DIM0 = 0, SA1_DIM0 = 0
M_B_DQ4 DQ3 DM5
4 DQ4 DM6 170 SO-DIMMA SPD Address is 0xA0
M_B_DQ5 6 187
DQ5 DM7
M_B_DQ6 16 DQ6
SO-DIMMA TS Address is 0x30
M_B_DQ7 18 200
DQ7 SDA PCH_SMBDATA 15,20,65
M_B_DQ8 21 202
DDR_VREF_S3 DQ8 SCL PCH_SMBCLK 15,20,65
M_B_DQ9 23 DQ9 3D3V_S0
If SA0 DIM0 = 0, SA1_DIM0 = 1
M_B_DQ10 33 198 TS#_DIMM0_1 15
M_B_DQ11 35
DQ10 EVENT# SO-DIMMA SPD Address is 0xA4
DQ11
2
M_B_DQ12 22 199 SO-DIMMA TS Address is 0x34

R1404 M_B_DQ13 DQ12 VDDSPD
SCD1U10V2KX-5GP
SC2D2U10V3KX-1GP
24 DQ13
0R0402-PAD M_B_DQ14 34 197 SA0_DIM1
DQ14 SA0
1
C1401
C1402
M_B_DQ15 36 201 SA1_DIM1
M_VREF_DQ_DIMM1 M_B_DQ16 DQ15 SA1
39
1
M_B_DQ17 DQ16
41 77
DY
2
M_B_DQ18 DQ17 NC#1
M_B_DQ19
51
53
DQ18
DQ19
NC#2
NC#/TEST
122
125 1D5V_S3 Thermal EVENT
M_B_DQ20 40 DQ20
1
M_B_DQ21 42 75 3D3V_S0
C1411 C1412 C1413 M_B_DQ22 DQ21 VDD1
C
DY M_B_DQ23
50 DQ22 VDD2 76
TS#_DIMM0_1
C
SCD1U10V2KX-5GP
SC2D2U10V3KX-1GP
SCD1U10V2KX-5GP
52 81 1R1403 2
2
M_B_DQ24 DQ23 VDD3 10KR2J-3-GP

57 DQ24 VDD4 82
M_B_DQ25 59 87
M_B_DQ26 DQ25 VDD5
67 DQ26 VDD6 88
M_B_DQ27 69 93
M_B_DQ28 DQ27 VDD7
56 DQ28 VDD8 94
M_B_DQ29 58 99
M_B_DQ30 DQ29 VDD9
68 DQ30 VDD10 100
M_B_DQ31 70 105
M_B_DQ32 DQ31 VDD11
129 DQ32 VDD12 106
X02-0303 change 0R to short pad M_B_DQ33 131 111
M_B_DQ34 DQ33 VDD13
141 DQ34 VDD14 112
M_B_DQ35 1D5V_S3
M_B_DQ36
143 DQ35 VDD15 117 SODIMM A DECOUPLING
130 DQ36 VDD16 118
M_B_DQ37 132 123
M_B_DQ38 DQ37 VDD17
140 DQ38 VDD18 124
M_B_DQ39 142
M_B_DQ40 DQ39
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
147 2
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
DQ40 VSS
C1403
C1404
C1405
C1406
C1407
C1408
C1409
C1410
M_B_DQ41 149 3
DQ41 VSS
1
M_B_DQ42 TC1401
ST330U2VDM-4-GP
157 DQ42 VSS 8
M_B_DQ43
M_B_DQ44
159
146
DQ43 VSS 9
13
DY DY DY DY DY DY DY
2
M_B_DQ45 DQ44 VSS
148 DQ45 VSS 14
M_B_DQ46 158 19
M_B_DQ47 DQ46 VSS
0D75V_S0 Place these caps M_B_DQ48
160 DQ47 VSS 20
163 DQ48 VSS 25
close to VTT1 and M_B_DQ49 165 DQ49 VSS 26
M_B_DQ50 175 31
VTT2. M_B_DQ51 177
DQ50 VSS
32
M_B_DQ52 DQ51 VSS
SC1U6D3V2KX-GP
SCD1U10V2KX-5GP
164 DQ52 VSS 37
C1414
C1415
C1416
C1417
M_B_DQ53
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SCD1U10V2KX-5GP
B 166 DQ53 VSS 38 B
1
C1419
C1420
C1421
C1422
M_B_DQ54 174 43 Layout Note:

DQ54 VSS
1
M_B_DQ55 176 44
C1418 M_B_DQ56 DQ55 VSS Place these Caps near
DY DY DY 181 48
2
M_B_DQ57 DQ56 VSS
SC10U6D3V5KX-1GP
183 49 SO-DIMMA.
2
M_B_DQ58 DQ57 VSS

191 DQ58 VSS 54
M_B_DQ59 193 55
M_B_DQ60 DQ59 VSS
180 DQ60 VSS 60
M_B_DQ61 182 61
M_B_DQ62 DQ61 VSS
192 DQ62 VSS 65
M_B_DQ63 194 66 12/28 Yellow mark for OPI change
DQ63 VSS
VSS 71
M_B_DQS#0 10 72
M_B_DQS#1 DQS0# VSS
27 DQS1# VSS 127
M_B_DQS#2 45 128
M_B_DQS#3 DQS2# VSS
62 DQS3# VSS 133
M_B_DQS#4 135 134
M_B_DQS#5 DQS4# VSS
152 DQS5# VSS 138
M_B_DQS#6 169 139
M_B_DQS#7 DQS6# VSS
186 DQS7# VSS 144
VSS 145
M_B_DQS0 12 150
M_B_DQS1 DQS0 VSS
M_B_DQS#[7:0] 6 29 DQS1 VSS 151
M_B_DQS2 47 155
M_B_DQS3 DQS2 VSS
M_B_DQS[7:0] 6 64 DQS3 VSS 156
M_B_DQS4 137 161
M_B_DQS5 DQS4 VSS
154 DQS5 VSS 162 12/3 Change DM2 to 62.10024.E21
M_B_DQS6 171 167
M_B_DQS7 DQS6 VSS
188 DQS7 VSS 168 12/9 Change DM2 to 62.10017.K01
VSS 172
6 M_B_DIM0_ODT0 116 ODT0 VSS 173 12/21 Change DM2 to 62.10017.P61
A
6 M_B_DIM0_ODT1 120 ODT1 VSS 178 A
VSS 179 12/22 Change DM2 to 62.10024.E21 DN15ATI Whistler
M_VREF_CA_DIMM1 126 VREF_CA VSS 184
M_VREF_DQ_DIMM1 1 VREF_DQ VSS 185
15,37 DDR3_DRAMRST# 30 RESET#

VSS
VSS
189
190 Wistron Corporation
195 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
VSS Taipei Hsien 221, Taiwan, R.O.C.
VSS 196
0D75V_S0 203 VTT1 VSS 205
204 206 Title
VTT2 VSS
DDR3-SODIMM2
DDR3-204P-135-GP Size Document Number Rev
H =5.2mm Custom
62.10024.E21 Enrico Caruso 14 A00
5 4 3 2 1
5 4 3 2 1
DM1
SSID = MEMORY M_A_A0 98 A0 NP1 NP1
11/ 17 Change SMbus adress note
M_A_A1 97 NP2
M_A_A2 A1 NP2
M_A_A[15:0] 6
M_A_A3
96 A2 Note:
95 A3 RAS# 110 M_A_RAS# 6 M_A_DQS#[7:0] 6
M_A_A4 92 113 M_A_WE# 6
SO-DIMMB SPD Address is 0xA0
M_A_A5 A4 WE#
91 A5 CAS# 115 M_A_CAS# 6 M_A_DQS[7:0] 6 SO-DIMMB TS Address is 0x30
M_A_A6 90
M_A_A7 A6
86 A7 CS0# 114 M_A_DIM0_CS#0 6
M_A_A8 89 121 M_A_DIM0_CS#1 6
M_A_A9 A8 CS1#
M_A_A10
85 A9 SO-DIMMB is placed farther from
107 A10/AP CKE0 73 M_A_DIM0_CKE0 6
M_A_A11 84 74 M_A_DIM0_CKE1 6
the Processor than SO-DIMMA
M_A_A12 A11 CKE1
D 83 A12 D
M_A_A13 119 101 M_A_DIM0_CLK_DDR0 6 SA1_DIM0
M_A_A14 A13 CK0
80 A14 CK0# 103 M_A_DIM0_CLK_DDR#0 6
M_A_A15 78 SA0_DIM0
A15
6 M_A_BS2 79 A16/BA2 CK1 102 M_A_DIM0_CLK_DDR1 6
CK1# 104 M_A_DIM0_CLK_DDR#1 6
2
6 M_A_BS0 109 BA0
108 11 R1502 R1501
6 M_A_BS1 BA1 DM0 10KR2J-3-GP
6 M_A_DQ[63:0] DM1 28 10KR2J-3-GP
M_A_DQ0 5 46
M_A_DQ1 DQ0 DM2
7 63
1
M_A_DQ2 DQ1 DM3
15 DQ2 DM4 136
M_A_DQ3 17 153
M_A_DQ4 DQ3 DM5
4 DQ4 DM6 170
DDR_VREF_S3 M_A_DQ5 6 187
M_A_DQ6 DQ5 DM7
16 DQ6
M_A_DQ7 18 200
DQ7 SDA PCH_SMBDATA 14,20,65
M_A_DQ8 21 202
DQ8 SCL PCH_SMBCLK 14,20,65
2
M_A_DQ9 23
R1504 M_A_DQ10 DQ9 3D3V_S0
33 DQ10 EVENT# 198 TS#_DIMM0_1 14
0R0402-PAD M_A_DQ11 35
M_A_DQ12 DQ11
22 DQ12 VDDSPD 199
M_VREF_CA_DIMM0 M_A_DQ13 24
1
DQ13
1
C1502
M_A_DQ14 SA0_DIM0
SCD1U10V2KX-5GP
SC2D2U10V3KX-1GP
34 DQ14 SA0 197
C1501
M_A_DQ15 36 201 SA1_DIM0
M_A_DQ16 DQ15 SA1
39
DY
2
M_A_DQ17 DQ16
41 DQ17 NC#1 77
1
M_A_DQ18 51 122
C1523 C1524 C1522 M_A_DQ19 DQ18 NC#2 1D5V_S3
DY M_A_DQ20
53 DQ19 NC#/TEST 125
SCD1U10V2KX-5GP
SC2D2U10V3KX-1GP
SCD1U10V2KX-5GP
40
2
M_A_DQ21 DQ20
42 DQ21 VDD1 75
C M_A_DQ22 50 76 C
M_A_DQ23 DQ22 VDD2
52 DQ23 VDD3 81
M_A_DQ24 57 82
M_A_DQ25 DQ24 VDD4
59 DQ25 VDD5 87
M_A_DQ26 67 88
M_A_DQ27 DQ26 VDD6
69 DQ27 VDD7 93
M_A_DQ28 56 94
M_A_DQ29 DQ28 VDD8
58 DQ29 VDD9 99
M_A_DQ30 68 100
M_A_DQ31 DQ30 VDD10
70 DQ31 VDD11 105
M_A_DQ32 129 106
M_A_DQ33 DQ32 VDD12 1D5V_S3
131 DQ33 VDD13 111
DDR_VREF_S3 M_A_DQ34
M_A_DQ35
141 DQ34 VDD14 112 SODIMM B DECOUPLING
143 DQ35 VDD15 117
M_A_DQ36 130 118 12/28 Yellow mark for OPI change
M_A_DQ37 DQ36 VDD16
132 DQ37 VDD17 123
2
M_A_DQ38
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
140 124
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
DQ38 VDD18
C1503
C1504
C1505
C1506
C1507
C1508
C1509
C1510
R1503 M_A_DQ39 142 DQ39
1
0R0402-PAD M_A_DQ40 147 2
M_A_DQ41 DQ40 VSS
M_VREF_DQ_DIMM0 M_A_DQ42
149 DQ41 VSS 3
DY DY DY DY DY
157 8
1
2
M_A_DQ43 DQ42 VSS
159 DQ43 VSS 9
M_A_DQ44 146 13
M_A_DQ45 DQ44 VSS
148 DQ45 VSS 14
M_A_DQ46 158 19
DQ46 VSS
1
M_A_DQ47 160 20
C1515 C1516 C1517 M_A_DQ48 DQ47 VSS
DY M_A_DQ49
163 DQ48 VSS 25
SCD1U10V2KX-5GP
SC2D2U10V3KX-1GP
SCD1U10V2KX-5GP
165 26
2
M_A_DQ50 DQ49 VSS
SC1U6D3V2KX-GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
175 DQ50 VSS 31
C1511
C1512
C1513
C1514
M_A_DQ51 177 32
DQ51 VSS
1
M_A_DQ52 164 37 Layout Note:
M_A_DQ53 DQ52 VSS
B 166 DQ53 VSS 38 B
M_A_DQ54 174 43 Place these Caps near
2
M_A_DQ55 DQ54 VSS
176 DQ55 VSS 44 SO-DIMMB.
M_A_DQ56 181 48
M_A_DQ57 DQ56 VSS
183 DQ57 VSS 49
X02-0303 change 0R to short pad M_A_DQ58 191 54
M_A_DQ59 DQ58 VSS
193 DQ59 VSS 55
M_A_DQ60 180 60
M_A_DQ61 DQ60 VSS
182 DQ61 VSS 61
M_A_DQ62 192 65
M_A_DQ63 DQ62 VSS
194 DQ63 VSS 66
Place these caps M_A_DQS#0 VSS 71
10 DQS0# VSS 72
0D75V_S0 close to VTT1 and M_A_DQS#1 27 DQS1# VSS 127
M_A_DQS#2 45 128
VTT2. M_A_DQS#3 DQS2# VSS
62 DQS3# VSS 133
M_A_DQS#4 135 134
M_A_DQS#5 DQS4# VSS
152 DQS5# VSS 138
C1518
C1519
C1520
C1521
M_A_DQS#6
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
169 DQS6# VSS 139

1
M_A_DQS#7 186 144

DQS7# VSS
DY DY M_A_DQS0 VSS 145
12 150
2
M_A_DQS1 DQS0 VSS

29 DQS1 VSS 151
M_A_DQS2 47 155
M_A_DQS3 DQS2 VSS
64 DQS3 VSS 156
M_A_DQS4 137 161 12/7 Change DM1 to 62.10024.D51
M_A_DQS5 DQS4 VSS
154 DQS5 VSS 162
M_A_DQS6 171 167 12/9 Change DM1 to 62.10017.K11
M_A_DQS7 DQS6 VSS
188 DQS7 VSS 168
VSS 172 12/17 Change DM1 to 62.10017.N11
6 M_A_DIM0_ODT0 116 ODT0 VSS 173
A
6 M_A_DIM0_ODT1 120 ODT1 VSS 178 12/21 Change DM1 to 62.10017.Q41 A
VSS 179 DN15ATI Whistler
M_VREF_CA_DIMM0 126 VREF_CA VSS 184 12/22 Change DM1 to 62.10024.D91
M_VREF_DQ_DIMM0 1 VREF_DQ VSS 185
VSS 189 12/22 Change DM1 to 62.10024.D51 Wistron Corporation
14,37 DDR3_DRAMRST# 30 RESET# VSS 190
195 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
VSS Taipei Hsien 221, Taiwan, R.O.C.
VSS 196
0D75V_S0 203 VTT1 VSS 205
204 206 Title
VTT2 VSS
Note: DDR3-SODIMM1
H =9.2mm DDR3-204P-128-GP The symbol DM1 is change value and PN only. Size Document Number Rev
Custom
62.10024.D51 Enrico Caruso 14 A00
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
Wistron Corporation
Title
Reserved
A3
5 4 3 2 1
5 4 3 2 1
D D
PCH1D 4 OF 10 3D3V_S0
27 L_BKLT_EN J47 AP43
49 LVDS_VDD_EN M45
L_BKLTEN
L_VDD_EN
Cougar SDVO_TVCLKINN
SDVO_TVCLKINP AP45
3D3V_S0
49 L_BKLT_CTRL P45 L_BKLTCTL
Point SDVO_STALLN AM42
2
1
L_DDC_DATA(PAGE17): LVDS_DDC_CLK_R SDVO_STALLP AM40
RN1706
49 LVDS_DDC_CLK_R T40 L_DDC_CLK DDI Port B Detect:(SDVO_CTRL_ DATA)
RN1701
This signal is on the LVDS interface. 49 LVDS_DDC_DATA_R LVDS_DDC_DATA_R K47 AP39 SRN2K2J-1-GP HDMI 1: Port B detected
L_DDC_DATA SDVO_INTN
This signal needs to be left NC if eDP is SDVO_INTP AP40
1 4 L_CTRL_DATA L_CTRL_CLK T45 0: Port B not detected
L_CTRL_CLK used for the local flat panel display L_CTRL_DATA L_CTRL_CLK
2 3 P39
3
4
L_CTRL_DATA
LVDS_IBG AF37 P38
SRN2K2J-1-GP LVD_IBG SDVO_CTRLCLK PCH_HDMI_CLK 51
TPAD14-GP TP1701 1 LVDS_VBG AF36 M39
LVD_VBG SDVO_CTRLDATA PCH_HDMI_DATA 51
1
2 RN1704 3 LVDS_VREFH AE48 LVD_VREFH
R1701 1 4 LVDS_VREFL AE47 AT49
RN1702 2K37R2F-GP 0R4P2R-PAD LVD_VREFL DDPB_AUXN
DDPB_AUXP AT47
2 3 L_BKLT_EN AT40
DDPB_HPD HDMI_PCH_DET 51
RN
1 4 LVDS_VDD_EN Place near PCH 49 LVDSA_CLK# AK39
LVDS
2
LVDSA_CLK#
49 LVDSA_CLK AK40 LVDSA_CLK DDPB_0N AV42 HDMI_DATA2_R# 51
SRN100KJ-6-GP AV40 HDMI_DATA2_R 51
DDPB_0P
49 LVDSA_DATA0# AN48 LVDSA_DATA#0 DDPB_1N AV45 HDMI_DATA1_R# 51
C AM47 AV46 C
49 LVDSA_DATA1# HDMI_DATA1_R 51
Digital Display Interface

LVDSA_DATA#1 DDPB_1P
49 LVDSA_DATA2# AK47 LVDSA_DATA#2 DDPB_2N AU48 HDMI_DATA0_R# 51
AJ48 LVDSA_DATA#3 DDPB_2P AU47 HDMI_DATA0_R 51
X02-0303 change 0R to short pad DDPB_3N AV47 HDMI_CLK_R# 51
49 LVDSA_DATA0 AN47 LVDSA_DATA0 DDPB_3P AV49 HDMI_CLK_R 51
49 LVDSA_DATA1 AM49 LVDSA_DATA1
49 LVDSA_DATA2 AK49 LVDSA_DATA2
AJ47 LVDSA_DATA3 DDPC_CTRLCLK P46
DDPC_CTRLDATA P42
AF40 LVDSB_CLK#
AF39 LVDSB_CLK DDPC_AUXN AP47
DDPC_AUXP AP49
AH45 LVDSB_DATA#0 DDPC_HPD AT38
AH47 LVDSB_DATA#1
AF49 LVDSB_DATA#2 DDPC_0N AY47
AF45 LVDSB_DATA#3 DDPC_0P AY49
DDPC_1N AY43
AH43 LVDSB_DATA0 DDPC_1P AY45
AH49 LVDSB_DATA1 DDPC_2N BA47
AF47 LVDSB_DATA2 DDPC_2P BA48
Close to PCH side AF43 LVDSB_DATA3 DDPC_3N BB47
DDPC_3P BB49
11/19 Del R1703~R1705
PCH_CRT_BLUE
PCH_CRT_GREEN 50 PCH_CRT_BLUE N48 M43
PCH_CRT_RED CRT_BLUE DDPD_CTRLCLK
50 PCH_CRT_GREEN P49 CRT_GREEN DDPD_CTRLDATA M36
50 PCH_CRT_RED T49 CRT_RED
B B
AT45
CRT
DDPD_AUXN
50 PCH_CRT_DDCCLK T39 CRT_DDC_CLK DDPD_AUXP AT43
50 PCH_CRT_DDCDATA M40 CRT_DDC_DATA DDPD_HPD BH41
5
6
7
8
RN1705 BB43
SRN150F-1-GP DDPD_0N
50 PCH_CRT_HSYNC M47 CRT_HSYNC DDPD_0P BB45
50 PCH_CRT_VSYNC M49 CRT_VSYNC DDPD_1N BF44
DDPD_1P BE44
BF42
4
3
2
1
DAC_IREF_R DDPD_2N
T43 DAC_IREF PCH1 DDPD_2P BE42
T42 CRT_IRTN DDPD_3N BJ42
1
DDPD_3P BG42
11/20 Add C1722~C1724 R1702
1KR2D-1-GP COUGAR-GP-U2-NF
Notes:
P/N: ND27V
2
2 1C1722 PCH_CRT_BLUE
1K 0.5% 0402.
DY SC10P50V2JN-4GP
CHIP RES 1K D 1/16W 0402
2 1C1723 PCH_CRT_GREEN
DY SC10P50V2JN-4GP
2 1C1724 PCH_CRT_RED
DY SC10P50V2JN-4GP
A <Core Design> A
Wistron Corporation
Title
PCH (LVDS/CRT/DDI)
A3
5 4 3 2 1
5 4 3 2 1
1D8V_S0
SSID = PCH
1
PCH1E 5 OF 10
AY7 R1808
RSVD
Cougar RSVD AV7 2K2R2J-2-GP
BG26 TP1 RSVD AU3
12/2 Net swap for layout BJ26 Point BG4 R1809
2
TP2 RSVD
BH25 TP3
BJ16 AT10 NV_CLE 1 2
TP4 RSVD H_SNB_IVB# 5
BG16 BC8 1KR2J-1-GP
TP5 RSVD
D RN1801 AH38 D
INT_PIRQB# TP6
1 10 3D3V_S0 AH37 TP7 RSVD AU2
INT_PIRQD# 2 9 INT_PIRQE# AK43 TP8 RSVD AT4 DMI & FDI Termination Voltage
INT_PIRQC# 3 8 INT_PIRQA# AK45 AT3
TP9 RSVD
INT_PIRQF# 4 7 INT_PIRQH# C18 AT1 Set to Vss when LOW
INT_PIRQG# TP10 RSVD NV_CLE
3D3V_S0 5 6 N30 TP11 RSVD AY3
H3 AT5 Set to Vcc when HIGH
TP12 RSVD
SRN8K2J-2-GP-U AH12 AV3
NVRAM
TP13 RSVD
AM4 TP14 RSVD AV1
AM5 TP15 RSVD BB1
Y13 TP16 RSVD BA3
K24 TP17 RSVD BB5
L24 TP18 RSVD BB3
AB46 TP19 RSVD BB7
AB45 BE8 1D8V_S0
RSVD
R1801 TP20 RSVD
1 4K7R2J-2-GP PCI_GNT3#
2
DY RSVD BD4
BF6
RSVD
1
Danbury Technology:
B21 AV5 NV_ALE Disabled when Low. R1810
TP21 RSVD NV_CLE 1KR2J-1-GP
M20
AY16
TP22 DF_TVS AY1 Enable when High. DY
A16 swap override Strap/Top-Block TP23 NV_RCOMP TP1803 TPAD14-GP
BG46 AV10 1
2
TP24 RSVD
Swap Override jumper
AT8 NV_ALE
RSVD
PCI_GNT#3 Low = A16 swap RN1803 BE28 AY5
DGPU_HOLD_RST# TP25 RSVD
override/Top-Block 1 4 BC30 TP26 RSVD BA2
Swap Override enabled DGPU_PWR_EN# 2 3 BE32 TP27
High = Default BJ32 TP28 RSVD AT12
C SRN10KJ-5-GP BC28 BF3 C
TP29 RSVD
BE30 TP30 USB Ext. port 1 (HS)
BF32
BG32
TP31
C24
External debug port use on Huron river platform
TP32 USBP0N
AV26 TP33 USBP0P A24
BB26 TP34 USBP1N C25 USB_PN1 61
AU28 TP35 USBP1P B25 USB_PP1 61
AY30 TP36 USBP2N C26
AU26 TP37 USBP2P A26
2R1802 BBS_BIT1
1
DY 1KR2J-1-GP
AY26
AV28
TP38 USBP3N K28
H28 USB Table
TP39 USBP3P
2R1803 BBS_BIT0
1
DY 1KR2J-1-GP BBS_BIT0 21 AW30 TP40 USBP4N E28
D28
3D3V_S0 USBP4P
USBP5N C28 USB_PN5 32 Pair Device
USBP5P A28 USB_PP5 32
USBP6N C29 0 X
2 USBP6P B29
BOOT BIOS Strap INT_PIRQA# K40 PIRQA# USBP7N N28 1 USB Ext. port 2 (MB)
R1814 INT_PIRQB# K38 M28
PCI
PIRQB# USBP7P
GNT1#/GPIO51 SATA1GP/GPIO19 BOOT BIOS Location 8K2R2J-3-GP INT_PIRQC# H38 L30 USB_PN8 82 2 X
INT_PIRQD# PIRQC# USBP8N
G38 PIRQD# USBP8P K30 USB_PP8 82
0 0 LPC G30 USB_PN9 82 3 X
1
USBP9N
83 DGPU_HOLD_RST# C46 E30
USB
REQ1#/GPIO50 USBP9P USB_PP9 82
0 1 Reserved TPAD14-GP TP1807 1 DGPU_SELECT# C44 REQ2#/GPIO52 USBP10N C30 4 X
93 DGPU_PWR_EN# DGPU_PWR_EN# E40 A30
REQ3#/GPIO54 USBP10P
1 0 Reserved USBP11N L32 USB_PN11 65 5 CARD READER
BBS_BIT1 D47 K32 USB_PP11 65
GNT1#/GPIO51 USBP11P
1 1 SPI(Default) TPAD14-GP TP1806 1 PCH_GPIO53 E42 GNT2#/GPIO53 USBP12N G32 USB_PN12 49 6 X
TPAD14-GP TP1801 1 PCI_GNT3# F46 E32 USB_PP12 49
B GNT3#/GPIO55 USBP12P B
USBP13N C32 7 X
USBP13P A32
INT_PIRQE# G42 PIRQE#/GPIO2 8 USB Ext. port 3
56 SATA_ODD_DA# 1R1813 2 INT_PIRQF# G40 PIRQF#/GPIO3
0R0402-PAD INT_PIRQG# C42 PIRQG#/GPIO4 USBRBIAS# C33 USB_RBIAS 1 2 9 USB Ext. port 1
INT_PIRQH# D44 R1811
PIRQH#/GPIO5 22D6R2F-L1-GP 10 X
USBRBIAS B33
TPAD14-GP TP1802 1 PCI_PME# K10 PME# 11 Mini Card1 (WLAN+BT)
X02-0311 dummy R1804 PCI_PLTRST# C6 PLTRST# OC0#/GPIO59 A14 USB_OC#0_1 USB_OC#0_1 61 12 CAMERA
K20 USB_OC#2_3
OC1#/GPIO40
DY OC2#/GPIO41 B17 USB_OC#4_5 13 X
71 CLK_PCI_LPC R1804 1 2 22R2J-2-GP CLK_PCI_LPC_R H49 C16 USB_OC#6_7
R1805 CLKOUT_PCI0 OC3#/GPIO42
20 CLK_PCI_FB 1 2 22R2J-2-GP CLK_PCI_FB_R H43 CLKOUT_PCI1 OC4#/GPIO43 L16 USB_OC#8_9 USB_OC#8_9 61
27 CLK_PCI_KBC R1806 1 2 22R2J-2-GP CLK_PCI_KBC_R J48 A16 USB_OC#10_11
CLKOUT_PCI2 OC5#/GPIO9 USB_OC#12_13
K42 CLKOUT_PCI3 PCH1 OC6#/GPIO10 D14
PCH_GPIO14
H40 CLKOUT_PCI4 OC7#/GPIO14 C14
2
EC1802 EC1801 EC1803

DY DY DY COUGAR-GP-U2-NF
SC33P50V2JN-3GP
SC33P50V2JN-3GP
SC4D7P50V2CN-1GP
KBC CLK EMI P/N: ND27V

1
X02-0303 change 0R to short pad OC[3:0]# for Device 29 (Ports 0-7)

OC[7:4]# for Device 26 (Ports 8-13)
5,27,31,65,71,83 PLT_RST# 1 R1807 2 PCI_PLTRST#

0R0402-PAD
A <Core Design> A
12/1 Swap net for layout
11/11 change to RN1802 to meet schematic check result. Wistron Corporation
1
R1816 RN1802 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

DYC1801 PCH_GPIO14 Taipei Hsien 221, Taiwan, R.O.C.
DY 1 10
100KR2J-1-GP
3D3V_S5
SC220P50V2KX-3GP USB_OC#6_7 2 9 USB_OC#0_1
2
USB_OC#10_11 3 8 USB_OC#12_13 Title

2
USB_OC#4_5 USB_OC#8_9
3D3V_S5
4
5
7
6 USB_OC#2_3 PCH (PCI/USB/NVRAM)
A3
SRN8K2J-2-GP-U
5 4 3 2 1
5 4 3 2 1
SSID = PCH
PCH1C 3 OF 10
4 DMI_RXN[3:0] FDI_TXN[7:0] 4
DMI_RXN0 FDI_TXN0
Signal Routing Guideline: DMI_RXN1
BC24
BE20
DMI0RXN Cougar FDI_RXN0 BJ14
AY14 FDI_TXN1
DMI1RXN FDI_RXN1
DMI_ZCOMP keep W=4 mils and DMI_RXN2
DMI_RXN3
BG18
BG20
DMI2RXN Point FDI_RXN2 BE14
BH13
FDI_TXN2
FDI_TXN3
D
routing length less than 500 DMI3RXN FDI_RXN3
BC12 FDI_TXN4 D
mils. 4 DMI_RXP[3:0] FDI_RXN4
DMI_RXP0 BE24 BJ12 FDI_TXN5
DMI0RXP FDI_RXN5
DMI_IRCOMP keep W=4 mils and DMI_RXP1 BC20 DMI1RXP FDI_RXN6 BG10 FDI_TXN6
routing length less than 500 DMI_RXP2 BJ18 BG9 FDI_TXN7
DMI_RXP3 DMI2RXP FDI_RXN7
BJ20
mils. DMI3RXP
BG14 FDI_TXP0 FDI_TXP[7:0] 4
4 DMI_TXN[3:0] DMI_TXN0 FDI_RXP0 FDI_TXP1
AW24 DMI0TXN FDI_RXP1 BB14
DMI_TXN1 AW20 BF14 FDI_TXP2
DMI_TXN2 DMI1TXN FDI_RXP2 FDI_TXP3
BB18 DMI2TXN FDI_RXP3 BG13
DMI_TXN3 AV18 BE12 FDI_TXP4
DMI
FDI
DMI3TXN FDI_RXP4 FDI_TXP5
4 DMI_TXP[3:0] FDI_RXP5 BG12
DMI_TXP0 AY24 BJ10 FDI_TXP6
DMI_TXP1 DMI0TXP FDI_RXP6 FDI_TXP7
AY20 DMI1TXP FDI_RXP7 BH9
DMI_TXP2 AY18
DMI_TXP3 DMI2TXP
AU18 DMI3TXP
FDI_INT AW16 FDI_INT 4
1D05V_VTT BJ24 AV12
DMI_ZCOMP FDI_FSYNC0 FDI_FSYNC0 4 For platforms not supporting Deep S4/S5
R1901 249D9R2F-GP DMI_COMP_R
1 BG25 DMI_IRCOMP FDI_FSYNC1 BC10 FDI_FSYNC1 4 1.VccSUS3_3 and VccDSW3_3 will rise at the same time (connected on board)
R1902 1 2750R2F-GP RBIAS_CPY BH21 DMI2RBIAS FDI_LSYNC0 AV14 FDI_LSYNC0 4 2.DPWROK and RSMRST# will rise at the same time (connected on board)
FDI_LSYNC1 BB10 FDI_LSYNC1 4 3.SLP_SUS# and SUSACK# are left as ˉno connectˇ
DY
2 1R1926 SYS_PWROK 4.SUSWARN# used as SUSPWRDNACK/GPIO30
10KR2J-3-GP X02-0303 change 0R to short pad
2 1R1904 PWROK
DSWVRMEN A18 DSWODVREN
100KR2J-1-GP 1R1910 2 PM_RSMRST#
System Power Management

C 0R0402-PAD C
SUS_PWR_ACK 1R1903 2 SUSACK# C12 E22 PCH_DPWROK 1 2 RTC_AUX_S5
0R0402-PAD SUSACK# DPWROK R1911 10KR2J-3-GP
DY
5 XDP_DBRESET# 1R1925 2 SYS_RESET# K3 SYS_RESET# WAKE# B9 PCH_WAKE# 27
0R0402-PAD
1R1905
36
3D3V_S0
SYS_PWROK 10KR2J-3-GPDY2 P12 N3
SYS_PWROK CLKRUN#/GPIO32 PM_CLKRUN# 27
1R1923 2
DY 0R2J-2-GP
27,36 S0_PWR_GOOD 1R1924 2 PWROK L22 PWROK SUS_STAT#/GPIO61 G8 PM_SUS_STAT# 1 TP1901 TPAD14-GP
0R0402-PAD
2 1R1906
45,46,47 RUNPWROK 1 R1907 2 MEPWROK 0R0402-PAD L10 APWROK SUSCLK/GPIO62 N14 SUS_CLK 1R1913 2 PCH_SUSCLK_KBC 27
0R2J-2-GP 0R0402-PAD DSWODVREN - On Die DSW VR Enable
DY
5,37 PM_DRAM_PWRGD B13 D10 PM_SLP_S5# 1 HIGH Enabled (DEFAULT)
DRAMPWROK SLP_S5#/GPIO63 TP1902 TPAD14-GP
S0_PWR_GOOD after PM_SLP_S3# delay 200 ms
PM_RSMRST# C21 H4 LOW Disabled
RSMRST# SLP_S4# PM_SLP_S4# 27,46
27 SUS_PWR_ACK K16 SUSWARN#/SUSPWRDNACK/GPIO30 SLP_S3# F4 PM_SLP_S3# 27,36,37,47 RTC_AUX_S5
27 PM_PWRBTN# E20 G10 PM_SLP_A# 1

PWRBTN# SLP_A# TP1903 TPAD14-GP R1917 1 2 330KR2J-L1-GP
27 AC_PRESENT H20 G16 PM_SLP_SUS# 1

B ACPRESENT/GPIO31 SLP_SUS# TP1904 TPAD14-GP DSWODVREN R1918 B
2 330KR2J-L1-GP
1
DY
BATLOW# E10 PCH1 AP14 H_PM_SYNC
BATLOW#/GPIO72 PMSYNCH H_PM_SYNC 5
PM_RI# A10 K14 PM_SLP_LAN# 1

RI# SLP_LAN#/GPIO29 TP1905 TPAD14-GP
COUGAR-GP-U2-NF
3D3V_S0
P/N: ND27V PM_RSMRST# 1R1912 2 RSMRST#_KBC 27
0R0402-PAD
PM_CLKRUN# R1919 1 2 8K2R2J-3-GP
3D3V_S5 12/2 Swap net for layout
RN1901
8 1 BATLOW#
7 2 PCH_WAKE#
6 3 PM_RI# PCH_SUSCLK_KBC
5 4 SUS_PWR_ACK
2
SRN10KJ-6-GP
PCIE_WAKE# EC1901
CRB : 1K DY
SC4D7P50V2CN-1GP
2 R1909
1 AC_PRESENT
10KR2J-3-GP CEKLT: 10K
A
DY
2 1R1922 PM_PWRBTN# <Core Design> A
10KR2J-3-GP
DY 1R1920 PM_SLP_LAN#
2
10KR2J-3-GP Wistron Corporation
2 R1908
1 PM_RSMRST# Title
10KR2J-3-GP
PCH (DM I/FDI/PM)
A3
5 4 3 2 1
5 4 3 2 1
3D3V_S5 3D3V_S5
CLK_PCH_48M
SSID = PCH
1
R2004 SMB_CLK 4 1 RN2003
2
10KR2J-3-GP SMB_DATA 3 2 SRN2K2J-1-GP
EC2001 UMA
SML0_DATA 1 RN2004
DY 4
2
PCH1B 2 OF 10 PEG_CLKREQ#_R SML0_CLK 3 2 SRN2K2J-1-GP
SC4D7P50V2CN-1GP
1
BG34
BJ34
PERN1 Cougar E12 EC_SWI# R2005
SML1_CLK
SML1_DATA
2
1
3 RN2005
4 SRN2K2J-1-GP
PERP1 SMBALERT#/GPIO11 EC_SWI# 27
AV32 PETN1 Point SMB_CLK DIS 10KR2J-3-GP
PCIE_CLK_REQ6#
AU32 PETP1 W-WAN SMBCLK H14 1 4 RN2006
D PCH_GPIO74 2 3 SRN10KJ-5-GP D
2
BE34 C9 SMB_DATA
31 PCIE_RXN2 PERN2 SMBDATA
31 PCIE_RXP2 BF34 PERP2
C2001 2 SCD1U10V2KX-5GP PCIE_TXN2_C
31 PCIE_TXN2 C2002
1
1 2 SCD1U10V2KX-5GP PCIE_TXP2_C
BB32
AY32
PETN2 LAN DRAMRST_CNTRL_PCH 1 R2009 2
SMBUS
31 PCIE_TXP2 PETP2 DRAMRST_CNTRL_PCH 1KR2J-1-GP
SML0ALERT#/GPIO60 A12 DRAMRST_CNTRL_PCH 37
BG36 PERN3
BJ36 C8 SML0_CLK 3D3V_S0
PERP3 SML0CLK
AV34
AU34
PETN3 Card Reader G12 SML0_DATA RN2007
PETP3 SML0DATA
2 3
65 PCIE_RXN4
65 PCIE_RXP4
C2005
BF36
BE36
PERN4
PERP4 WLAN
1 4
CRB : 1K
1 2 SCD1U10V2KX-5GP PCIE_TXN4_C AY34 C13 PCH_GPIO74 SRN2K2J-1-GP
65 PCIE_TXN4
65 PCIE_TXP4
C2006 1 2 SCD1U10V2KX-5GP PCIE_TXP4_C BB34
PETN4
PETP4
SML1ALERT#/PCHHOT#/GPIO74
E14 SML1_CLK 2nd = 84.DM601.03F CEKLT: 10K
PCI-E*
SML1CLK/GPIO58 SML1_CLK 27,85
BG37 84.2N702.A3F
PERN5 SML1_DATA
BH37 PERP5 SML1DATA/GPIO75 M16 SML1_DATA 27,85 2N7002KDW-GP
AY36
BB36
PETN5 USB3.0 SMB_DATA 6 1
PETP5 PCH_SMBDATA 14,15,65
BJ38 PERN6 5 2
BG38
Controller
PERP6 CL_CLK 1
12/2 Swap net for layout
AU36
AV36
PETN6 Intel GBE LAN CL_CLK1 M7
TP2001 TPAD14-GP
4 3
PETP6
Q2001
Link
BG40 T11 CL_DATA1
PERN7 CL_DATA1 PCH_SMBCLK 14,15,65
RN2001 BJ40 TP2002 TPAD14-GP
PERP7 SMB_CLK
C PCIE_CLK_REQ0#
1
2
10
9 PEG_B_CLKRQ#
3D3V_S5 AY40
BB40
PETN7 Dock P10 CL_RST#1 C
PCIE_CLK_LAN_REQ# 3 PCIE_CLK_REQ4# PETP7 CL_RST1# TP2003 TPAD14-GP
8
PCIE_CLK_REQ5# 4 7 CLK_PCIE_REQ7# BE38
EC_SWI# PERN8
3D3V_S5 5 6 BC38
AW38
PERP8 NEW CARD
PETN8
SRN10KJ-L3-GP AY38 PETP8 C2008
PEG_A_CLKRQ#/GPIO47 M10 PEG_CLKREQ#_R 1 DY 2R2003 PEG_CLKREQ# 85 XTAL25_IN 2 1
RN
Y40 0R2J-2-GP
CLKOUT_PCIE0N
Y39 CLKOUT_PCIE0P WWAN CLK RN2016 12/6 swap net for layout SC15P50V2JN-2-GP
AB37 CLKOUT_PEG_A_N 1 4 CLK_PCIE_VGA# 83
CLKOUT_PEG_A_N
CLOCKS
PCIE_CLK_REQ0# J2 AB38 CLKOUT_PEG_A_P 2 3 CLK_PCIE_VGA 83
PCIECLKRQ0#/GPIO73 CLKOUT_PEG_A_P 0R4P2R-PAD
3
X2001
65 CLK_PCIE_WLAN# 2 RN2012 3 CLK_PCH_SRC1_N AB49 CLKOUT_PCIE1N CLKOUT_DMI_N AV22 CLKOUT_DMI_N 2 RN2010 3 CLK_EXP_N 5
2
CLK_PCH_SRC1_P CLKOUT_DMI_P XTAL-25MHZ-155-GP
65 CLK_PCIE_WLAN 1 4
0R4P2R-PAD
AB47 CLKOUT_PCIE1P WLAN CLK CLKOUT_DMI_P AU22 1 4
0R4P2R-PAD
CLK_EXP_P 5
R2006
65 CLK_PCIE_WLAN_REQ# M1 1M1R2J-GP
PCIECLKRQ1#/GPIO18
RN
RN
AM12
2
CLKOUT_DP_N
AM13
1
CLKOUT_DP_P
AA48 CLKOUT_PCIE2N
AA47 CLKOUT_PCIE2P
BF18 CLK_BUF_EXP_N C2007
CLKIN_DMI_N
12/6 swap net for layout PCIE_CLK_REQ2# V10 PCIECLKRQ2#/GPIO20 CLKIN_DMI_P BE18 CLK_BUF_EXP_P XTAL25_OUT 2 1
RN
RN2008
31 CLK_PCIE_LAN# 1RN2014 4 CLK_PCH_SRC3_N Y37 CLKOUT_PCIE3N CLKIN_GND1_N BJ30 CLK_BUF_CPYCLK_N 2 3 SC15P50V2JN-2-GP
CLK_PCH_SRC3_P CLK_BUF_CPYCLK_P
31 CLK_PCIE_LAN 2
0R4P2R-PAD
3 Y36 CLKOUT_PCIE3P LAN CLK CLKIN_GND1_P BG30 1
SRN10KJ-5-GP
4
B B
31 PCIE_CLK_LAN_REQ# A8 PCIECLKRQ3#/GPIO25 11/29 change X2001 to 82.30020.D41
A00-0413 SWAP RN2014 net for layout CLKIN_DOT_96N G24 CLK_BUF_DOT96_N
CLKIN_DOT_96P E24 CLK_BUF_DOT96_P PL 10K FOR Integrated CLOCK GEN mode. X01-0217 change C2008 , C2007 to 15pF
Y43 CLKOUT_PCIE4N
3D3V_S0
RN2018
Y45 CLKOUT_PCIE4P USB3.0 CLK AK7 CLK_BUF_CKSSCD_N RN2020 SRN10KJ-5-GP
CLKIN_SATA_N
1 4 PCIE_CLK_REQ2# PCIE_CLK_REQ4# L12 PCIECLKRQ4#/GPIO26 CLKIN_SATA_P AK5 CLK_BUF_CKSSCD_P CLK_BUF_DOT96_N 2 3 UMA_DISCRETE#
2 3 CLK_PCIE_WLAN_REQ# CLK_BUF_DOT96_P 1 4 3D3V_S0 3D3V_S0
UMA: 1 1
SRN10KJ-5-GP CLK_BUF_REF14 DIS :0 1
V45 CLKOUT_PCIE5N REFCLK14IN K45
1
RN2021 SRN10KJ-5-GP SG(PX) : 0 0
PCIECLKRQ1# and PCIECLKRQ2# V46 CLKOUT_PCIE5P CLK_BUF_CKSSCD_N 2 3 R2012 R2013 Optimus(Muxless) : 1 0
Support S0 power only PCIE_CLK_REQ5# L14 H45 CLK_PCI_FB CLK_BUF_CKSSCD_P 1 4
10KR2J-3-GP
10KR2J-3-GP
PCIECLKRQ5#/GPIO44 CLKIN_PCILOOPBACK CLK_PCI_FB 18
UMA
12/6 swap net for layout
2
AB42 V47 XTAL25_IN RN2019 SRN10KJ-5-GP UMA_DIS# UMA_DIS# 22
CLKOUT_PEG_B_N XTAL25_IN XTAL25_OUT CLK_BUF_EXP_N DGPU_PRSNT#
AB40 CLKOUT_PEG_B_P XTAL25_OUT V49 2 3
CLK_BUF_EXP_P 1 4
1
PEG_B_CLKRQ# E6 PEG_B_CLKRQ#/GPIO56 R2010 R2011
Y47 XCLK_RCOMP
1 2R2007 DY DIS
10KR2J-3-GP
10KR2J-3-GP
XCLK_RCOMP +VCCDIFFCLKN
V40 PCH1 90D9R2F-1-GP CLK_BUF_REF14 R2008
1 2
CLKOUT_PCIE6N 10KR2J-3-GP
V42
2
CLKOUT_PCIE6P
PCIE_CLK_REQ6# T13 PCIECLKRQ6#/GPIO45
11/1 Add EC2002~EC2007 for EMI request V38 K43 JTAG_TCK R2001 1 2
DY
CLKOUT_PCIE7N CLKOUTFLEX0/GPIO64 JTAG_TCK_VGA 83,85
22R2J-2-GP
V37 NEWCARD CLK
FLEX CLOCKS
CLKOUT_PCIE7P CLK_48_USB30 R2016 1

A CLKOUTFLEX1/GPIO65 F47 2 CLK_PCH_48M 32 <Core Design> A
CLK_PCIE_WLAN# 2 DY1EC2002 CLK_PCIE_REQ7# K12 22R2J-2-GP
SC22P50V2JN-4GP PCIECLKRQ7#/GPIO46 CLK_27M_VGA_R
CLKOUTFLEX2/GPIO66 H47 1
CLK_PCIE_WLAN 2 DY1EC2003 ITPXDP_N TP2007 TPAD14-GP
SC22P50V2JN-4GP TPAD14-GP TP2005
1
1 ITPXDP_P
AK14
AK13
CLKOUT_ITPXDP_N
CLKOUT_ITPXDP_P CLKOUTFLEX3/GPIO67 K49 DGPU_PRSNT# Wistron Corporation
CLK_PCIE_LAN 2 DY1EC2004 TPAD14-GP TP2006 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
SC22P50V2JN-4GP Taipei Hsien 221, Taiwan, R.O.C.
CLK_PCIE_LAN# 2 DY1EC2005 COUGAR-GP-U2-NF
P/N: ND27V 11/18 Del VGA 27M and change to TP2007
Title

SC22P50V2JN-4GP
PCH (PCI-E/SMBUS/CLOCK/CL)
JTAG_TCK_VGA 2 DY1EC2007
SC22P50V2JN-4GP if Prioritize 27/14/24/48/25-MHz FLEX on FLEX1 and FLEX3
Do not configure 27/14/24/48/25-MHz FLEX clock on FLEX0 and FLEX2
more than 2 PCI clocks + PCI loopback are routed.
Size
A3
Document Number
Enrico Caruso 14
Rev
A00
5 4 3 2 1
5 4 3 2 1
RTC_AUX_S5
SSID = PCH X01-0210 Merge R2115 R2116
RN2106
2 3 INTVRMEN- Integrated SUS
1 4
RTC_X1 1.05V VRM Enable X01-0208 Add RN2101, R2127 for LPC EA result
1
SRN20KJ-1-GP C2103 High - Enable internal VRs X01-0210 change RN2101 to RN2104 RN2105
1 2 RTC_X2 SC1U6D3V2KX-GP
R2101 10MR2J-L-GP
Low - Enable external VRs
2
LPC_AD[0..3]
LPC_AD[0..3] 27,71
D RN2104 SRN33J-5-GP-U D
PCH1A 1 OF 10 2 3 LPC_AD0
X2101
1 4 LPC_AD1
RTC_X1 LPC_AD0_R
1 4 A20 RTCX1 Cougar FWH0/LAD0 C38
A38 LPC_AD1_R RN2105 SRN33J-5-GP-U
FWH1/LAD1
Point
LPC
RTC_X2 C20 B37 LPC_AD2_R 1 4 LPC_AD2
SC15P50V2JN-2-GP
RTCX2 FWH2/LAD2
1
1
C2101
2 3 C37 LPC_AD3_R 2 3 LPC_AD3

C2102 RTC_RST# FWH3/LAD3
D20 RTCRST#
X-32D768KHZ-67-GP SC15P50V2JN-2-GP D36 LPC_FRAME#_R 2 1 R2127 LPC_FRAME# 27,71
2
2
FWH4/LFRAME#
2
G2101 1M1R2J-GP SRTC_RST# G22 33R2J-2-GP
82.30001.A81 SRTCRST#
1
C2104 R2104 E36
LDRQ0#
RTC
SC1U6D3V2KX-GP 2 1 SM_INTRUDER# K22 K36 KB_DET# 69
INTRUDER# LDRQ1#/GPIO23
2nd = 82.30001.691 GAP-OPEN
2
3rd = 82.30001.861 RTC_AUX_S5 1 2 PCH_INTVRMEN C17 V5 INT_SERIRQ 27
1
INTVRMEN SERIRQ
R2105
330KR2F-L-GP AM3 SATA_RXN0 56
HDA_BITCLK SATA0RXN
33R2J-2-GP2 1R2123 HDA_SDOUT
N34 HDA_BCLK SATA0RXP AM1
SATA_TXN0_C SCD01U16V2KX-3GP 2 1 C2114
SATA_RXP0 56
HDD1
SATA 6G
29 HDA_CODEC_SDOUT SATA0TXN AP7 SATA_TXN0 56
HDA_SYNC L34 AP5 SATA_TXP0_C SCD01U16V2KX-3GP 2 1 C2113 SATA_TXP0 56
HDA_SYNC SATA0TXP
29 HDA_SPKR T10 SPKR SATA1RXN AM10

RN2102 AM8
HDA_RST# HDA_RST# SATA1RXP
29 HDA_CODEC_RST# 1 4 K34 HDA_RST# SATA1TXN AP11
2 3 HDA_BITCLK AP10
29 HDA_CODEC_BITCLK SATA1TXP
SRN33J-5-GP-U 29 HDA_SDIN0 E34 AD7
HDA_SDIN0 SATA2RXN
SATA2RXP AD5
G34 AH5
C Notes: HDA_SDIN1 SATA2TXN
AH4 C
SATA2TXP
ME_UNLOCK (HDA_SDO) connect to EC. C34 HDA_SDIN2
IHDA
SATA3RXN AB8
Make sure EC drive this pin "low" all the time. A34 HDA_SDIN3 SATA3RXP AB10
AF3
SATA3TXN
SATA3TXP AF1
Flash Descriptor Security Overide HDA_SDOUT A36 HDA_SDO
1 R2107 2 1KR2J-1-GP
SATA
27 ME_UNLOCK SATA4RXN Y7 SATA_RXN4 56
Low = Default
+3VS_+1.5VS_HDA_IO
HDA_SDOUT High = Enable TPAD14-GP TP2105
1PCH_GPIO33 C36 HDA_DOCK_EN#/GPIO33
SATA4RXP
SATA4TXN
Y5
AD3 SATA_TXN4_C
SATA_TXP4_C
C2111 1
C2112 1
2SCD01U16V2KX-3GP
SATA_RXP4
SATA_TXN4
56
56 ODD
SATA4TXP AD1 2SCD01U16V2KX-3GP SATA_TXP4 56
N32 HDA_DOCK_RST#/GPIO13
1R2102
DY
2 HDA_SDOUT SATA5RXN Y3
Y1
1KR2J-1-GP SATA5RXP
SATA5TXN AB3
TPAD14-GP TP2101 1 PCH_JTAG_TCK_BUF J3 AB1
JTAG_TCK SATA5TXP
NO REBOOT STRAP TPAD14-GP TP2102 1 PCH_JTAG_TMS H7 Y11 1D05V_VTT
3D3V_S0 JTAG_TMS SATAICOMPO
JTAG
No Reboot Strap TPAD14-GP TP2103 1 PCH_JTAG_TDI K5 Y10 SATA_COMP R2112 1 2 37D4R2F-GP
JTAG_TDI SATAICOMPI
1R2106
DY
2 HDA_SPKR Low = Default TPAD14-GP TP2104 1 PCH_JTAG_TDO H1 1D05V_VTT
1KR2J-1-GP JTAG_TDO
HDA_SPKR High = No Reboot SATA3RCOMPO AB12
AB13 SATA3_COMP R2113 1 2 49D9R2F-GP

SATA3COMPI
+3VS_+1.5VS_HDA_IO 1 2 PCH_SPI_CLK T3 AH1 RBIAS_SATA3 R2114 1 2 750R2F-GP

27,60 SPI_CLK_R SPI_CLK SATA3RBIAS
R2108 33R2J-2-GP
B B
1 R2103 2 1KR2J-1-GP HDA_SYNC 27,60 SPI_CS0#_R 1 2 PCH_SPI_CS0# Y14 SPI_CS0# PCH1
R2109 33R2J-2-GP
This signal has a weak internal pull down. T1 SPI_CS1#
SPI
On Die PLL VR is supplied by 1.5V when SATALED# P3 SATA_LED# 68
sampled high, 1.8 V when sampled low. PCH_SPI_SI SATA_DET#0
27,60 SPI_SI_R 1 2 V4 SPI_MOSI SATA0GP/GPIO21 V14
Needs to be pulled High for Huron River platform. R2110 33R2J-2-GP
co-operate with R2310 27,60 SPI_SO_R 2 1 PCH_SPI_SO U3 P1 BBS_BIT0 BBS_BIT0 18
ER2111 0R0402-PAD SPI_MISO SATA1GP/GPIO19
11/1 Add R2111 for EMI request COUGAR-GP-U2-NF

P/N: ND27V
PLL ODVR VOLTAGE
11/ 17 change R2111 from 33ohm to 0ohm and change to ER2111
Low = 1.8V (Default)
HDA_SYNC High = 1.5V
HDA_SYNC: This strap is sampled on rising edge of RSMRST# and is used to 3D3V_S0
RN2103
sample 1.5V VccVRM supply mode. 1K external pull-up resistor is required on this INT_SERIRQ 1 4
signal on the board. Signal may have leakage paths via powered off devices (Audio SATA_DET#0 2 3
Codec) and hence contend with the external pull-up. A blocking FET is SRN10KJ-5-GP
recommended in such a case to isolate HDA_SYNC from the Audio Codec device
22 S_GPIO 1R2125 2
11/2 Merge R2122 into Q2101 until after the Strap sampling is complete. 10KR2J-3-GP
22 PSW_CLR# 1R2126 2
HDA_CODEC_BITCLK HDA_CODEC_SDOUT SPI_CS0#_R 10KR2J-3-GP
RUN_ENABLE
A Q2101 <Core Design> A
2
G 12/6 Separate RN2103 to

EC2102 EC2103 EC2101
HDA_SYNC_R2 R2124 1 HDA_SYNC
R2125 and R2126
D
DY DY DY Wistron Corporation
1
1
SC4D7P50V2CN-1GP
SC4D7P50V2CN-1GP
SC4D7P50V2CN-1GP
HDA_CODEC_SYNC S 33R2J-2-GP 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

29 HDA_CODEC_SYNC Taipei Hsien 221, Taiwan, R.O.C.
R2117
100KR2J-1-GP
2
2N7002K-2-GP
84.2N702.J31 Title
2ND = 84.2N702.031
11/11Remove RN2104 and FP_DET# PCH (SPI/RTC/LPC/SATA/IHDA)
1
33R2J-2-GP2 1R2122 A3
DY Enrico Caruso 14 A00
5 4 3 2 1
5 4 3 2 1
SSID = PCH Note:

For PCH debug with XDP, need to DUMMY R2218
PCH1F 6 OF 10
S_GPIO 1 R2218 2 PCH_GPIO0 T7

21 S_GPIO 100R2J-2-GP BMBUSY#/GPIO0 Cougar TACH4/GPIO68 C40 SATA_ODD_PWRGT 56
27 EC_SMI# EC_SMI# A42 TACH1/GPIO1 Point TACH5/GPIO69 B41 UMA_DIS# UMA_DIS# 20

DGPU_HPD_INTR# H36 C41 PCH_GPIO70 1 TP2204 TPAD14-GP
TACH2/GPIO6 TACH6/GPIO70
D D
EC_SCI# E38 A40 PCH_GPIO71 1 TP2205 TPAD14-GP
27 EC_SCI# TACH3/GPIO7 TACH7/GPIO71
TPAD14-GP TP2219 1 ICC_EN# C10
3D3V_S0 GPIO8
60 RTC_SENSE# RTC_SENSE# C4
R2202 LAN_PHY_PWR_CTRL/GPIO12
1 2 SATA_ODD_PRSNT# PCH_GPIO15 G2 P4 H_A20GATE 27
GPIO15 A20GATE
100KR2J-1-GP X02-0303 change 0R to short pad AU16 H_PECI_R 1R2203
DY
2 H_PECI 5,27
CPU/MISC
PECI 0R2J-2-GP
56 SATA_ODD_PRSNT# 2 R2213 1 PCH_GPIO16 U2 SATA4GP/GPIO16
3D3V_S0 0R0402-PAD P5 H_RCIN# 27
RCIN#
GPIO
RN2203 86,92,93 DGPU_PWROK DGPU_PWROK D40 AY11 H_CPUPWRGD 5,36
H_A20GATE TACH0/GPIO17 PROCPWRGD
2 3
1 4 H_RCIN# TPAD14-GP TP2210 1 PCH_GPIO22 T5 AY10 PCH_THERMTRIP_R R2204 1 2 390R2J-1-GP
SCLOCK/GPIO22 THRMTRIP# H_THERMTRIP# 5,36,85
SRN10KJ-5-GP TPAD14-GP TP2212 1 PCH_GPIO24 E8 T14 INIT3_3V# 1 TP2201 TPAD14-GP
GPIO24/MEM_LED INIT3_3V#
GPIO27 has a weak[20K] internal pull up. TPAD14-GP TP2203 1 PCH_GPIO27 E16 GPIO27
To enable on-die PLL Voltage regurator,
PLL_ODVR_EN P8
should not place external pull down. GPIO28
TS_VSS1 AH8
PSW_CLR# K1
21 PSW_CLR# STP_PCI#/GPIO34
TPAD14-GP TP2213 PCH_GPIO35 TS_VSS2 AK11 TS Signal Disable Guideline:
1 K4 GPIO35
2
TS_VSS1, TS_VSS2, TS_VSS3 and TS_VSS4
GAP-OPEN
TS_VSS3 AH10
11/11 Remove R2220 for GPIO48 set to GPO DMI_OVRVLTG V8 SATA2GP/GPIO36 should not float on the motherboard. They should
G2201 AK10 TS_VSS 1R2219 2
C FDI_OVRVLTG TS_VSS4 0R0402-PAD be tied to GND directly. C
M5 SATA3GP/GPIO37
P37
1
MFG_MODE NC_1
N2 SLOAD/GPIO38
TPAD14-GP TP2211 1 GFX_CRB_DET M3 SDATAOUT0/GPIO39
3D3V_S0 TPAD14-GP TP2214 1 PCH_GPIO48 V13 BG2
SDATAOUT1/GPIO48 NCTF_VSS#BG2
PCH_TEMP_ALERT# V3 BG48 3D3V_S0
SATA5GP/GPIO49 NCTF_VSS#BG48
PCH_TEMP_ALERT# 1 2 D6 BH3
GPIO57 NCTF_VSS#BH3
1
R2222 10KR2J-3-GP FDI TERMINATION VOLTAGE OVERRIDE
BH47 R2207
MFG_MODE NCTF_VSS#BH47 10KR2J-3-GP
1 2
R2223 10KR2J-3-GP TPAD14-GP TP2206 1 PCH_NCTF_1 A4 BJ4 DY
NCTF_VSS#A4 NCTF_VSS#BJ4
GPIO37 LOW - Tx, Rx terminated to same voltage
2
RN2201 A44 BJ44 FDI_OVRVLTG (FDI_OVRVLTG) (DC Coupling Model DEFAULT)
A4,A44,A45,A46,A5,A6,B3,B47,BD1,BD49,BE1,BE49,BF1,BF49
DGPU_HPD_INTR# NCTF_VSS#A44 NCTF_VSS#BJ44
1 8
1
EC_SCI# 2 7 A45 BJ45
BG2,BG48,BH3,BH47,BJ4,BJ44,BJ45,BJ46,BJ5,BJ6,C2,C48
EC_SMI# 3 6 R2208
NCTF
4 5 A46 BJ46 10KR2J-3-GP
NCTF TEST PIN:

SRN10KJ-6-GP A5 BJ5
2
11/11Remove DBC_EN
X01-0211 swap DGPU_HPD_INTR#, EC_SMI# for layout. A6 NCTF_VSS#A6 NCTF_VSS#BJ6 BJ6 DMI TERMINATION VOLTAGE OVERRIDE
B3 NCTF_VSS#B3 NCTF_VSS#C2 C2
3D3V_S5
B47 C48 3D3V_S0 GPIO36 LOW - Tx, Rx terminated to same voltage
B NCTF_VSS#B47 NCTF_VSS#C48 B
12/1 Add R2224 pull high (DMI_OVRVLTG) (DC Coupling Model DEFAULT)
11/15 Remove Rn2204 BD1 NCTF_VSS#BD1 NCTF_VSS#D1 D1
1
D1,D49,E1,E49,F1,F49
RTC_SENSE# 1 2 BD49 D49 R2209
R2224 10KR2J-3-GP NCTF_VSS#BD49 NCTF_VSS#D49 10KR2J-3-GP
TPAD14-GP TP2207 1 PCH_NCTF_2 BE1 E1 DY Integrated Clock Enable functionality is achieved
PCH_GPIO15 NCTF_VSS#BE1 NCTF_VSS#E1
1 R2201 2
via soft-strap. The default is integrated clock
2
1KR2J-1-GP TPAD14-GP TP2208 PCH_NCTF_3 DMI_OVRVLTG
DY 1 BE49 NCTF_VSS#BE49 NCTF_VSS#E49 E49
enable.
1
BF1 NCTF_VSS#BF1 NCTF_VSS#F1 F1
11/ 17 Dummy R2201 because GPIO15 internal PH R2210
TPAD14-GP TP2209 1 PCH_NCTF_4 BF49 F49 10KR2J-3-GP
NCTF_VSS#BF49 NCTF_VSS#F49
PCH1 Integrated Clock Chip Enable
2
COUGAR-GP-U2-NF
P/N: ND27V ICC_EN# HIGH (R2211 DY)- DISABLED [DEFAULT]
LOW (R2211)- ENABLED

ICC_EN#1 R2211 2
1KR2J-1-GP GPIO8 has a weak[20K] internal pull up.
Integrated Clock Enable functionality is achieved
via soft-strap. The default is integrated clock
enable.
A <Core Design> A
PLL ON DIE VR ENABLE
NOTE:This signal has a weak internal pull-up 20K

ENABLED -- HIGH (R2212 UNSTUFFED) DEFAULT
Wistron Corporation
DISABLED -- LOW (R2212 STUFFED) Taipei Hsien 221, Taiwan, R.O.C.
Title
PLL_ODVR_EN DY 1 R2212 2 PCH (GPIO/CPU)

1KR2J-1-GP Size Document Number Rev
A3
5 4 3 2 1
5 4 3 2 1
11/ 17 Add R2301 but dummy it

SSID = PCH 6A and change L2301 source to 3D3V_DAC_S0 3D3V_S0 3D3V_DAC_S0
2
DY R2301
1D05V_VTT
PCH1G POWER 7 OF 10 (0.1uF/0.01uF x1)
0R2J-2-GP
1.3A(Total current of VCCCORE) 0.001A (10uF x1_0603)
1
Cougar L2301
AA23 U48 +VCCA_DAC_1_2 1 2
AC23
VCCCORE Point VCCADAC HCB1608KF-181-GP
SC10U6D3V3MX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
D D
VCCCORE
1
CRT
(1uFx3)
C2301
C2304
AD21 C2313 C2314 C2315 68.00214.051
VCCCORE
1
(10uFx1_0603)
C2302
C2303
AD23 U47 2nd = 68.00206.041
SC10U6D3V3MX-GP
SCD1U10V2KX-5GP
SCD01U16V2KX-3GP
VCCCORE VSSADAC
VCC CORE
AF21 3rd = 68.00335.081
2
VCCCORE
AF23
2
VCCCORE 3D3V_S0
AG21 VCCCORE 0.001A
AG23 VCCCORE
AG24 AK36 +3VS_VCCA_LVDS 1R2304 2
VCCCORE VCCALVDS 0R0603-PAD
AG26 VCCCORE
AG27 VCCCORE VSSALVDS AK37
AG29 VCCCORE
AJ23
LVDS
VCCCORE 1D8V_S0
AJ26 VCCCORE VCCTX_LVDS AM37 0.06A
AJ27 VCCCORE
11/18 change capacity to 0603 package AJ29 VCCCORE VCCTX_LVDS AM38 +1.8VS_VCCTX_LVDS 1R2305 2
AJ31 0R0805-PAD
SCD01U16V2KX-3GP
SCD01U16V2KX-3GP
VCCCORE
(0.01uF x2)
C2316
C2317
AP36 C2318
VCCTX_LVDS
1
1D05V_VTT (22uF x1)
SC10U6D3V3MX-GP
VCCTX_LVDS AP37 11/2 change
AN19
R2304, R2305 to 0ohm
2
VCCIO
1D05V_VTT
TPAD14-GP TP2301 1 VCCAPLLEXP BJ22 VCCAPLLEXP X02-0303
(10uF x1)
change 0R to short pad
2.925A(Total current of VCCIO) V33
HVCMOS
VCC3_3
AN16 VCCIO 3D3V_S0
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
(1uF x4) (0.1uFx1)
C2305
C2306
C2309
AN17 0.266A
SC4D7U6D3V3KX-GP
VCCIO
1
1
C2307
C2308
VCC3_3 V34
C C
DY
1
AN21 11/18 change capacity to 0603 package
2
2
VCCIO C2319
AN26 SCD1U10V2KX-5GP 1D5V_S0
2
VCCIO
0.16A
AN27 VCCIO VCCVRM AT16
1D05V_VTT
AP21 VCCIO 0.042A
12/28 Yellow mark for OPI change X02-0303
AP23 AT20 +1.05VS_VCC_DMI 1R2306 2
VCCIO VCCDMI 0R0402-PAD (1uF x1) change 0R to short pad
DMI
1
AP24
VCCIO
VCCIO C2320
AP26 AB36 SC1U6D3V2KX-GP
2
VCCIO VCCCLKDMI
Refer to NPCE795 shared SPI flash architecture
1D05V_VTT
AT24 VCCIO 0.02A
+1.05VS_VCC_DMI_CCI 1R2307 2
0.266A (Totally VCC3_3 current) AN33 0R0402-PAD
VCCIO
1
(1uFx1)
3D3V_S0 AN34 AG16 C2321 (10uFx1)
VCCIO VccDFTERM SC1U6D3V2KX-GP
2
NAND / SPI
(0.1uF x1) BH29 VCC3_3 VccDFTERM AG17
1
C2310
0.159A(Totally current of VCCVRM) SCD1U10V2KX-5GP AJ16
2
VccDFTERM 1D8V_S0
B 1D5V_S0 AP16 VCCVRM 0.19A B

VccDFTERM AJ17
VCCVRM(Internal PLL and VRMs):
1
TPAD14-GP TP2302 1 VCCFDIPLL BG6 VCCAFDIPLL
C2322 (0.1uFx1)
A.1.5V for Mobile SCD1U10V2KX-5GP
B.1.8 V for Desktop
2
1D05V_VTT AP17 VCCIO
FDI
PCH1 VCCSPI V1
3D3V_S5
+1.05VS_VCC_DMI AU20 0.02A
VCCDMI
0.042A (Totally current of VCCDMI)
1
COUGAR-GP-U2-NF (1uFx1)
C2323
P/N: ND27V SC1U6D3V2KX-GP
11/3 Add LDO for CRT DAC

power 11/ 17change U2301 Vout power rail and stuff the circuit
3D3V_DAC_S0
5V_S0 U2301
A 1 VIN VOUT 5 <Core Design> A

2 GND
1
C2311 3 4 C2312
EN NC#4
Wistron Corporation
SC1U10V2KX-1GP
SC1U6D3V2KX-GP
1
2
G9091-330T11U-GP 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

74.09091.J3F Taipei Hsien 221, Taiwan, R.O.C.
2nd = 74.09198.G7F 2
Title
PCH (POWER1)
A3
5 4 3 2 1
5 4 3 2 1
SSID = PCH
PCH1J POWER 10 OF 10 1D05V_VTT
TPAD14-GP TP2401 VCCACLK

1 AD49 VCCACLK Cougar VCCIO N26
(1uFx1)
SC1U6D3V2KX-GP
1
Point
C2423
0.002A VCCIO P26
3D3V_S5 1 R2403 2 +VCCPDSW T16 VCCDSW3_3
3D3V_S0 0R0603-PAD P28
2
VCCIO
1 DCPSUSBYP V12 T27
TPAD14-GP TP2405 DCPSUSBYP VCCIO 3D3V_S5 5V_S5
(10uFx1)
D (1uFx1) VCCIO T29 D
+V3.3S_VCC_CLKF33 T38 3D3V_S5
VCC3_3
2
L2401 0.097A (Totally current of VCCSUS3_3)
1 2+V3.3S_VCC_CLKF33 VCCSUS3_3 T23 D2401
IND-10UH-218-GP TPAD14-GP TP2404 1 +VCCAPLL_CPY_PCH BH23 VCCAPLLDMI2
(0.1uFx1) CH751H-40PT-GP
1
C2401
C2402
68.10050.10Y T24 C2424 2nd = 83.R2004.B8F 83.R0304.A8F
SC1U10V2KX-1GP
SC10U6D3V3MX-GP
VCCSUS3_3
2nd = 68.10090.10B 1D05V_VTT (10uFx1) AL29 SCD1U10V2KX-5GP R2408
1
VCCIO
V23 1 2
USB
2
2
VCCSUS3_3
TPAD14-GP TP2402 1 +VCCSUS1 AL24 V24 3D3V_S5 10R2J-2-GP (0.1uFx1)
DCPSUS VCCSUS3_3
1
P24 C2426
VCCSUS3_3
(0.1uFx1) SCD1U10V2KX-5GP
2
1
AA19 VCCASW
T26 1D05V_VTT C2425
VCCIO SCD1U10V2KX-5GP
AA21
2
VCCASW
+5VA_PCH_VCC5REFSUS
0.001A
AA24 VCCASW V5REF_SUS M26
11/18 change capacity to 0603 package 3D3V_S0 5V_S0
Clock and Miscellaneous

AA26 VCCASW
AN23 +VCCA_USBSUS 1 TP2403 TPAD14-GP
1D05V_VTT DCPSUS
AA27 VCCASW
2
1.01A (Total current of VCCASW) VCCSUS3_3 AN24 3D3V_S5
AA29 VCCASW DYC2437
SC1U10V2KX-1GP
D2402
CH751H-40PT-GP
SC10U6D3V3MX-GP
SC4D7U6D3V3KX-GP
2
(22uFx2_0603)
C2403
C2404
AA31 2nd = 83.R2004.B8F 83.R0304.A8F
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
VCCASW
1
1
(1uFx3)
C2406
C2407
C2408
0.001A R2407
1
DY AC26 P34 +5VS_PCH_VCC5REF 1 2
VCCASW V5REF
(1uFx1)
2
2
C AC27 10R2J-2-GP C
VCCASW
1
N20 3D3V_S5
VCCSUS3_3
PCI/GPIO/LPC
AC29 C2427
VCCASW SC1U10V2KX-1GP
N22
2
VCCSUS3_3
AC31 VCCASW
(1uFx1)
1
VCCSUS3_3 P20
1D05V_VTT (1uFx1) C2428
0.08A AD29 VCCASW
(220uFx1) P22 SC1U6D3V2KX-GP
2
VCCSUS3_3
L2402 12/28 Yellow mark for OPI change AD31 VCCASW
1 2 +1.05VS_VCCA_A_DPL
IND-10UH-218-GP W21 AA16 3D3V_S0
VCCASW VCC3_3
1
68.10050.10Y C2443 C2409

2nd = 68.10090.10B SC10U6D3V3MX-GP SC1U6D3V2KX-GP W23 W16
VCCASW VCC3_3
DY (0.1uFx2)
2
1
W24 VCCASW VCC3_3 T34
0.08A C2430 C2431
(1uFx1) W26 SCD1U10V2KX-5GP SCD1U10V2KX-5GP
2
VCCASW
L2403 (220uFx1)
1 2 +1.05VS_VCCA_B_DPL W29 3D3V_S0
IND-10UH-218-GP VCCASW
1
68.10050.10Y C2444 C2410 W31 AJ2

VCCASW VCC3_3
2nd = 68.10090.10B SC10U6D3V3MX-GP SC1U6D3V2KX-GP (0.1uFx1)
1
DY W33
2
VCCASW C2429
VCCIO AF13
SCD1U10V2KX-5GP
2
+VCCRTCEXT N16 DCPRTC 1D05V_VTT
0.16A (Totally current of VCCVRM VCCIO AH13
1
B
C2411 (0.1uFx1) 1D5V_S0 Y49 VCCVRM VCCIO AH14
B
SCD1U10V2KX-5GP (1uFx1)
2
1
AF14 C2432
+1.05VS_VCCA_A_DPL VCCIO SC1U6D3V2KX-GP
BD47
SATA
2
VCCADPLLA 1D05V_VTT
VCCAPLLSATA AK1
+1.05VS_VCCA_B_DPL BF47 R2411
VCCADPLLB
11/ 17 Change R2406 from close gap to 0ohm +V1.05S_VCCAPLL_SATA3 1
DY 2
VCCVRM AF11 1D5V_S0 (10uFx1)
1
1D05V_VTT 1D05V_VTT +VCCDIFFCLKN +VCCDIFFCLK 0R3J-0-U-GP
0.055A (1uFx1)
AF17
AF33
VCCIO DY C2434
VCCDIFFCLKN
2 R2404 1 +VCCDIFFCLK 1 R2406 2 AF34 AC16 SC10U6D3V5KX-1GP
2
VCCDIFFCLKN VCCIO
0R0402-PAD (1uFx1) 0R0402-PAD AG34 VCCDIFFCLKN
1
1D05V_VTT
C2412 C2414
0.095A VCCIO AC17
SC1U6D3V2KX-GP SC1U6D3V2KX-GP +V1.05S_SSCVCC AG33 AD17

2
SCD1U10V2KX-5GP(1uFx1) VCCSSC VCCIO

(1uFx1)
SC1U6D3V2KX-GP
1
C2435
C2415
1D05V_VTT (0.1uFx1) 2 1 +VCCSST V16 DCPSST 1D05V_VTT
2
2 R2405 1 +V1.05S_SSCVCC
0R0402-PAD T17 T21
DCPSUS VCCASW
1
(1uFx1) TPAD14-GP TP2406 1 DCPSUS V19 DCPSUS

MISC
C2413 +3VS_+1.5VS_HDA_IO
SC1U6D3V2KX-GP 1D05V_VTT V21
2
VCCASW
0.001A 2 R2409 1
CPU
3D3V_S5
BJ8 0R0402-PAD
V_PROC_IO +3VS_+1.5VS_HDA_IO
X02-0303 change 0R to short pad (0.1uFx2) T19
SCD1U10V2KX-5GP SC1U6D3V2KX-GP
VCCASW
1
(4.7uFx1_0603) 11/ 17 Change R2409 from close gap to 0ohm

C2418
C2417
PCH1
A <Core Design> A
SC4D7U6D3V3KX-GP 0.01A
2
RTC
A22 P32
HDA
RTC_AUX_S5 VCCRTC VCCSUSHDA

(0.1uFx1)
Wistron Corporation
1
6uA COUGAR-GP-U2-NF C2433 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
SCD1U10V2KX-5GP Taipei Hsien 221, Taiwan, R.O.C.
P/N: ND27V
SCD1U10V2KX-5GP
(0.1uFx2) 2
C2421
C2422
1
(1uFx1) Title
PCH (POWER2)
2

A3
5 4 3 2 1
5 4 3 2 1
SSID = PCH PCH1I 9 OF 10
AY4
AY42
VSS Cougar VSS H46
K18
VSS VSS
AY46 VSS Point VSS K26
AY8 VSS VSS K39
B11 VSS VSS K46
B15 VSS VSS K7
B19 VSS VSS L18
B23 VSS VSS L2
B27 VSS VSS L20
D B31 VSS VSS L26 D
PCH1H 8 OF 10 B35 L28
VSS VSS
H5 VSS B39 VSS VSS L36
AA17
Cougar AK38
B7
F45
VSS VSS L48
M12
VSS VSS VSS VSS
AA2 VSS Point VSS AK4 BB12 VSS VSS P16
AA3 VSS VSS AK42 BB16 VSS VSS M18
AB11 VSS VSS AL16 BB24 VSS VSS M30
AB7 VSS VSS AL26 BC14 VSS VSS M46
AC19 VSS VSS AL27 BC18 VSS VSS M8
AC2 VSS VSS AL31 BC2 VSS VSS N18
AC21 VSS VSS AL33 BC22 VSS VSS P30
AC24 VSS VSS AL34 BC26 VSS VSS N47
AC33 VSS VSS AL48 BC32 VSS VSS P11
AC34 VSS VSS AM11 BC34 VSS VSS P18
AC48 VSS VSS AM14 BC36 VSS VSS T33
AD10 VSS VSS AM36 BC40 VSS VSS P40
AD13 VSS VSS AM45 BD46 VSS VSS P7
AD19 VSS VSS AM46 BD5 VSS VSS R2
AD24 VSS VSS AM7 BE22 VSS VSS R48
C AD26 AN2 BE26 T12 C
VSS VSS VSS VSS
AD27 VSS VSS AN29 BE40 VSS VSS T31
AD33 VSS VSS AN3 BF10 VSS VSS T37
AD34 VSS VSS AN31 BF12 VSS VSS T4
AD36 VSS VSS AP12 BF16 VSS VSS W34
AD37 VSS VSS AP19 BF20 VSS VSS T46
AD4 VSS VSS AP32 BF26 VSS VSS V11
AD42 VSS VSS AP4 BD3 VSS VSS V26
AD8 VSS VSS AR2 BF8 VSS VSS V36
AE2 VSS VSS AR48 BG17 VSS VSS V39
AE3 VSS VSS AT11 BG21 VSS VSS V43
AF10 VSS VSS AT13 BG33 VSS VSS V7
AF12 VSS VSS AT18 BG44 VSS VSS W17
AD14 VSS VSS AT22 BG8 VSS VSS W19
AD16 VSS VSS AT26 BH11 VSS VSS W2
AF16 VSS VSS AT28 BH15 VSS VSS W27
AF19 VSS VSS AT30 BH17 VSS VSS W48
AF24 VSS VSS AT32 BH19 VSS VSS Y12
AF26 VSS VSS AT34 H10 VSS VSS Y38
B B
AF4 VSS VSS AU24 BH39 VSS VSS BG29
AF42 VSS VSS AU30 BH43 VSS VSS N24
AF46 VSS VSS AV16 BH7 VSS VSS AJ3
AF5 VSS VSS AV20 D3 VSS VSS AD47
AF7 VSS VSS AV24 D12 VSS VSS B43
AF8 VSS VSS AV30 D16 VSS VSS BE10
AG19 VSS VSS AV38 D18 VSS VSS BG41
AG2 VSS VSS AV4 D22 VSS VSS G14
AG31 VSS VSS AV43 D24 VSS VSS H16
AG48 VSS VSS AV8 D26 VSS VSS T36
AH11 VSS VSS AW14 D30 VSS VSS BG22
AH3 VSS VSS AW18 D32 VSS VSS BG24
AH36 VSS VSS AW2 D34 VSS VSS C22
AH39 VSS VSS AW22 D38 VSS VSS AP13
AH40 VSS VSS AW26 D42 VSS VSS M14
AH42 VSS PCH1 VSS AW28 D8 VSS VSS AP3
AH46 VSS VSS AW32 E18 VSS VSS AP1
AH7 VSS VSS AW34 E26 VSS VSS BE16
AJ19 VSS VSS AW36 G18 VSS VSS BC16
AJ21 VSS VSS AW40 G20 VSS VSS BG28
AJ24 VSS VSS AW48 G26 VSS VSS BJ28
AJ33 VSS VSS AV11 G28 VSS
AJ34 VSS VSS AY12 G36 VSS
AK12 VSS VSS AY22 G48 VSS
AK3 VSS VSS AY28 H12 VSS PCH1
H18 VSS
COUGAR-GP-U2-NF H22 VSS
P/N: ND27V H24
H26
VSS
A VSS DN15ATI Whistler A
H30 VSS
H32 VSS
H34
F3
VSS
VSS
Wistron Corporation
COUGAR-GP-U2-NF Title
P/N: ND27V PCH (VSS)
A3
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
Wistron Corporation
Title
Reserved
A3
5 4 3 2 1
11/17 change R2724 to meet X00 PCB ver
5 X01-0210 change R2724 to meet X01 PCB ver
X02-0314 change R2724 to meet X02 PCB ver
4 3D3V_AUX_KBC 3
PCB VERSION A/D(PIN98) PULL-LOW RESISTOR PULL-HIGH RESISTOR VOLTAGE
2 3D3V_AUX_KBC
MODEL_ID_DET(GPIO07) PULL-LOW RESISTOR
1 PULL-HIGH RESISTOR VOLTAGE
SSID = KBC Reserved 0.1uF on all of ADC input pins X00 100.0K 10.0K 3.0V Reserved 100.0K 10.0K(64.10025.6DL) 3.0V
1
11/ 17 change R2702 from close gap to 0ohm base on NUVOTON feedback list.(C2717~C2721) R2724 X01 100.0K 20.0K 2.75V R2710 Reserved 100.0K 20.0K(64.20025.6DL) 2.75V
3D3V_AUX_KBC 47KR2F-GP
X02-0303 change 0R to short pad A00-0413 change R2724 to 47K for PCB ver MODELID 47KR2F-GP
X02 100.0K 33.0K 2.48V DV15_UMA with HDMI 100.0K 33.0K 2.48V
1R2702 2 VBAT 3D3V_S0
2
0R0603-PAD A00 100.0K 47.0K 2.24V DV15_UMA without HDMI 100.0K 47.0K(64.47025.6DL) 2.24V
SC2D2U10V3KX-1GP
2
PCB_VER_AD
C2703
SCD1U10V2KX-5GP
1
MODEL_ID_DET DV14_UMA with HDMI
C2702
R2771 Reserved 100.0K 64.9K 2.0V 100.0K 64.9K(64.64925.6DL) 2.0V
SC2D2U10V3KX-1GP
SCD1U10V2KX-5GP
SCD1U16V2KX-3GP
1
1
2D2R3-1-U-GP
DY
SCD1U10V2KX-5GP
100KR2F-L1-GP
1
1
R2726 Reserved 100.0K 76.8 1.87V DV14_UMA without HDMI 100.0K 76.8K(64.76825.6DL) 1.87V
2
3D3V_AUX_KBC_VCC
C2717
100KR2F-L1-GP
1
2
SCD1U10V2KX-5GP
DV14_DIS(512M) with HDMI
C2718
R2739
DY Reserved 100.0K 100.0K 1.65V 100.0K 100.0K(64.10035.6DL) 1.65V
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SC2D2U10V3KX-1GP
2
C2701
C2704
C2705
C2706
C2707
C2708
A00-0328
2
1
1
DV14_DIS(512M) without HDMI
C2709
C2710
Reserved 100.0K 143.0K 1.358V 100.0K 143.0K(64.14335.L0L) 1.358V
change R2735 to 10R
2
DY DY
and C2711 to 220p Reserved 100.0K 174.0K 1.204V DV14_DIS(1G) with HDMI 100.0K 174.0K(74.17435.6DL) 1.204V
2
115
102
D EC_AGND
D
19
46
76
88
4
U2701A 1 OF 2 1 C2711
2 Reserved 100.0K 215.0K 1.048V EC_AGND DV14_DIS(1G) without HDMI 100.0K 215.0K(64.21535.6DL) 1.048V
SC220P50V2KX-3GP
VCC
VCC
VCC
VCC
VCC
AVCC
VDD
40 AD_IA EC_AGND
104 7 PLT_RST#_EC 1R2735 2 11/2 Add MODEL_ID_DET pin
C2714 1 2 SCD1U10V2KX-5GP
VREF LRESET#
2 10R2J-2-GP
PLT_RST# 5,18,31,65,71,83 NOTES:
EC_AGND
PCB_VER_AD
97
GPIO90/AD0
LCLK
LFRAME#
3
LPC_AD3
CLK_PCI_KBC 18
LPC_FRAME# 21,71 The NPCE795P GPIO/PWM outputs that are connected for Vostro & Inspron select Notes:
98 1
GPIO91/AD1 LAD3
11/16 Add R2728 R2729 38
28
PSID_EC
CPU_THRM
99
100
GPIO92/AD2 LAD2
128
127
LPC_AD2
LPC_AD1
LPC_AD[0..3] 21,71 to LEDs have high drive buffers (20mA) and can be The total SPI interface signal between EC and PCH
for SERIES_ID GPIO93/AD3 LAD1
126 LPC_AD0 connected directly to the LEDs.
28 FAN1_DAC
101
GPIO94/DA0
LAD0
SERIRQ
125 INT_SERIRQ 21 canˇt not exceed 6500mil. The mismatch between
49 LCD_TST 105 8 PM_CLKRUN# 19
GPIO95/DA1 GPIO11/CLKRUN#
3D3V_AUX_KBC SERIES_ID 106
GPIO96/DA2 GPIO65/SMI#
9
29
PANEL_BLEN
ECSCI#_KBC
11/19 add TP2701 for KBC_GPIO10 SPI signal must be within 500mil
ECSCI#/GPIO54 KBC_GPIO10 TP2701 TPAD14-GP
124 1
GPIO10/LPCPD# ECSWI#_KBC
19 SUS_PWR_ACK 79 123
1
GPIO2 GPIO67/PWUREQ#
95 121 H_A20GATE 22
R2728 VGA_THRM GPIO3 GPIO85/GA20 U2701B 2 OF 2
28 VGA_THRM 96 122 H_RCIN# 22 KCOL[0..16] 69
100KR2J-1-GP GPIO4 KBRST#/GPIO86
Ins 28 SYS_THRM 108
GPIO5
PSL_IN2 93
GPIO6
Follow DQ15 change PCIE_RST# 28 FAN_TACH1 31
GPIO56/TA1 KBSOUT0/JENK#
53 KCOL0
MODEL_ID_DET 94 27 BLON_OUT 49 to AD_IA_HW2 19 PM_PWRBTN# 117 52 KCOL1
2
GPIO7 GPIO52/PSDAT3/RDY# AD_IA_HW2 GPIO20/TA2 KBSOUT1/TCK KCOL2

68 BATT_WHITE_LED# 114 25 AD_IA_HW2 40 31 PCIE_WAKE# 63 51
SERIES_ID ECSMI#_KBC GPIO16 GPIO50/PSCLK3/TDO GPIO14/TB1 KBSOUT2/TMS KCOL3
6 11 PCH_WAKE# 19 19,36,37,47 PM_SLP_S3# 64 50
CAP_LED# GPIO24 GPIO27/PSDAT2 GPIO01/TB2 KBSOUT3/TDI KCOL4
69 CAP_LED# 109 10 49
1
GPIO30 GPIO26/PSCLK2 KBSOUT4/JEN0# KCOL5

36 S5_ENABLE 14
GPIO34 GPIO35/PSDAT1
71 TPDATA 69 68 CHG_AMBER_LED# 32
GPIO15/A_PWM KBSOUT5/TDO
48 11/16 Add R2776 for aviod kbc code error
KCOL6
R2729
100KR2J-1-GP
15
GPIO36 GPIO37/PSCLK1
72 TPCLK 69 <------ TP 29 KBC_BEEP 118
GPIO21/B_PWM KBSOUT6/RDY#
47
KCOL7
Vostro 39 BAT_IN# 80
GPIO41
62
GPIO13/C_PWM KBSOUT7
43
KCOL8
82 LID_CLOSE# 17 65 42
GPIO42/TCK GPIO32/D_PWM KBSOUT8 KCOL9 3D3V_AUX_KBC
19 RSMRST#_KBC 20 70 <------ BATTERY / CHARGER 40 AD_IA_HW 81 41
2
GPIO43/TMS GPIO17/SCL1 BAT_SCL 39,40 GPIO66/G_PWM KBSOUT9/SDP_VIS# KCOL10

19,46 PM_SLP_S4# 21 69 BAT_SDA 39,40 66 40
GPIO44/TDI GPIO22/SDA1 GPIO33/H_PWM KBSOUT10/P80_CLK KCOL11
21 ME_UNLOCK 23
26
GPIO46/TRST# GPIO73/SCL2
67
68
SML1_CLK 20,85 <------PCH / eDP 68 KBC_WLAN_OUT# 22
16
GPIO45/E_PWM KBSOUT11/P80_DAT
39
38 KCOL12 R2776
38 RCID GPIO51 GPIO74/SDA2 SML1_DATA 20,85 68 PWRLED# GPIO40/F_PWM KBSOUT12/GPIO64
PSL_IN1 73 119 37 KCOL13 PCIE_WAKE# 2 1
GPIO70 GPIO23/SCL3 PM_LAN_ENABLE 31 KBSOUT13/GPIO63
PSL_OUT 74 120 EC_ENABLE#_1 36 KCOL14 DY
EC_GPIO72 GPIO71 GPIO31/SDA3 PROCHOT_EC ECRST# KBSOUT14/GPIO62 KCOL15 100KR2J-1-GP
75 24 85 35
GPIO72 GPIO47/SCL4 VCC_POR# KBSOUT15/GPIO61/XOR_OUT KCOL16
65 WIFI_RF_EN 82
GPIO75 GPIO53/SDA4
28
LCD_TST_EN 49 11/22 change WLAN LED control to KBC GPIO60/KBSOUT16
34
65 BLUETOOTH_EN 83 33
GPO76/SHBM GPIO57/KBSOUT17
19,36 S0_PWR_GOOD 84 65 E51_RxD 113 KROW[0..7] 69
GPIO77 GPIO87/SIN_CR KROW0
91
GPIO81 X02-0309 change 0R to short pad 65 E51_TxD 111
GPO83/SOUT_CR/TRIST# KBSIN0
54
110 55 KROW1
C 61 USB_PWR_EN#
19 AC_PRESENT
36,42 IMVP_PWRGD
112
107
GPO82/TEST#
GPO84/XORTR#
GPIO97
F_CS0#
F_SCK
90
92
EC_SPI_CS#_C
EC_SPI_CLK_C
2 R2736
2 R2719
1 33R2J-2-GP
1 33R2J-2-GP
SPI_CS0#_R 21,60
SPI_CLK_R 21,60
29 AMP_MUTE#
19 PCH_SUSCLK_KBC
30
77
GPIO55/CLKOUT
GPIO00/EXTCLK
KBSIN1
KBSIN2
KBSIN3
56
57
KROW2
KROW3 11/ 17 DY D2705 to meet DN13 result
C
11/22 add RTC_AUX_S5 to KBC_GPIO72 86 EC_SPI_DI_C 2 R2737 1 0R0402-PAD 58 KROW4
F_SDI/F_SDIO1 SPI_SO_R 21,60 KBSIN4
87 EC_SPI_DO_C 2 R2722 1 33R2J-2-GP 59 KROW5
SC1U10V3ZY-6GP
KBC_VCORF F_SDIO/F_SDIO0 SPI_SI_R 21,60 PECI KBSIN5 KROW6

X01-0127 Del R2757 to follow 44
VCORF 5,22 H_PECI R2721 1 243R2J-GP 13
PECI KBSIN6
60 D2705
EC_VTT KROW7
C2712
standard 10mw circuit 1D05V_VTT 1 2 12 61 22 EC_SMI# 1 DY

1
R2720 0R0402-PAD VTT KBSIN7

NOTE:
1
AGND EC_SPI_DI_C ECSMI#_KBC
C2716
3
GND
GND
GND
GND
GND
GND
SCD1U10V2KX-5GP
Locate resistors R2736,R2719 and R2722 close
1
NPCE795PA0DX-GP-U
2
to the NPCE795P.
11/1 Add R2777, C2777 for EMI 2
2
NPCE795PA0DX-GP-U R2773 BAS16-6-GP
18
45
78
89
116
5
103
100KR2J-1-GP 83.00016.K11
CLK_PCI_KBC Very close to EC 2ND = 83.00016.F11
2
NOTE: Very close to EC
EC_AGND
R2777 11/ 17 add R2774 pull high for LID_CLOSE#

22R2J-2-GP
Connect GND and AGND planes via either

1
22 EC_SMI# 1 R2760 2ECSMI#_KBC

0R resistor or one point layout connection. 0R0402-PAD
DY 3D3V_S5
1R2711 2 3D3V_AUX_S5
2 CLK_PCI_KBC_EMI
0R0402-PAD
1
12/10 Add R2762 and dummy R2732, Q2702
1
R2774 ECRST#
100KR2J-1-GP EC_AGND R2705
10KR2J-3-GP
EC_GPIO47 High Active
2
Q2701
1
LID_CLOSE# D2701 1 R2762 2 MMBT3906-7F-GP C2715
SC4D7P50V2CN-1GP
E
2
C2777 20 EC_SWI# 1 0R0402-PAD SC1U6D3V2KX-GP

DY DY 28,36 PURE_HW_SHUTDOWN# B
DY
2
3 ECSWI#_KBC Q2702
1
BAS16-6-GP PROCHOT_EC G 84.03906.P11
C
2
H_PROCHOT#_EC
2nd = 84.03906.F11
D 1 2 H_PROCHOT# 5,40,42
1
83.00016.K11 DY R2733 0R0402-PAD

2ND = 83.00016.F11 R2732 S
DY
100KR2J-1-GP
D2704 2N7002K-2-GP
22 EC_SCI# 1 84.2N702.J31
2
DY ECSCI#_KBC
2ND = 84.2N702.031
3
B BAS16-6-GP
B
ROSA Multi GPIO setting 2
83.00016.K11
2ND = 83.00016.F11
VGA_THRM C2719
1 DYSCD1U10V2KX-5GP
2 PSL SOLUTION 10mW SOLUTION EC GPIO standard PH/PL
SYS_THRM SCD1U10V2KX-5GP
C2720
1 DY 2
20 EC_SWI# 1 R2758 2ECSWI#_KBC 11/ 17 DY R2734 and stuff R2756 to keep KBC data
SCD1U10V2KX-5GP 3D3V_AUX_KBC
CPU_THRM C2721
1 DY 2 0R0402-PAD
1 R2759 2ECSCI#_KBC
RTC_AUX_S5 3D3V_AUX_KBC
R2734
VBACKUP
22 EC_SCI# RN2701
0R0402-PAD 1 R2756 2 EC_GPIO72 1 2 EC_GPIO72
0R0402-PAD 0R2J-2-GP BAT_SCL
EC_AGND DY BAT_SDA
3
4
2
1
3D3V_AUX_S5 12/22 swap net for layout SRN4K7J-8-GP
1 2 PANEL_BLEN 3D3V_AUX_S5 RN2703

17 L_BKLT_EN
R2761 0R0402-PAD C2722 40 PWR_CHG_ACOK 1R8909 2 AC_OK 1 R2768 2 PSL_IN1 AC_IN#_KBC 1 R2763 2 PSL_IN1 AC_IN#_KBC 4 1
1
1 2 0R0402-PAD 0R2J-2-GP BAT_IN# 3 2

PSL 10mW
RN2706
SCD1U10V2KX-5GP 0R2J-2-GP
DY R2769
100KR2J-1-GP
PSL_IN1 SRN100KJ-6-GP
S
4 1 X01-0208 dummy R2769

2
KBC_ON#_R 3 2KBC_ON#_GATE G Q2703 RN2705

G
DMP2130L-7-GP S5_ENABLE 8 1
SCD1U10V2KX-5GP
SRN10KJ-5-GP EC_ENABLE#_1 7 2
PSL_IN2
D 2ND = 84.03413.A31
2N7002K-2-GP
PSL_OUT 6 3
1
ECRST#
C2713
5 4
D
DY 84.02130.031 3D3V_AUX_KBC G
10mW SRN10KJ-6-GP
2
D KBC_ON#
BAT54CPT-GP
R2704 DY 12/6 swap net for layout
1 1 2 EC_GPIO72 3D3V_AUX_KBC 1 R2767 2 KBC_ON#_R EC_ENABLE#_1 S
330KR2J-L1-GP 0R2J-2-GP 3D3V_S0
68 KBC_PWRBTN# 3 83.R2003.E81 Q2704
2ND = 83.00054.Q81 PSL_OUT G 84.2N702.J31 FAN_TACH1 1 2
2 Q2706 PSL 2ND = 84.2N702.031
28 FAN_TACH1
R2712 10KR2J-3-GP
G D
A D2702
KBC_ON# D S5_ENABLE S
KBC_ON# 1 R2766
10mW
2 KBC_ON#_R
0R2J-2-GP
E51_RxD 1 R2708 2
A
S Q2705
DY10KR2J-3-GP
2N7002K-2-GP
2N7002K-2-GP 84.2N702.J31 <Core Design>
D2703 84.2N702.J31 2ND = 84.2N702.031
2ND = 84.2N702.031
2
BLUETOOTH_EN 1 R2709 2 Wistron Corporation
10mW 3 10KR2J-3-GP 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
AC_IN# 40 NOTES: DY Taipei Hsien 221, Taiwan, R.O.C.
2ND = 83.00054.Q81
83.R2003.E81
1 Please make sure there's no pull-down resistor on USB_PWR_EN#,AC_PRESENT,E51_TXD. Title
BAT54CPT-GP KBC Nuvoton NPCE795
AC_IN#_KBC A2
5 4 3 2 1
5 4 3 2 1
SSID = Thermal Thermal sensor P2800 Fan controller P2793 5V_S0

U2802
R2802
3D3V_S0 FON#
1 DY 0R2J-2-GP
2 1 FON# GND 8
5V_S0 2 VIN GND 7
FAN_VCC 3 6
VO GND
27 FAN1_DAC 4 VSET GND 5
1
*Layout* 10 mil
1
R2803 C2803 C2804
DY 107KR2F-GP For linear FAN G991P11U-GP
SC4D7U6D3V3KX-GP
74.00991.031
SCD1U10V2KX-5GP
D D
2
2
3D3V_S0
ADJ 87.1 Degree 2nd = 74.02793.A31
1
C2802
1
12/14 dummy R2803, R2804 and C2805 Very close to CPU1 12/15 Remove 3rd source
226KR2F-GP
SCD1U10V2KX-5GP
1
R2804 C2805
2
SCD1U10V2KX-5GP DY DY
2
11/4 Vendor recommand 3D3V_S0
2
1R2813 2
Layout notice : X01-0209 dummy U2805 circuit DY 470KR2J-2-GP
2
Both DXN and DXP routing 10 mil
150R2F-1-GP
R2828
0R2J-2-GP
trace width and 10 mil spacing.
Very Close to CPU1
R2805
DY DY
P2800_DXP U2805
U2801
1
SC2200P50V2KX-2GP
SC470P50V3JN-2GP
1
2ND = 84.03904.P11 ADJ_G709 1 5 G709_VCC

SET VCC
3
84.03904.L06
C2806
C2807
Q2801
5 VCC TDR 4 SYS_THRM 27
THERM_SYS_SHDN#
2 GND DY
DY 1 6 3 1 2T8_G709
DY 0R2J-2-GP 3 4 HYST_PH
24K3R2F-1-GP
DXP TDL CPU_THRM 27 OUT# HYST
PMBS3904-1-GP 7 2 R2810
2
DXN GND
1
8 1 ADJ

2
OTZ ADJ
1
R2812
P2800_DXN G709T1UF-GP C2808
R2808 DY DY SCD1U10V2KX-5GP
NTC-100K-8-GP P2800EB0-GP 86.9
2
THERM_SYS_SHDN#1 2 T8_P2800 74.02800.B71
2
C R2811 0R2J-2-GP C
1.H/W T8 Shutdown
2.System Sensor, Put on palm rest
R(K)= 0.0012*T^2- 0.9308T+ 96.147
FAN1
5
27 FAN_TACH1 1R2807 2 FAN_TACH1_C 3
0R0402-PAD 2
*Layout* 15 mil
FAN_VCC 1
4
CH551H-30PT-GP
SC4D7U6D3V3KX-GP
SC2200P50V2KX-2GP
FOX-CON3-6-GP-U
C2810
AFTP2801 1 FAN_VCC 20.D0210.103
1
C2809
D2802
AFTP2802 1 FAN_TACH1_C DY
AFTP2803 1 GND
2
X02-0309 change AFTP to followDV14 AMD
1
12/13 change P2800 to ver B 83.R5003.C8F
2ND = 83.R5003.H8H
3rd = 83.5R003.08F
3D3V_S0
B B
1
R2809
100KR2J-1-GP
Q2802
2
S THERM_SYS_SHDN#
27,36 PURE_HW_SHUTDOWN# D
VGA Thermal sensor P2800 11/18 remove R2817, R2818, C2816

G 3D3V_S0
1
C2811
and NC U2804 OTZ pin 2N7002K-2-GP
DY
SCD1U10V2KX-5GP
84.2N702.J31
2
P2800_VGA_DXP 2ND = 84.2N702.031
85 P2800_VGA_DXP U2804
Layout notice : DY
EMI/ESD
1
Both DXN and DXP routing 10 mil DY 3D3V_S0_thermal 5 4 VGA_THRM_TDR 1R2816 2 0R2J-2-GP VGA_THRM 27
C2812 VCC TDR VGA_THRM_TDL
trace width and 10 mil spacing. 6 DXP TDL 3 1R2817 2 0R2J-2-GP
SC2200P50V2KX-2GP 7 DY 2 DY
2
DXN GND
1
8 OTZ ADJ 1
85 P2800_VGA_DXN P2800_VGA_DXN R2815 FAN_VCC
100KR2J-1-GP
P2800EB0-GP
DY
74.02800.B71
2
1
A 3D3V_S0 1 2 3D3V_S0_thermal EC2801 <Core Design> A
R2814 0R0402-PAD X02-0311 Add R2816& R2817 to DY
SCD1U16V2KX-3GP
option VGA_THRM
2
1
DY C2814 Wistron Corporation

and DY the circuit
2

SCD1U10V2KX-5GP
Title
Thermal P2800/Fan Controllor P2793

A3
5 4 3 2 1
5 4 3 2 1
AUD_SPK_R+ 5V_S0 +PVDD 5V_S0

SSID = AUDIO AUD_SPK_R-
AUD_SPK_L-
AUD_SPK_R+ 58
AUD_SPK_R- 58
AUD_SPK_L- 58
+AVDD R2903
AUD_SPK_L+ R2902 2 1
SC10U6D3V5KX-1GP
AMP_MUTE# +PVDD AUD_SPK_L+ 58 0R0603-PAD
27 AMP_MUTE# 2 1
+AVDD 0R0603-PAD
SC1U10V2KX-1GP
SC1U10V2KX-1GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
C2905
C2906
C2908
C2909
C2910
2
1
AUD_VREG
R2904
2 1
0R0603-PAD
2
Close to codec AUD_AGND
AUD_DVDDCORE
41
40
39
38
37
36
35
34
33
32
31
D D
U2901 AUD_AGND
1
AUD_AGND
PORTD_-L
PORTD_+L
AVDD2
THERMAL_PAD
EAPD
PVDD
PORTD_+R
PORTD_-R
PVDD
PVSS
VREG/+2_5V
C2901
SC10U6D3V5KX-1GP
2
11/ 17 change R2930 to 0ohm and PUMP_CAPP
part reference change to ER2930
2
CLOSE TO CODEC
C2914
1 30 SC2D2U10V3KX-1GP
1
DVDD_LV CAP+
11/1 Add R2930 for EMI 2 DMIC_CLK/GPIO_1 CAP- 29 PUMP_CAPN
3D3V_S0 3 28 AUD_V_B
HDA_CODEC_SDOUT DMIC_0/GPIO_2 V-
21 HDA_CODEC_SDOUT 4 SDATA_OUT AVSS2 27
ER2930 1 2 0R0402-PAD HDA_CODEC_BITCLK_R 5 26 AUD_HP1_JACK_R R2906 1 2 60D4R2F-GP
21 HDA_CODEC_BITCLK BITCLK PORTB_R AUD_HP1_JACK_R2 82
Close to codec 21 HDA_SDIN0
R2901 1 233R2J-2-GP HDA_CODEC_SDIN0 6 SDATA_IN PORTB_L 25 AUD_HP1_JACK_L R2905 1 2 60D4R2F-GP AUD_HP1_JACK_L2 82
7 DVDD AVSS2 24 AUD_AGND
HDA_CODEC_SYNC 8 71.92H87.A03 23 AUD_EXT_MIC_R C2922 2 1 SC1U10V3KX-3GP MIC_IN_R 82
21 HDA_CODEC_SYNC HDA_CODEC_RST# SYNC PORTA_R AUD_EXT_MIC_L C2921
9 22 2 1 SC1U10V3KX-3GP
SC1U6D3V2KX-GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
21 HDA_CODEC_RST# RESET# PORTA_L MIC_IN_L 82

1
2
C2903
C2904
C2902
AUD_PC_BEEP 10 21 +AVDD
PCBEEP AVDD1
Close to codec
VREFOUT_C
VREFOUT_A
2
PORTC_R
VREFFILT
11/ 17 Del C2925
PORTF_R
SENSE_A
SENSE_B
PORTC_L
PORTF_L
CAP2
AUD_CAP2
92HD87B1A5NDGXTBX8-GP AUD_VREFFLT
11
12
13
14
15
16
17
18
19
20
2 R2911 1 AUD_V_B
C 0R0603-PAD C
AUD_VREFOUT_O
3D3V_S0 AUD_VREG
AUD_VREFOUT_B
SC10U6D3V5MX-3GP
SC10U6D3V5KX-1GP
SC4D7U6D3V3KX-GP
AUD_SENSE_A
AUD_SENSE_B
AUD_PC_BEEP
AUD_VREFFLT
Vendor recommand
SC1U6D3V2KX-GP
C2917
C2918
C2915
C2916
2 R2914 1
AUD_CAP2
1
1
0R0603-PAD
INT_MIC
R2908
R2920
10KR2J-3-GP 1 2 INT_MIC_L_R
2
2K2R2J-2-GP
2
AUD_VREFOUT_B 2 R2917 1
AMP_MUTE# 0R0603-PAD
AUD_AGND AUD_AGND AUD_AGND AUD_AGND
AUD_VREFOUT_B C2924
2 1
Close to codec
INT_MIC_L_R 58,82
HDA_CODEC_BITCLK SC1U10V3KX-3GP AUD_AGND
X02-0314 change 0R to short pad
MIC IN
1
C2923 C2907
SC1U10V2KX-1GP DY SC4D7P50V2CN-1GP
2
120KR2J-L-GP From PCH

R2909 AUD_VREFOUT_B
AUD_PC_BEEP C2912 2 1 SCD1U10V2KX-5GP SB_SPKR_R 1 2 HDA_SPKR 21 Close to Codec
2
1
C2913 1 SCD1U10V2KX-5GP KBC_BEEP_R
AUD_PC_BEEP 2 1
R2910
2
470KR2J-2-GP
KBC_BEEP 27
B B
Trace width>15 mils From EC RN2901
SRN4K7J-8-GP
3
4
82 MIC_IN_R
82 MIC_IN_L
Azalia I/F EMI

HDA_CODEC_SDOUT
11/16 Change C2919 to 0402 package
1
R2912
47R2J-2-GP +AVDD +AVDD
DY R2913
1 2
2
AUD_HP1_JD# 82
1
1
R2915 20KR2F-L-GP R2916
PCH_AZ_CODEC_SDOUT1
2K49R2F-GP 2K49R2F-GP
2
2
A AUD_SENSE_A AUD_SENSE_B <Core Design> A
1
1
R2918
C2919 20KR2F-L-GP Wistron Corporation
SC1KP50V2KX-1GP R2919 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
2
2 1 Taipei Hsien 221, Taiwan, R.O.C.

2
EXT_MIC_JD# 82
1
AUD_AGND 39K2R2F-L-GP Title

DY C2920
SCD1U10V2KX-5GP
AUD_AGND Audio Codec 92HD87B1
Close to Pin13
2

Close to Pin14 A3 A00
Enrico Caruso 14
5 4 3 2 1
5 4 3 2 1
D D
(Blanking)
C C
B B
Wistron Corporation
Title
Reserved
A3
5 4 3 2 1
5 4 3 2 1
3D3V_LAN_S5 X01-0127 change Q3101 base power rail

for leakage issue.
2
LAN CHIP R3101
DY R3102
10KR2J-3-GP
10KR2J-3-GP
1
EVDD10 Q3101_B
11/18 change L3101 to slime type 3D3V_LAN_S5 1 DY 2
1
1R3117 2
0R0603-PAD DY
D C3106 CLK_LAN_REQ#_R 2 3 PCIE_CLK_LAN_REQ# 20 D
1
Q3101
SC1U10V3ZY-6GP PMBS3904-1-GP
60 mils 2 DY 1R3123
2
DVDD10 10KR2J-3-GP
L3101
LANOUP_1.05S 1 2CTRL10A_R 1R3115 2 DVDD10
1
R3108
DY 2
0R2J-2-GP
1
IND-4D7UH-192-GP C3115 0R0603-PAD C3112
1
1
SC4D7U6D3V3KX-GP
C3120 C3113 C3109 C3114 C3117
GIGA C3123 C3116
SCD1U16V2ZY-2GP
GIGA GIGA 11/2 change LAN_REQ# circuit
2
3D3V_LAN_S5
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
DVDD10 to prevent leakage.
2
2
X02-0302 Dummy PCIE_CLK_LAN_REQ# circuit
X5R
For Switch Regulator enable
3D3V_LAN_S5
R3113
LANXOUT
2K49R2F-GP
LANXIN
2
3D3V_LAN_S5 1 2 LAN_RSET
GPO
R3105
40 mils 0R0402-PAD
DVDD10 R3106
48
47
46
45
44
43
42
41
40
39
38
37
1
1
C3118 C3121 C3119 U3101 AVDD33_REG 0R2J-2-GP

49 1 2
AVDD33
AVDD33
AVDD10
CKXTAL2
CKXTAL1
AVDD33
DVDD10
LED0
DVDD33
LED1/EESK
RSET
GPO/SMBALERT
GND
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
DY
2
C AVDD33_REG 1 36 LANOUP_1.05S C
59 LAN_MDI0P MDIP0 REGOUT
59 LAN_MDI0N 2 MDIN0 VDDREG 35
DVDD10 3 34
AVDD10 VDDREG ENSWREG
59 LAN_MDI1P 4 MDIP1 ENSWREG 33
3D3V_LAN_S5 5 32 EEDI/SDA
59 LAN_MDI1N MDIN1 EEDI/SDA
1R3104 2 DVDD10 6 AVDD10 LED3/EEDO 31
0R0603-PAD 7 30 LAN_EECS R3107 1 2 10KR2J-3-GP
C3101 C3111 59 LAN_MDI2P MDIP2 EECS/SCL DVDD10
59 LAN_MDI2N 8 MDIN2 LAN DVDD10 29 DVDD10
1
3D3V_S0
SC4D7U6D3V3KX-GP
DVDD10 9 28 PCIE_WAKE# 27
AVDD10 LANWAKE#
SCD1U16V2ZY-2GP
59 LAN_MDI3P 10 MDIP3 DVDD33 27 3D3V_LAN_S5

3
4
11 26 ISOLATE# 2 1R3110
2
RN3103 59 LAN_MDI3N 3D3V_LAN_S5 MDIN3 ISOLATE# 1KR2J-1-GP

3D3V_LAN_S5 12 AVDD33 PERST# 25
1
X5R SRN10KJ-5-GP
R3109
REFCLK_N
REFCLK_P
SMBDATA
CLKREQ#
SMBCLK
DVDD10
EVDD10
15KR2F-GP
2
1
HSON
HSOP
HSIN
HSIP
GND
2
Q3104_B
X02-0303 change 0R to short pad Q3104
PMBS3904-1-GP RTL8111E-VB-GR-GP LAN_RST#
13
14
15
16
17
18
19
20
21
22
23
24
1
DVDD10
LAN_RST# 3 2 PLT_RST# 5,18,27,65,71,83
1 3D3V_LAN_S5
TPAD14-GP TP3101
1 2 SMBDATA_LAN PCIE_WAKE# 10KR2J-3-GP2 DY 1 R3122
R3130 DY 0R2J-2-GP CLK_LAN_REQ#_R
PCIE_TXP2
B
X02-0311 add circuit to provent leakage. PCIE_TXN2 C3102
B
X02-0314 SWAP net CLK_PCIE_LAN LANXOUT 1 2
CLK_PCIE_LAN#
SC15P50V2JN-2-GP
EVDD10 EVDD10
3D3V_S0 3D3V_LAN_S5
3
PCIE_RXP2_C
1R3119
DY
2 PCIE_RXN2_C X3101
SCD1U10V2KX-5GP
0R3J-0-U-GP XTAL-25MHZ-155-GP
2
C3131
1R3120
DY
2
2
3D3V_S5 0R3J-0-U-GP 82.30020.D41
1
PA102FMG-GP-U C3103
Q3103 main: 84.00102.031 11/29 change X3101 to 82.30020.D41 LANXIN 1 2
2nd: 84.03403.031 X01-0217 change C3102, C3103 to 15pF SC15P50V2JN-2-GP
S D
1
C3105
1
R3121 PCIE_RXP2_C 1 2SCD1U10V2KX-5GP

SCD1U10V2KX-5GP
SCD1U10V2KX-4GP
SCD1U10V2KX-5GP
PCIE_RXP2 20
1
C3130 10KR2J-3-GP C3122 R3116 1 210KR2J-3-GP SMBDATA_LAN PCIE_RXN2_C 1 2 PCIE_RXN2 20

G
SCD1U10V2KX-4GP SC1U6D3V2KX-GP GIGA C3104 SCD1U10V2KX-5GP

2
C3126
GIGA PCIE_TXP2
PCIE_TXP2 20
2
1
C3129
C3128
PCIE_TXN2
PCIE_TXN2 20
2
1 R3118 2 PM_LAN_ENABLE_R
11/19 add R3131 for KBC code test CLK_PCIE_LAN 20
2
2
1
20KR2F-L-GP DY C3125 CLK_PCIE_LAN# 20

LAN_ENABLE_R_C
1R3131 2 SC1U10V2KX-1GP 3D3V_LAN_S5

2
0R2J-2-GP DY
Q3102 A00-0320 R3103 1 GIGA 2 1KR2J-1-GP GPO
Wistron Corporation
G
27 PM_LAN_ENABLE Change R3118 for LOM power sequence 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
D Taipei Hsien 221, Taiwan, R.O.C.
R3114
S 1 2 EEDI/SDA Title
X01-0211 add C3122 for soft-sart
2N7002K-2-GP 10KR2J-3-GP Reserved
A3
5 4 3 2 1
5 4 3 2 1
SSID = SDIO
XD_D7 1
TP3204 TPAD14-GP
XD_D6/MS_BS XD_D6/MS_BS 74
XD_D5/SD_D2/MS_D5 XD_D5/SD_D2/MS_D5 74
20 CLK_PCH_48M
XD_D4/SD_D3/MS_D1 XD_D4/SD_D3/MS_D1 74
D D
XD_D3/SD_D4/MS_D4 1
TP3205 TPAD14-GP
11/ 17 dummy C3204 and C3209 C3209 DY
1 2 RREF
SC100P50V2JN-3GP
R3201
24
23
22
21
20
19
1 2 U3201
6K2R2F-GP
XD_D7
SP14
SP13
SP12
SP11
CLK_IN
3D3V_S0 1 18 XD_D2/SD_CMD
RREF SP10 XD_D2/SD_CMD 74
USB_PN5_R 2 17 CR_GPIO0 1 TP3201 TPAD14-GP
DM GPIO0
43mA USB_PP5_R 3 DP SP9 16 XD_D1/SD_D5/MS_D0 XD_D1/SD_D5/MS_D0 74
4 15 XD_D0/SD_CLK/MS_D2 XD_D0/SD_CLK/MS_D2 74
3V3_IN SP8 XD_WP/SD_D6/MS_D6 1
5 14
SCD1U10V2KX-5GP
SC4D7U6D3V3KX-GP
3D3V_CARD_S0 CARD_3V3 SP7 TP3206 TPAD14-GP

V18 6 13 XD_WE#/SD_CD# XD_WE#/SD_CD# 74
V18 SP6
1
XD_CD#
250mA
C3204
C3203
SP1
SP2
SP3
SP4
SP5
DY 25
2
GND
SC1U6D3V2KX-GP
C3208
RTS5138-GR-GP
7
8
9
10
11
12
1
71.05138.003
2
C C
Close to chip
XD_ALE/SD_D7/MS_D3 XD_ALE/SD_D7/MS_D3 74
3D3V_CARD_S0 Vendor recommand XD_CLE/SD_D0/MS_D7 XD_CLE/SD_D0/MS_D7 74
XD_CE#/SD_D1 XD_CE#/SD_D1 74
XD_RE#/MS_INS# XD_RE#/MS_INS# 74
SCD1U10V2KX-5GP
SC4D7U6D3V3KX-GP
XD_RDY/SD_WP/MS_CLK_R 1R3208 2 XD_RDY/SD_WP/MS_CLK 74

1
1
C3206
C3207
XD_CD# 1 0R2J-2-GP
TP3203 TPAD14-GP
2
11/22 vendor recommand
Close U3201
11/1 Add R3210, C3210 for EMI
B USB_PN5_R B
USB_PN5 18
CLK_PCH_48M
4
3
1
R3210
10R2J-2-GP
DY
TR3201
DLW21HN900SQ2LGP-U
2
68.00201.141
CLK_PCH_48M_R
USB_PP5_R USB_PP5 18
SC10P50V2JN-4GP
1
C3210 DY
X02-0311 stuff TR3201 and change symbol to 68.00201.141
2
A00-0324 change TR6102 to TR3201

A00-0406 remove R3206, R3207 PAD
<Core Design>
A A
Wistron Corporation
Title
Size
Card Reader-RTS5138
Document Number Rev
A3
5 4 3 2 1
A B C D E
4 4
3 3
(Blanking)
2 2
1 DN15ATI Whistler 1
Wistron Corporation
Title
Reserved
A3
A B C D E
5 4 3 2 1
D D
C C
(Blanking)
B B
Wistron Corporation
Title
Reserved
A3
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
Wistron Corporation
Title
Reserved
A3
5 4 3 2 1
5 4 3 2 1
R3622
27,42 IMVP_PWRGD 1 R3614 2 SYS_PWROK 1D05V_VTT 2 1 H_THERMTRIP# 5,22,85
0R0402-PAD
SSID = Reset.Suspend
1
56R2J-4-GP
C3612 DY
E
SCD01U50V2KX-1GP
2
Q3603 1 R3601 2 H_PWRGD_R B DY Q3601
PS_S3CNTRL 5,22 H_CPUPWRGD 1KR2J-1-GP
G DY
1
CHT2222APT-GP
C
20101206 X02: D C3602 DY
SCD1U10V2KX-5GP
Add Q3603 for RTC power sequence. X02-0303 change 0R to short pad
2
D S D
2N7002K-2-GP 12/16 Add Q3603 to meet RTC sequence as DN13

2ND = 83.00016.F11
83.00016.K11
Power Sequence 2
BAS16-6-GP
2 3 PURE_HW_SHUTDOWN# 27,28
19,27 S0_PWR_GOOD 3 DY 41 3V_5V_EN 1

D3601
1
200KR2J-L1-GP
SYS_PWROK 19
1
1 2 S5_ENABLE 27
D3602
R3602
R3603 1KR2J-1-GP
BAS16-6-GP DY
83.00016.K11
2ND = 83.00016.F11
2
ROSA Run Power 15V_S5
AO4468 MAX 9A
Rds(on) = 18.5mOhm
5V_S0
2nd = 84.08882.037
5V_S5 84.04468.037 5V_S0
2
AO4468-GP
C +5V_RUN Comsumption C
R3604 5 4
100KR2J-1-GP 6
D G
3
Peak current 7.73A
D S
7 D S 2
8 1
1
D S
1
U3601
1 R3605 2 5V_RUN_ENABLE C3603
3D3V_AUX_S5 10KR2J-3-GP SC10U10V5ZY-1GP
2
1
C3608
SCD01U50V2KX-1GP
PS_S3CNTRL 37
2
1 R3606 2 PS_S3CNTRL
100KR2J-1-GP
D G S
6
Rds(on) = 18.5mOhm
Q3602 AO4468 MAX 11.6A
2N7002KDW-GP
2nd = 84.08882.037
3D3V_S0
84.2N702.A3F 3D3V_S5 84.04468.037 3D3V_S0
1
2nd = 84.DM601.03F AO4468-GP

+3.3V_RUN Comsumption
S G D 5 D G 4
Peak current 8.14A
6 D S 3
7 D S 2
8 1
1
D S
B 19,27,37,47 PM_SLP_S3# U3602 B
C3604
RUN_ENABLE 15v 1 R3607 2 3.3V_RUN_ENABLE SC10U6D3V5KX-1GP
2
10KR2J-3-GP
1
C3605
SCD01U50V2KX-1GP
2
1D5V_S3 1D5V_S0
1.5V_RUN for VGA Comsumption 1D5V_S0
Peak current 7.39A TPCA8062-H-GP MAX 28A
Rds(on) = 4.1~5.4m OHM MAX Current ? mA
+1.5V_RUN_CPU Comsumption Design Current ? mA
Peak current 3A U3606
8 D S 1 Total= 11.39A
+1.5V_RUN for Mini-Card Comsumption 7 D S 2
6 D S 3
Peak current 1A
1
5 D G 4
C3609
<Core Design>
A POWERPAK-8P-GP SC10U6D3V5KX-1GP A
2
1 R3630 2 1.5V_RUN_ENABLE
10KR2J-3-GP
Wistron Corporation
1
X02-0314 Change U3606 footprint. 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
C3610 Taipei Hsien 221, Taiwan, R.O.C.
SCD01U50V2KX-1GP
2
Title
Power Plane Enable

A3
5 4 3 2 1
5 4 3 2 1
Close to DIMM
Close to CPU S3 Power Reduction Circuit SM_DRAMPWROK
S3 Power Reduction Circuit Processor VREF_DQ Implementation 0D75V_S0 1D5V_S0
R3707
0R2J-2-GP
1 DY 2
1
Q3708
R3703
22R2J-2-GP 2 DY
R3704
220R2J-L2-GP
D S +V_SM_VREF_CNT 9 D
Q3702_D2
2
Q3701_D
M_VREF_DQ_DIMM0 1 2 +V_SM_VREF D
R3708 0R0402-PAD R3705
G 100KR2J-1-GP
D
1
2N7002K-2-GP
D
84.2N702.J31 Q3702
Q3701 2N7002K-2-GP
2ND = 84.2N702.031
RUN_ENABLE
2N7002K-2-GP
DY 84.2N702.J31
84.2N702.J31
2ND = 84.2N702.031
2ND = 84.2N702.031
S
G
S
PS_S3CNTRL
36 PS_S3CNTRL
Close to CPU
2N7002K-2-GP S3 Power Reduction Circuit SM_DRAMPWROK
C G 1D5V_S3 C
36 PS_S3CNTRL
D 0D75V_EN
1
S R3706
1KR2J-1-GP
Q3704 1.05VTT_PWRGD 45,48
84.2N702.J31
2
2ND = 84.2N702.031 R3709
DY1 2
0R2J-2-GP
1 2ND = 84.2N702.031 S3 Power Reduction Circuit
R3710 X02-0303 change 0R to short pad 84.2N702.J31
Q3703 SM_DRAMRST#
0R0402-PAD
5 SM_DRAMRST# S
2
D SM_DRAMRST#_D
1 R3718 2 DDR3_DRAMRST# 14,15
1KR2J-1-GP
1
19,27,36,47 PM_SLP_S3# 1
R3716
DY22R2J-2-GP
2 0D75V_EN 46 G
C3702
SC100P50V2JN-3GP
2
2N7002K-2-GP
1
C3705 DRAMRST_CNTRL_PCH 20
DY SCD1U10V2KX-5GP
2
B B
C3703
Close to CPU 2 1DRAMRST_CNTRL_PCH
S3 Power Reduction Circuit SM_DRAMPWROK SCD047U16V2KX-1-GP
3D3V_S0
3D3V_S0 1D5V_S0
1
R3713
CEKLT V1.0: PCH to 1K,CUP to 200R
1
200R2F-L-GP
R3702
U3701 200R2F-L-GP
DY
2
5,19 PM_DRAM_PWRGD 1 B
5
2
0D75V_EN VCC
2 A
4 VDDPWRGOOD_R 1R3719 2 VDDPWRGOOD 5
Y 910R2F-GP
3 GND
1
74LVC1G08GW-1-GP R3721
39R2J-L-GP
73.01G08.L04 DY
1
2nd = 73.7SZ08.DAH R3720

2
Q3707_D 750R2F-GP
D
A <Core Design> A
DY Q3707
2N7002K-2-GP
R3717
5,19 PM_DRAM_PWRGD 1 DY 2 VDDPWRGOOD_R 84.2N702.J31 Wistron Corporation
0R2J-2-GP 2ND = 84.2N702.031 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
G
Title
over VDDQ * 0.55 ∮

SM_DRAMPWROK must have a maximum of 15ns rise or fall time
200mV and the edge must be monotonic PS_S3CNTRL
Size Document Number
S3 Reduction Circuit
Rev
A3
5 4 3 2 1
5 4 3 2 1
5V_S5
SSID = PWR.Support
DCin CONN
1
PR3801 20100107
1
15KR2J-1-GP
PR3802 DY 3D3V_S5
Change 09/09
2
10KR2J-3-GP PD3802
1
PSID_PROTECT 1 PMBS3904-1-GP BAV99-4-GP 3D3V_S5
3
PQ3802
PR3804
2
2
1
3
1
D PR3803 PSID_DISABLE#_R_C1 D
2PSID_DISABLE#_R
100KR2J-1-GP DY PR3806
10KR2J-3-GP DEL PR4305, PSID_DISABLE# 08/13 2K2R2J-2-GP
G
1
PQ3801
PD3803
2
FDV301N-NL-GP
3
BAV99-5-GP-U
PR3807
D S PS_ID 1 2
D
PSID_EC 27
33R2J-2-GP
PQ3803
27 RCID G
PR3808
2
PR3812 DY
1
DY 2
100KR2J-1-GP
D
33R2J-2-GP
DY S
Modify 0923 2N7002K-2-GP
1
X02-0314 Del short pad PAD1 to prevent system burn.
+DC_IN
When PQ3801 is stuffed, the PR3806 need change to 2.2K 1% resistor
DCIN1
1 8 19,5V This cap should be used
only as last resort for
X01-0217 change PU3801 to 84.04407.G37
C 2 9 C
3 10
EMI suppression.
4 11 PS_ID_R +DC_IN AD+
5 12 PU3801
6 13 1 S D 8
S D
PC3805
PC3802
PC3803
PC3806
7 14 2 7
SC1U25V5KX-1GP
SC10U25V6KX-1GP
SCD01U50V2KX-1GP
SCD01U50V2KX-1GP
SCD01U50V2KX-1GP
1
1
S D
PC3804
PR3810
240KR3-GP
3 6
1
ACES-CONN14G-GP PC3801 G D
PR3809 1 2 0R0603-PAD PS_ID_R2 DY SCD1U50V3KX-GP
4 5
DY DY
2
AO4407AL-GP
2
A00
2
Id= -10A
K
1
PD3801 Qg= -22nC
P6SBMJ27APT-GP PD3804
11/25 Rdson=14~30mohm
DY B240A-13-GP
11/25
A
AFTP3812 PS_ID_R
2
1
2
AFTP3813 1 +DC_IN PQ3805
R2
AFTP3814 1 GND PQ3804 E PR3811
R1
C AD_OFF_L B
DY
R1
47KR3J-L-GP 20100107
AD_OFF_R
40 PWR_CHG_AD_OFF B
DY E
C
1
R2 PDTA124EU-1-GP
PDTC124EU-1-GP
X02-0309 Change AFTP to follow DV14 AMD 12/2 change PD3801 to 83.P6SBM.DAG(CHENMKO)
B B
A <Core Design> A
Wistron Corporation
Title
DCIN Jack
A3
5 4 3 2 1
5 4 3 2 1
SSID = PWR.Support
D D
Batt Connecter
X02-0309 Change AFTP to follow DV14 AMD
BATT1
10
1
BT+
K
2
1
AFTP3901 1BAT_ALERT 3
EC3904 EC3903 PD3902
SCD1U50V3KX-GP SC2200P50V2KX-2GP DY
SMF18AT1G-GP
4
5
2
6
A
11/25 7
merge PR3902~3904 11/18 8
SRN33J-7-GP 9
PBAT_SMBCLK1
27,40 BAT_SCL 4
3
5
6 PBAT_SMBDAT1
11 20.81507.009
27,40 BAT_SDA
2 7 PBAT_PRES1#
27 BAT_IN#
1 8 ALP-CON9-4-GP
1 AFTP3906
PN3901
EC3901 EC3902
12/2
SC10P50V2JN-4GP
SC10P50V2JN-4GP
1
1
DELETE PR3901 11/8 DY DY
C C
2
12/6 swap net for layout
AFTP3902 1 PBAT_PRES1#
AFTP3903 1 PBAT_SMBDAT1
AFTP3904 1 PBAT_SMBCLK1
AFTP3905 1 BT+
11/25
X02-0309 change AFTP to follow DV14 AMD
B For actual location, need to be swap all pin B
Placement: Close to Batt Connector
BAT_SCL
BAT_IN#
BAT_SDA
3
D3902 D3903 D3901

BAV99-5-GP-U BAV99-5-GP-U BAV99-5-GP-U
1
83.00099.T11
2nd = 83.00099.K11
83.00099.T11
2nd = 83.00099.K11
83.00099.T11
2nd = 83.00099.K11
A 3rd = 83.BAV99.D11 3rd = 83.BAV99.D11 3rd = 83.BAV99.D11 <Core Design> A
3D3V_AUX_KBC
Wistron Corporation
Title
BATT CONN
A3
5 4 3 2 1
5 4 3 2 1
SSID = Charger
D
X01-0217 change PU4002, PU4003 to 84.04407.G37 D
AD+_TO_SYS DCBATOUT BT+

PU4003
PU4002 1 S D 8
EE need pull high and net name AD+ 8
7
D
D
S
S
1
2 1 2
19,5v 2
3
S
S
D
D
7
6
1
6 D S 3 PR4002 AD+ 4 G D 5
100KR2J-1-GP
PR4003
5 D G 4 D01R2512F-4-GP
GAP-CLOSE-PWR-3-GP
AO4407AL-GP
0802 Rename H_PROCHOT# AO4407AL-GP
19,5v Id= -10A
2
2
1
10KR2J-3-GP
AD+_G_2
3D3V_AUX_S5 Id= -10A
PG4002
PG4004
PG4005
PG4001
PG4006
PR4004
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
PG4003 PR4005 Qg= -22nC
10KR2F-2-GP
Qg= -22nC GAP-CLOSE-PWR-3-GP 470KR2J-2-GP
Rdson=14~13mohm
PR4001
PR4006
Rdson=14~13mohm
1
1
0R2J-2-GP
2
5,27,42 H_PROCHOT#
DY PR4037 2
DY 1
DC_IN_D
100KR2J-1-GP
1
PQ4005
D
PQ4002
AD+_G_1
2N7002A-7-GP 1 2
2
A00-0412 dummy PR4037 3 4
SC1U25V3KX-1-GP
SC1U25V3KX-1-GP
PC4002
G PWR_CHG_CMPOUT PWR_CHG_ACOK 2 5 SCD1U25V2KX-GP
g PWR_DCBATOUT_CHG
PC4003
PC4004
1 6
SC1U25V3KX-1-GP
PWR_CHG_CMPIN A00-0412 stuff PQ4005AD+
S
SC2200P50V2KX-2GP
2N7002KDW-GP d DY
SCD1U50V3KX-GP
PC4024
SCD1U25V2ZY-1GP
2
PWR_CHG_ACN
1
PWR_CHG_ACP
84.2N702.A3F
PC4009
1
SC10U25V5KX-GP
SC10U25V5KX-GP
SC10U25V5KX-GP
SC10U25V5KX-GP
SC10U25V5KX-GP
EC4001
EC4002
PR4029 2nd = 84.DM601.03F
1
PC4008
PC4006
PC4026
PC4014
PC4025
54K9R2F-L-GP
PWR_CHG_REGN
SCD47U25V3KX-2GP
A00-0412 Change PR4029 to 54.9K PR4008 DY DY
CHG_AGND CHG_AGND DY DY
2
1
20R5J-GP PD4001
PR4029_22
2
5
6
7
8
C PR4007 PR4009 C
1 2 PWR_CHG_VCC SD103AWS-1-GP 11/10
D
D
D
D
AO4496-GP
PU4004
316KR2F-GP CHG_AGND 0R3J-0-U-GP
PC4010
1 2 K A 1 2
SCD047U25V2KX-GP
PC4007
PC4011_1
1 2
2
1
PR4010 20R5J-GP PU4005 SC1U25V3KX-1-GP
11/18
PC4011
ACP
ACN
2
1
PWR_CHG_REGN
G
S
S
S
PWR_CHG_IOUT CHG_AGND 20
D
VCC
1
4
3
2
1
PQ4004 PR4011 PR4030
2
SCD01U50V2KX-1GP
49K9R2F-L-GP PR4031
2N7002K-2-GP 19K1R2F-GP 100KR2J-1-GP PWR_CHG_ACDET 6 17 PWR_CHG_BTST

ACDET BTST
1
Charger Current=1.4~3.6A
1
PC4012
2
PWR_CHG_CMPOUT 16
REGN
2
1
PR4014 3 delete net name 11/10
S
R4013 PR4032 CMPOUT PWR_CHG_HIDRV PL4001

18
49K9R2F-L-GP 120KR2F-L-GP 3D3MR2J-GP HIDRV IND-5D6UH-52-GP BT+
4 1
DY
2
CMPIN PWR_CHG_PHASE
AD_IA_HW 27 A00-0412 Change PR4013 to 49.9K 19 1 2BT+_R 1 2
2
2
PWR_CHG_CMPIN PHASE PC4013 PR4016
SC3300P50V3KX-1GP
SCD1U50V3KX-GP
CHG_AGND delete net name 11/15 D01R2512F-4-GP
SC10U25V5KX-GP
SC10U25V5KX-GP
SC10U25V5KX-GP
SC10U25V5KX-GP
PC4019
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
CHG_AGND 2 1 PWR_CHG_BAT_SCL 9 15 PWR_CHG_LODRV
27,39 BAT_SCL SCL LODRV
PC4015
PC4016
PC4017
PC4018
CHG_AGND PG4007 GAP-CLOSE-PWR-3-GP
1
SCD1U25V2KX-GP
BQ24707ARGRR-GP
5
6
7
8
2
2 1 PWR_CHG_BAT_SDA 8 DY
27,39 BAT_SDA SDA
D
D
D
D
3D3V_AUX_S5
PG4009
PG4010
AO4496-GP
PU4001
PG4008 GAP-CLOSE-PWR-3-GP
PWR_CHG_CMPIN
2
PC4020
A00-0412 stuff PR4030& PR4032 13 PWR_CHG_SRP 1 PR4021 2
1
SRP
1
PWR_CHG_ILIM 10 10R2F-L-GP
ILIM
1
1
PR4017 12 PWR_CHG_SRN 1 PR4020 2
SRN
G
S
S
S
PR4027 100KR2J-1-GP 7D5R2F-GP DY
19K6R2F-GP 2 1 PWR_CHG_IFAULT
11 IFAULT#
DY
4
3
2
1
38 PWR_CHG_AD_OFF
2
PR4018 CHG_AGND
2
B 0R2J-2-GP PR4022 B
1
PWR_CHG_CMPIN_R 0R2J-2-GP
10KR2F-2-GP
3D3V_AUX_S5
SCD1U25V2KX-GP
PR4023 5 7 PWR_CHG_IOUT 1 2
PR4035
ACOK# IOUT AD_IA 27

A00-0412 Change PR4027 to 19.6K 59KR2F-GP PWR_CHG_CSOP_1
GND
GND
DY
SC220P50V2JN-3GP
PWR_CHG_REGN
D
PC4021
X01-0217 change PU4001, PU4004 to 84.04496.037
2
8K45R2F-2-GP
PQ4003 PR4026
DY IC so sanh
1 PR4024
21
14
2N7002K-2-GP PQ4001 100KR2J-1-GP
D
1
2N7002A-7-GP
PC4022
CHG_AGND PG4011
2
1 2
DY
2
G PWR_CHG_CMPOUT CHG_AGND
SCD1U25V2KX-GP
GAP-CLOSE-PWR PWR_CHG_CSON_1
S
CHG_AGND DY
S
2
EE need check pull high
PC4023
Add net name 11/10
1
AD_IA_HW2 27
2
CHG_AGND
CHG_AGND
CHG_AGND
CHG_AGND
ROSA PWR_CHG_REGN 3D3V_AUX_S5
3D3V_AUX_S5 PWR_CHG_REGN
11/29
Adapter Type PR4023
1
11/15
1
PR4025 PR4034
AD+
65W 24K DY 100KR2J-1-GP 100KR2J-1-GP PR4019
100KR2J-1-GP
DYPR4028
100KR2J-1-GP
2
90W 33.2K
2
2
1
27 AC_IN# BOM merge 12/15 27 PWR_CHG_ACOK

SCD1U25V3KX-GP
PR4038
1
PC4001
130W 59K 316KR2F-GP

DY
1
A A
PR4033 PQ4007
EC code only BQ24707
D
DY DY120KR2F-L-GP <Core Design>
2
G PQ4006
2
2N7002K-2-GP
2
H_PROCHOT# AD_IA_HW AD_IA_HW2 D DY DY PR4036

120KR2F-L-GP Wistron Corporation
1
S 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

65W 0 0 PR4039 Taipei Hsien 221, Taiwan, R.O.C.
2
2N7002K-2-GP DY 49K9R2F-L-GP
G
Title
90W 1 0 PR4034 can dummy if you use external 10mW
CHARGER BQ24707
2
X01-0127 DY PQ4007, PR4038, PR4039 AC_IN# Size Document Number Rev

130W 0 1 Custom
for new version BQ24707 Enrico Caruso 14 A00
5 4 3 2 1
A B C D E
SSID = PWR.Plane.Regulator_3p3v5v X01-0217 change PR4103 to 100K(F) 3D3V_PWR_2 PWR_5V3D3V_VLK
1
PC4103 PC4104
SC1KP50V2KX-1GP
PC4102
SCD1U25V3KX-GP SCD1U25V3KX-GP
PR4102
2
100KR2J-1-GP
PC4103_2
PC4104_2
2
11/18 11/18
PWR_3D3V5V_ENTRIP
PWR_5V_ENTRIP1
khoi nang ap
3
PC4105
SC18P50V2JN-1-GP
PQ4101 PR4103
1
2N7002K-2-GP 100KR2F-L1-GP 12/10 EE change for BOM merge PD4101 PD4102
DY BAT54S-5-GP BAT54S-5-GP
4 4
4
DCBATOUT PWR_3D3V_DCBATOUT PQ4102 15V_PWR
1
2N7002KDW-GP 15V_S5 5V_PWR
PG4103 11/18 84.2N702.A3F PG4112
S
2nd = 84.DM601.03F GAP-CLOSE-PWR-3-GP
PC4101_1
1 2
GAP-CLOSE-PWR-3-GP
3
36 3V_5V_EN 1 2 ALW_ON_1 1 2
PG4104 PR4104 10KR2J-3-GP
3D3V_S5
K
3D3V_PWR 1 2 11/18
1
GAP-CLOSE-PWR-3-GP PWR_3D3V_ENTRIP2 PC4106 PC4107
PD4103
1
PG4102 SC1U25V3KX-1-GP SCD1U10V2KX-5GP
BZT52C15S-GP
1
1 2 PG4106 PR4106 DY
SC18P50V2JN-1-GP
2
1
1
GAP-CLOSE-PWR-3-GP 1 2 DY 200KR2J-L1-GP PR4107
GAP-CLOSE-PWR-3-GP 91KR2F-GP PC4101
PC4108
DY
A
PG4105 11/18 SCD1U25V3KX-GP
2
1 2 PG4109
2
GAP-CLOSE-PWR-3-GP 1 2 PWR_5V_DCBATOUT
GAP-CLOSE-PWR-3-GP
TPS51125 RT8205B
11/18
PG4107
1 2 PWR_3D3V_DCBATOUT PR4108 DY ASM
SCD1U50V3KX-GP
PC4112
GAP-CLOSE-PWR-3-GP DCBATOUT PWR_5V_DCBATOUT 5V_PWR 5V_S5
1
SC10U25V5KX-GP
PC4116
SC10U25V5KX-GP
PC4117
SC10U25V5KX-GP
PC4131
SC10U25V5KX-GP
PC4132
PWR_5V_DCBATOUT
PG4108 PR4108 12/13 PG4119
PC4109 PWR_5V3D3V_EN0
1 2 1
DY 2 1 2
2
1
SCD01U50V2KX-1GP
GAP-CLOSE-PWR-3-GP PC4114 PC4115 PG4111 GAP-CLOSE-PWR-3-GP

1
1
SC10U25V5KX-GP
PC4110
SC10U25V5KX-GP
PC4130
SC10U25V5KX-GP
SCD01U50V2KX-1GP
820KR3J-GP 1 2
1
PG4110 TPS51125 RT8205B GAP-CLOSE-PWR-3-GP PG4118
2
4
1 2 PR4110 0R3J 4R7 1 2
2
G1
D1
D1
D1
GAP-CLOSE-PWR-3-GP 12/15 PU4104 PG4114 GAP-CLOSE-PWR-3-GP
2
TPS51125 RT8205B
Q1
FDMS3604S-GP 1 2
8
7
6
5
PG4113 PR4109 0R3J 4R7 GAP-CLOSE-PWR-3-GP PG4101

D
D
D
D
PU4102
PHASE
1 2 1 2
GAP-CLOSE-PWR-3-GP S1/D2 GAP-CLOSE-PWR-3-GP
16
FDMC8884-GP 9 PG4116
Q2 S2
PU4101 1 2
G2
S2
S2
Design Current = 16A GAP-CLOSE-PWR-3-GP PG4120
VIN
PC4113 1 2
0826 25.1A<OCP< 29.3A
5
Design Current = 4.5A SCD1U25V3KX-GP SCD1U25V3KX-GP PG4130 GAP-CLOSE-PWR-3-GP
S
S
S
G
12/15 PR4109
PR4110
PC4118 1 2
7A<OCP< 8.4A
1
2
3
4
2 1 PWR_3D3V_VBST2_1
1 2PWR_3D3V_VBST2 9 22 PWR_5V_VBST11 2 PWR_5V_VBST1_1 1 2 GAP-CLOSE-PWR-3-GP PG4123
3D3V_PWR VBST2 VBST1 0R3J-0-U-GP 5V_PWR
2D2R3J-2-GP 1 2
PL4102 PWR_3D3V_DRH2 10 21 PWR_5V_DRVH1 PG4131 GAP-CLOSE-PWR-3-GP
DRVH2 DRVH1 PL4103
3 1 2 3
2 1 PWR_3D3V_LL2 11 20 PWR_5V_LL1 1 2 GAP-CLOSE-PWR-3-GP PG4124
SCD1U10V2KX-5GP
LL2 LL1 IND-1D5UH-34-GP 1 2

1
COIL-2D2UH-27-GP PWR_3D3V_DRVL2 PWR_5V_DRVL1 GAP-CLOSE-PWR-3-GP

PC4119
12 19 68.1R510.10J PG4132
1
1
PU4103 DRVL2 DRVL1
1 2
8
7
6
5
DY
PT4103
SE330U6D3VM-15-GP
FDMC7696-GP TPS51125ARGER-GP GAP-CLOSE-PWR-3-GP
PC4120
PG4125
DY PR4112
SCD1U10V2KX-4GP
GAP-CLOSE-PWR-3-GP
D
D
D
D
PR4111 PWR_3D3V_VO2 7 24 PWR_5V_VO1 11/10 PT4101 PT4104 1 2

2
1
PG4121 2D2R5F-2-GP VO2 VO1 2D2R5F-2-GP GAP-CLOSE-PWR-3-GP
PG4133
2
1PR4111_2
1
GAP-CLOSE-PWR-3-GP
ST220U6D3VDM-15GP
ST220U6D3VDM-15GP
PWR_3D3V_FB2 5 2 PWR_5V_FB1 PG4122 1 2
1 PR4112_2 2
VFB2 VFB1 GAP-CLOSE-PWR-3-GP PG4126
2
4 1 2
G
11/18
2
2PWR_5V3D3V_EN0 3V_5V_POK 11/18 GAP-CLOSE-PWR-3-GP

S
S
S
1 13 23 PG4134
DY
2
PR4101 820KR2F-GP EN0 PGOOD
1 2
1
2
3
PWR_3D3V_ENTRIP2 6 1 PWR_5V_ENTRIP1 GAP-CLOSE-PWR-3-GP PG4138

51125_VREF ENTRIP2 ENTRIP1
PC4121
DY 12/15 1 2
2
SC330P50V2KX-3GP 3 15 PG4135 GAP-CLOSE-PWR-3-GP

VREF GND
DY PC4122
SC560P50V-GP 1 2
1
SCD22U10V2KX-1GP
PC4123
PWR_5V3V_TONSEL 4 GAP-CLOSE-PWR-3-GP
2
25 PG4139
TONSEL GND
1 2
X02-0310 stuff PC4120 PG4136 GAP-CLOSE-PWR-3-GP
2
1
14 18 PWR_5V3D3V_VLK 1 2
PR4114 SKIPSEL VCLK GAP-CLOSE-PWR-3-GP
PWR_5V3V_SKIPSEL PG4140
PR4113 DY 0R2J-2-GP 1 2
VREG3
VREG5
6K65R2F-GP PG4137 GAP-CLOSE-PWR-3-GP
1 2
2
1 2
1
51125_FB2_R PR4115 GAP-CLOSE-PWR-3-GP PG4141
PC4125 0R2J-2-GP 1 2
3D3V_AUX_S5_5_51125 8
17
3D3V_PWR_2
DYSC18P50V2JN-1-GP 5V_AUX_S5 DY GAP-CLOSE-PWR-3-GP
1
3D3V_PWR_2
PG4127
2
PR4116 PG4142
1 2
1
1 2 33KR2F-GP
PWR_5V_FB1_R 1 2
1
PR4118 PR4119 GAP-CLOSE-PWR-3-GP

PR4117 GAP-CLOSE-PWR-3-GP 100KR2J-1-GP PC4124 DY
51125_VREF 2
DY 1
2
10KR2F-2-GP 0R2J-2-GP SC18P50V2JN-1-GP PG4143
2
1 2
2
3D3V_PWR_2 2 1 GAP-CLOSE-PWR-3-GP
2
PR4121 0R0402-PAD
1
PG4144
51125_VREF 2 1 PR4120 1 2
1
PR4122 0R0402-PAD PC4126 PC4127 21K5R2F-GP GAP-CLOSE-PWR-3-GP

Close to VFB Pin (pin5)
SC4D7U6D3V5KX-3GP
SC10U10V5KX-2GP
2
3D3V_PWR_2 2
DY PR4123
1 Close to VFB Pin (pin2) PG4145 2
2
2
0R2J-2-GP 3D3V_PWR_2 3D3V_AUX_S5 1 2
GAP-CLOSE-PWR-3-GP
2 PR4124
1
DY 0R2J-2-GP 2 PR4125 1 PG4146
0R0402-PAD 1 2
GAP-CLOSE-PWR-3-GP
TPS51125 RT8205B
PR4118 DY ASM
PR4121 ASM DY 12/20 changePC4126 to 78.47520.51L
I/P cap: 10U 25V K0805 X5R/ 78.10622.51L I/P cap:10U 25V K0805 X5R/ 78.10622.51L
Inductor: 2.2U PCMC063T-2R2MN Cyntec 18mohm/20mohm Isat =10Arms 68.2R210.20B Inductor: 1.50UH PCMC104T-1R5 Cyntec 3.8mohm/4.2mohm Isat =33Arms 68.1R510.10J
O/P cap: 330U6.3V M6.3*5.7 15mOhm 3.16Arms Matsuki/77.53371.04L SKIPSEL VREG3 or VREG5 VREF(2V) GND O/P cap: 220U 6.3V PSLV0J227M 25mOhm 2.236Arms NEC_TOKIN/77.C2271.00L
H/S: SIS412DN / 24mohm/30mOhm@4.5Vgs/ 84.00412.037 H/S,L/S: FDMS3604S / 7.5mohm/9.8mOhm@4.5Vgs, 2.6mohm/3.2mOhm@4.5Vgs/ 84.03604.037
Operating OOA Auto Skip Auto Skip
L/S: SI7716ADN / 13.5mohm/16.5mOhm@4.5Vgs/ 84.07716.037 Mode PWM only
EN0 Open 820k  to GND GND

Operating
Mode enable both enable both LDOs, disable all
TPS51125: LDOs, VCLK on VCLK off and circuit
DCBATOUT and ready to ready to turn on
TONSEL CH1 CH2 turn on switcher channels
DCBATOUT GND 200kHz 265kHz switcher
2
channels
Vz=5.1V DY PD4105 VREF 245kHz 305kHz
1
PU4105 MMPZ5231BPT-GP
PR4126 4 3 PWR_5V3D3V_EN0 VREG3 300kHz 375kHz
40K2R2F-GP
DY
1
PU4101_2 VREG5 365kHz 460kHz

1
5 DY 2
1
2
PU4101_5 6 1 0629 Modify

0629 Modify
PR4105
1
2N7002KDW-GP RT8205B:
DY100KR2F-L1-GP
DY PR4127
750KR2F-GP TONSEL CH1 CH2
2
<Core Design>
84.2N702.A3F GND 200kHz 250kHz
2
VREF 300kHz 375kHz Wistron Corporation

VREG3 365kHz 460kHz Taipei Hsien 221, Taiwan, R.O.C.
VREG5 365kHz 460kHz Title
Size
TPS51125_5V/3D3V
Document Number Rev
A2 Enrico Caruso 14 A00
A B C D E
5 4 3 2 1
SSID = CPU.Regulator
3D3V_PWR 5V_S5
1D05V_VTT 3D3V_S0
1
PR4204 PR4205
D 1R2F-GP 1R2F-GP D
1 PR4210
1 PR4208
1 PR4209
1 PR4212
2
2
PC4213
PC4201
SCD1U25V3KX-GP
SCD1U25V3KX-GP
1
1
1D05V_VTT
12/2
Delete PR4212 Pull-up 200 R of ALL_SYS_PWRGD
2
130R2F-1-GP
10KR2F-2-GP
10KR2F-2-GP
54D9R2F-L1-GP
GND_1316 GND_1316 PU4201
1
DYPR4215
100R2F-L1-GP-U
DYPR4216
100R2F-L1-GP-U
PWR_VCORE_VDD5 12 VDD5 DCMDRP1 18
19
PWR_VCORE_DCMDRP1
PWR_VCORE_DCMDRP2
PWR_VCORE_VDD3 DCMDRP2
43 VDD3
PWR_VCORE_VDD3 42 14 PWR_VCORE_SENSE1- PR4217 1 2 0R0402-PAD
VSSSENSE 8
2
VDD3 SENSE1- PWR_VCORE_SENSE1+ PR4218 0R0402-PAD

SENSE1+ 13 1 2 VCCSENSE 8
15 PWR_VCORE_SENSE2- PR4219 1 2 0R0402-PAD
SENSE2- VSS_AXG_SENSE 9
16 PWR_VCORE_SENSE2+ PR4220 1 2 0R0402-PAD
SENSE2+ VCC_AXG_SENSE 9
PWR_VCORE_IMON1 21
PWR_VCORE_IMON2 IMON1 PWR_VCORE_TEMP_SENSE1
25 IMON2 TEMP_SENSE1 29
20101012 TEMP_SENSE_GFX 1PR4254 2 TEMP_SENSE_GFX_R 2H_PROCHOT#
PC4214
PC4231
30 1
SCD022U16V2KX-3GP
SCD022U16V2KX-3GP
TEMP_SENSE2 0R0402-PAD PR4224 100KR2F-L1-GP

43 PWR_VCORE_DB0 37 DB10
1
C 36 40 C
43 PWR_VCORE_DB1 DB11 SPHASE1_0 PWR_VCORE_SPHASE_0 43
1
1
PR4221 PR4222 35 39
7K87R2F-GP 8K87R2F-2-GP 43 PWR_VCORE_DB2 DB12 SPHASE1_1 PWR_VCORE_SPHASE_1 43 PR4255 PR4256
44 DB0_GFX 33 DB20 SPHASE1_2 38
32 34 61K9R2F-GP NTC-220K-2-GP
2
44 DB1_GFX DB21 SPHASE2 SPHASE_GFX 44

31
2
44 DB2_GFX DB22
5 H_CPU_SVIDCLK 8
2
PWR_VCORE_IDES1_N VCLK
43 PWR_VCORE_IDES1_N 24 IDES1_N VDIO 4 H_CPU_SVIDDAT 8
43 PWR_VCORE_IDES1_P
PWR_VCORE_IDES1_P 23 IDES1_P
NTCG104QH224HT
44 IDES_N_GFX 27 IDES2_N VR_ENABLE 6 D85V_PWRGD 48
44 IDES_P_GFX 28 IDES2_P VR_TT# 10 H_PROCHOT# 5,27,40
GND_1316 8
PWR_VCORE_R_OSC VR1_READY PWR_VCORE_VR2_DELAY IMVP_PWRGD 27,36
1 2 41 R_OSC VR2_READY 9
130KR2F-GP PR4225 1 2 PWR_VCORE_R_REF1 22
44K2R2D-GP PR4226 1 PWR_VCORE_R_REF2 R_REF1
2 26 R_REF2 ALERT# 7 VR_SVID_ALERT# 8
44K2R2D-GP PR4229
PR4233
1 2 PWR_VCORE_R_SEL0 2 17
23K7R2F-GP PR4231 PWR_VCORE_R_SEL1 R_SEL0 NC#17
1 2 1 R_SEL1 NC#20 20 1 2PWR_VCORE_TEMP_SENSE1_R
1 2 H_PROCHOT#
1 2 20101012 49K9R2F-L-GP PR4232 1 2 PWR_VCORE_R_SEL2 48 PR4223 100KR2F-L1-GP
PG4203 39K2R2F-L-GP PR4234 PWR_VCORE_R_SEL3 R_SEL2 5K76R2F-2-GP
PC4218
PC4219
1 2 47
SCD047U25V2KX-GP
SCD047U25V2KX-GP
R_SEL3
1
GAP-CLOSE-PWR 32K4R2F-1-GP PR4235 1 2 PWR_VCORE_R_SEL4 46 49 NTCG104QH224HT 12/17 change PR4246 to 475K(1%) as DN13
27K4R2F-GP PR4236 PWR_VCORE_R_SEL5 R_SEL4 GND PR4239
1 2 45 11
43K2R2F-L-GP
R_SEL5 GND
1
20101012 39K2R2F-L-GP PR4237 PWR_VCORE_R_SEL6 NTC-220K-2-GP
PR4238
1 2 44 R_SEL6 GND 3
GND_1316 3K74R2F-GP PR4201
1D05V_VTT 12/2
2
VT1316MAFQX-041-GP 1D05V_VTT 12/2
GND_1316
PWR_VCORE_DB1 DB1_GFX
11/18
B B
GND_1316 20101012
1
PR4243 PR4244 PR4245 PR4246
48K7R3F-1-GP 221KR2F-GP 158KR2F-GP 475KR3F-GP
2
PWR_VCORE_DCMDRP1 PWR_VCORE_DCMDRP2
20101012
1
PR4249 PC4228
1K54R2F-GP SC2200P50V2KX-2GP PR4250 PC4229
2
5K11R2F-L1-GP SC2200P50V2KX-2GP
2
2
2
GND_1316 GND_1316
A <Core Design> A
Wistron Corporation
DELETE 11/8 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Title
VT1316+1314_CPU_CORE(1/3)
A3
5 4 3 2 1
5 4 3 2 1
X01-0217 change PR4202, PR4213, PR4230

PR4247 to 7.5K(F)
PR4203
PR4202
1 2 1 2
20101012
7K5R2F-1-GP
5V_S5 400mils or Copper Shape
9K31R2F-GP
SCD1U10V2KX-4GP
PC4203
PC4208
PC4204
PC4205
PC4209
PC4206
PC4210
PC4207
SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
1 2PWR_VCORE_IDES1_N_2 SC4700P50V2KX-1GP
PC4202 SC1KP50V2KX-1GP
1
PWR_VCORE0_IDES_P_1
D PWR_VCORE0_IDES_N D
2
1
PR4206
3K09R2F-1-GP
G6
G5
G4
C6
C5
C4
E6
E5
E4
PU4202
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
PR4214 A5
PR4213
1 2 1 2
PWR_VCORE0_IDES_P A4
IDES_N
IDES_P 2120mils or Copper Shape
20101012
7K5R2F-1-GP A6
s1 VX#D1 D1
D2
PWR_VCORE_VX0
9K31R2F-GP 42 PWR_VCORE_DB0 DB0 VX#D2
42 PWR_VCORE_DB1 A1 DB1 VX#D3 D3
42 PWR_VCORE_DB2 B1 DB2 VX#D4 D4
VX#D5 D5
PC4212 B6 D6
42 PWR_VCORE_SPHASE_0 SPHASE VX#D6
1 2PWR_VCORE_IDES0_P_1 VT1314SFCX-001-GP-U
d2 VX#F1
VX#F2
F1
F2
5V_S5 PR4211 A3 AVDD VX#F3 F3
SC1KP50V2KX-1GP VX#F4 F4
1 2 PU4202_AVDD B3 AGND VX#F5 F5
B4 AGND VX#F6 F6
10R2J-2-GP B5 AGND
1 PU4202_AVDD
AGND
AGND
C C
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND_1317S_1
A2
B2
G3
G2
G1
E3
E2
E1
C3
C2
C1
PG4201
PC4215 VCC_CORE
SCD1U25V3KX-GP 1 2
2
GAP-CLOSE-PWR
PR4230 PR4227 GND_1317S_1
20101012
1 2
1 2
GND_1317S_1
mass GND_1317S_1
4
7K5R2F-1-GP
9K31R2F-GP 1 PL4201
PC4217 IND-240NH-GP
PWR_VCORE_IDES1_N 1 2PWR_VCORE_IDES1_N_1 SC4700P50V2KX-1GP
42 PWR_VCORE_IDES1_N
PC4216 SC1KP50V2KX-1GP 5V_S5 400mils or Copper Shape
2
PWR_VCORE_IDES1_P
1
42 PWR_VCORE_IDES1_P
12/29 change PL4201 to HF part
SCD1U10V2KX-4GP
PC4220
PC4221
PC4222
PC4223
PC4224
PC4225
PC4226
SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
1
1
PWR_VCORE1_IDES_P_1
2
B B
1
PR4241
3K09R2F-1-GP
G6
G5
G4
C6
C5
C4
2
E6
E5
E4
PU4203
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
PWR_VCORE1_IDES_N
PR4248
PWR_VCORE1_IDES_P
A5
A4
IDES_N
IDES_P
53A=2120mils or Copper Shape
PR4247
1 2 1 2 D1 PWR_VCORE_VX1
VX#D1
42 PWR_VCORE_DB0 A6 DB0 VX#D2 D2
7K5R2F-1-GP A1 D3
9K31R2F-GP 42 PWR_VCORE_DB1 DB1 VX#D3
42 PWR_VCORE_DB2 B1 DB2 VX#D4 D4
PC4227 D5
VX#D5
20101012 1 2PWR_VCORE_IDES1_P_1 42 PWR_VCORE_SPHASE_1 B6 SPHASE VX#D6 D6
SC1KP50V2KX-1GP F1
VT1314SFCX-001-GP-U VX#F1
VX#F2 F2
PU4203_AVDD A3 F3
AVDD VX#F3
5V_S5 VX#F4 F4
PR4242 B3 F5
AGND VX#F5
B4 AGND VX#F6 F6
1 2
B5 AGND
AGND
AGND
10R2J-2-GP
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND_1317S_2
1
A PC4230 <Core Design> A

SCD1U25V3KX-GP
A2
B2
G3
G2
G1
E3
E2
E1
C3
C2
C1
2
Wistron Corporation
GND_1317S_2 Taipei Hsien 221, Taiwan, R.O.C.
1 2
GND_1317S_2 PG4202
GAP-CLOSE-PWR Title
GND_1317S_2 VT1316+1314_CPU_CORE(2/3)
A3
5 4 3 2 1
5 4 3 2 1
X01-0217 change PR4402& PR4406 to 4.12K(F)
D D
20101012 PR4403
PR4402
42 IDES_N_GFX 1 2 1 2
4K12R2F-GP
11KR2F-L-GP PC4414
320mils or Copper Shape
1
5V_S5 VCC_GFXCORE
PC4413 1 2 IDES_N_GFX_1 SC4700P50V2KX-1GP
2
SC2700P50V2KX-1-GP
PC4415
PC4416
PC4417
PC4418
PC4419
PC4420
PC4421
SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SCD1U10V2KX-5GP
PWR_AXG_IDES_P_1 5V_S5
1
2
2
1
1
11/18
PR4404
3K09R2F-1-GP
PR4401
10R2J-2-GP
PC4422 1 2 IDES_P_GFX_1
0.12UH~0.15UH 2120mils or Copper Shape
G4
G5
G6
C6
C5
C4
SC2700P50V2KX-1-GP
E4
E5
E6
J4
J5
J6
PU4401 PL4401
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
PR4405
PR4406 PWR_AXG_IDES_N A5 H1 PWR_AXG_VX 1 2
PWR_AXG_IDES_P IDES_N VX#H1 IND-D1UH-26-GP
42 IDES_P_GFX 1 2 1 2 A4 IDES_P VX#H2 H2
C C
PC4423
PC4401
PC4424
PC4425
PC4426
H3 68.R1010.10T
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
20101012 4K12R2F-GP VX#H3
11KR2F-L-GP VX#H4 H4
1
42 DB0_GFX A6 DB0 VX#H5 H5
42 DB1_GFX A1 DB1 VX#H6 H6
42 DB2_GFX B1 D1
2
DB2 VX#D1 20100802 Power:
VX#D2 D2
B6 D3 Change PL4401 to 68.R1010.10T.
42 SPHASE_GFX SPHASE VX#D3
VT1317SFCX-001-GP D4
VX#D4
VX#D5 D5
A3 AVDD VX#D6 D6
B3 AGND VX#F6 F6
B4 AGND VX#F5 F5
B5 AGND VX#F4 F4
F3
1PWR_AXG_AVDD
VX#F3
VX#F2 F2
2120mils or Copper Shape
AGND
AGND
F1
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VX#F1
A2
B2
E3
E2
E1
C1
C2
C3
J3
J2
J1
G3
G2
G1
PC4402
PC4403
PC4404
PC4405
PC4406
PC4407
PC4408
PC4409
PC4410
PC4411
PC4412
IC nguon cap cho khoi VGA ( KHI CPU da hoat dong)
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
1
1
PC4427
SCD1U25V3KX-GP DY DY
2
2
1 2
PG4401
B GAP-CLOSE-PWR B
GND_1317S_3
A <Core Design> A
Wistron Corporation
Title
VT1316+1317_AXG_CORE(3/3)
A3
5 4 3 2 1
5 4 3 2 1
1D05V_PWR 1D05V_VTT
DCBATOUT PWR_1D05V_DCBATOUT
PG4505
1 2
1 2
GAP-CLOSE-PWR-3-GP PG4506
PWR_1D05V_DCBATOUT 1 2
1 2 X02-0310 stuff EC4501
GAP-CLOSE-PWR-3-GP 84.00172.037 PG4507
D 1 2 D
PG4503 BSZ115N03MSC GAP-CLOSE-PWR-3-GP
1 2 Id=20A, Qg=9.8nC,
1
GAP-CLOSE-PWR-3-GP 11/10 PC4504 PC4505 PC4507 EC4501 PG4508
Rdson=8.9 mohm
SC10U25V5KX-GP
SC10U25V5KX-GP
SCD1U50V3KX-GP
1 2
SCD1U25V3KX-GP
PG4504 PU4502 GAP-CLOSE-PWR-3-GP
2
5
6
7
8
1 2 RJK03B9DPA-00-J5A-GP
TPS51218 for 1D05V
D
D
D
D
GAP-CLOSE-PWR-3-GP PG4509
1 2
GAP-CLOSE-PWR-3-GP
X01-0217 Change PR4501 to 78.7K(F)
G
4 PG4510
S
S
S
PR4516 1 2
GAP-CLOSE-PWR-3-GP
3
2
1
3D3V_S0 2 1 12/15 Design Current = 14.375A
PG4511
22.6A<OCP< 26.7A 1 2
10KR2J-3-GP PU4501 GAP-CLOSE-PWR-3-GP
37,48 1.05VTT_PWRGD
11/18 PC4502
1D05V_PWR
PR4501 1 11 PR4504 SCD1U25V3KX-GP PG4512
PWR_1D05V_TRIP PGOOD GND PWR_1D05V_VBST 1
1 2 2 TRIP VBST 10 2PWR_1D05V_VBST_R2 1 PL4501 1 2
19,46,47 RUNPWROK 1 2 78K7R2F-GP PWR_1D05V_EN 3 EN DRVH 9 PWR_1D05V_DRVH BOM merge 11/18 GAP-CLOSE-PWR-3-GP
PR4502 PWR_1D05V_VFB 4 8 PWR_1D05V_SW 2D2R3-1-U-GP 1 2
0R0402-PAD PWR_1D05V_CCM VFB SW
5 7 5V_S5 PG4513
CCM V5IN
1
6 PWR_1D05V_DRVL IND-1D5UH-34-GP 1 2
DRVL PC4508
1
1
PR4505 GAP-CLOSE-PWR-3-GP
1
100R2F-L1-GP-U
PR4503 PC4503 PU4503 PR4514 PT4501 PT4509
5
6
7
8
RJK03D4DPA-00-J5A-GP
SCD1U10V2KX-5GP
470KR2F-GP TPS51218DSCR-GP-U1 2D2R5F-2-GP 11/10
DY DY
PG4514
D
D
D
D
SC1U10V2KX-1GP
SE330U2VDM-L-GP
SE330U2VDM-L-GP
1 2
2
C GAP-CLOSE-PWR-3-GP C
2
1PWR_1D05V_SNUB 2
VTT_SENSE_L
PG4515
1
1
PC4501 11/10
G
4 1 2
SC1KP50V2KX-1GP
S
S
S
PR4506 PC4511 GAP-CLOSE-PWR-3-GP
1
12/15 9K76R2F-1-GP
2
3
2
1
SCD1U10V2KX-4GP
84.00460.037 DY PG4516
1 2
2
SiR460DP-T1-GE3 GAP-CLOSE-PWR-3-GP
PWR_1D05V_VFB 79.33719.L01
Id=40A, Qg=16.8nC, PG4517
Rdson=4.7~6.1 mohm DY PC4509 1 2
1
SC560P50V-GP PR4507 GAP-CLOSE-PWR-3-GP
2
20KR2F-L-GP
PG4518
1 2
GAP-CLOSE-PWR-3-GP
2
VSS_SENSE_L
PG4519
1
1 2
100R2F-L1-GP-U 11/10
PG4520
1 2
2
GAP-CLOSE-PWR-3-GP
VTT_SENSE_L 1 PR4509 2 VCCIO_SENSE 8
1
0R0402-PAD
B B
DY
SCD1U50V3KX-GP
1
2
PC4510
EC4502
DY SC1000P50V3JN-GP-U Vout=0.704V*(R1+R2)/R2
2
VSS_SENSE_L 1 PR4510 2 VSSIO_SENSE 8
0R0402-PAD
I/P cap: 10U 25V K0805 X5R/ 78.10622.51L

Inductor: 1.50UH PCMC104T Cyntec 3.8mohm/4.2mohm Isat =33Arms 68.1R510.10J
O/P cap: 330U2V EEFSX0D331ER 9mOhm 3Arms Panasonic/79.33719.L01
H/S: SIR172DP / 10.3mohm/12.4mOhm@4.5Vgs/ 84.00172.037
L/S: SiR460DP / 0.49mohm/0.61mOhm@4.5Vgs/ 84.00460.037
A <Core Design> A
Wistron Corporation
Title
TPS51218_+1.05V_VTT
A3
5 4 3 2 1
5 4 3 2 1
SSID = PWR.Plane.Regulator_1p5v0p75v +PWR_SRC_1D5V
11/10
DCBATOUT +PWR_SRC_1D5V
PC4614
PG4603
SC10U25V5KX-GP
SC10U25V5KX-GP
SC10U25V5KX-GP
SCD1U50V3KX-GP
SC4D7U25V5KX-GP
1D5V_PWR 1D5V_S3
PC4613
2 1
1
5V_S5 GAP-CLOSE-PWR-3-GP
PC4609
PC4611
PC4612
PG4604 PG4608
SC1U10V3KX-3GP
2
2 1 1 2
GAP-CLOSE-PWR-3-GP GAP-CLOSE-PWR-3-GP
PC4601
3D3V_S0 84.00172.037
D D
1
BSZ115N03MSC PG4605 PG4609
Id=20A, Qg=9.8nC, 2 1 1 2
4
2
1
G1
D1
D1
D1
Rdson=8.9 mohm PU4602
PR4604
Q1
FDMS3604S-GP PG4606 PG4610
20KR2J-L2-GP 2 1 1 2
PHASE
PU4601 S1/D2
9
Q2 S2
2
PR4605_2
20 12 PC4619 PG4611
19,45,47 RUNPWROK PGOOD V5IN
G2
S2
S2
SCD1U25V3KX-GP 1 2
17 PR4605 GAP-CLOSE-PWR-3-GP
5
37 0D75V_EN VTTEN
VBST 15 PWR_1D5V_VBST 1 2 1 2 12/15 Design Current = 16.34A
PWR_1D5V_EN 16 2D2R3J-2-GP PG4612
EN/PSV
12/20 25.7A<OCP< 30.3A 1 2
PWR_1D5V_VREF 6 14 PWR_1D5V_DRVH 1D5V_PWR GAP-CLOSE-PWR-3-GP
VREF DRVH
1
PL4601
PR4603 BOM merge 11/18 PG4613
10KR2F-2-GP 13 PWR_1D5V_SW 1 2 1 2
SW GAP-CLOSE-PWR-3-GP
11/18 COIL-1UH-51-GP-U
SCD1U10V2KX-5GP
SC4D7U6D3V5KX-3GP
2
1
PWR_1D5V_REFIN 8 11 PWR_1D5V_DRVL PG4614
PC4621
REFIN DRVL
1
PT4603
PC4620
1 2
52K3R2F-L-GP
1
PG4607
10
DY DY
SCD1U25V3KX-GP
SCD1U50V3KX-GP
PGND
1 PR4601 2
SE220U2VDM-8GP
PWR_1D5V_MODE 19 2D2R5F-2-GP 68.R6810.20G 1D5V
SCD01U16V2KX-3GP
GAP-CLOSE-PWR-3-GP
2
MODE
2
PC4603
EC4601
PG4615
200KR2F-L-GP
Id=22~39A
2
1
1 2
1 PR4608 2
11/18 PWR_1D5V_TRIP PWR_1D5V_VDDQS DCR=2.4~2.7mohm GAP-CLOSE-PWR-3-GP

PC4602
18 9
1
TRIP VDDQS TPS51216_PHS_SET

BOM merge 11/18 Size=10X11.5X4
PWR_1D5V_VDDQS
2
C C
PR4601_1
2 PG4616
240R2F-1-GP
VTTIN
1
PWR_1D5V_VTTREF 5 +0D75V_DDR_P
PR4602
1 2
51KR2F-L-GP
VTTREF
2 PR4606 1
SCD1U10V2KX-5GP
SC10U6D3V5KX-1GP
PC4622 GAP-CLOSE-PWR-3-GP
3
DY
SC10U6D3V5MX-3GP
VTT
1
PC4610 SC330P50V2KX-3GP
2
PC4616
1
1
SC10U6D3V3MX-GP Change part refernce name 11/26
PC4615
PC4617
1 PG4617
1
VTTS
11/18 21 DY 1 2
2
GND
4 X01-0210 del PT4602 GAP-CLOSE-PWR-3-GP
2
VTTGND
7 GND X01-0209 PT4603
PG4618
TPS51216RUKR-GP UMA-->220uF 1 2
BOM merge 11/18 DIS-->470uF GAP-CLOSE-PWR-3-GP
74.51216.073 1D5V_PWR
PG4619
SC1U10V3KX-3GP
X01-0210 change PC4610 from 0.22uF to 10uF
PC4604
1 2
1
GAP-CLOSE-PWR-3-GP
X01-0217 change PR4601 to 52.3K(F)
PG4620
2
+0D75V_DDR_P 0D75V_S0 1 2
1 2
PG4621
GAP-CLOSE-PWR-3-GP 1 2
1 2
State S3 S5 VDDR VTTREF VTT PG4622
GAP-CLOSE-PWR-3-GP 1 2
S0 Hi Hi On On On GAP-CLOSE-PWR-3-GP
B
S3 Lo Hi On On Off(Hi-Z) DDR_VREF_S3
PG4623
B
1 2
S4/S5 Lo Lo Off Off Off PR4607 GAP-CLOSE-PWR-3-GP
PWR_1D5V_VTTREF 1 PR4611 2 0R0402-PAD
0R0603-PAD 1 2 PWR_1D5V_EN PG4624
19,27 PM_SLP_S4#
MODE 1 2
GAP-CLOSE-PWR-3-GP
1
11/10 PR4608 Frequency Discharge Mode PC4606
DY SCD1U10V2KX-5GP PG4625
200k ohm 400kHz 1 2
2
Tracking Discharge GAP-CLOSE-PWR-3-GP
100k ohm 300kHz
68k ohm 300kHz
Non-tracking Discharge
47k ohm 400kHz
I/P cap:10U 25V K0805 X5R/ 78.10622.51L
Inductor: 0.68UH PCMC104T-R68MN Cyntec 2.4mohm/2.7mohm Isat =39Arms 68.R6810.20G
O/P cap: 220U2V EEFCX0D221R 15mOhm 2.7Arm/Panasonic/79.22719.20L
H/S,L/S: FDMS3604S / 7.5mohm/9.8mOhm@4.5Vgs, 2.6mohm/3.2mOhm@4.5Vgs/ 84.03604.037
A <Core Design> A
Wistron Corporation
Title
TPS51216_+1.5V_SUS
A3
5 4 3 2 1
5 4 3 2 1
+1.8V_RUN
SSID = PWR.Plane.Regulator_1p8v Design current = 1.015A
APW7153B for 1D8V_S0 DIS
PR4709
1D8V_PWR 1D8V_S0
3D3V_S0 1
DY 2
10KR2F-2-GP PG4704
3D3V_S5 1 2
D 19,45,46 RUNPWROK GAP-CLOSE-PWR-3-GP D
PG4706 11/4
1
PR4705 PU4702 1 2
2D2R2F-GP
APW7153BQBI-TRG-GP 12/15 GAP-CLOSE-PWR-3-GP
1
PC4715 PC4711 DIS 1D8V_PWR
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
6 PVDD PGND 5
PL4702 PG4707
2
2
7 4 PWR_1D8V_LX 1 DIS 2 1 2
VDD LX#4 GAP-CLOSE-PWR-3-GP
1
PC4708 8 DIS 3 COIL-1D5UH-28-GP
POK LX#3
1
SCD1U10V2KX-5GP
DIS PC4713 PC4714 PC4716
PWR_1D8V_FB 9 2 PR4708DIS DIS
2
FB GND
SC100P50V2JN-3GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
20KR2F-L-GP
2
PWR_1D8V_COMP 10 1 PWR_1D8V_RT
GND
COMP SHDN/RT
2
1
PC4707
SCD1U10V2KX-4GP
PR4706
1
PR4704 74.07153.A73 PWR_1D8V_FB
11
820KR2F-GP
1MR2J-1-GPDIS DIS DY
1
2
2
PR4707
PC4709 PR4710
16KR2F-GP DIS
1DIS 2PWR_1D8V_COMP_R
1 DIS 2
2
SC1KP50V2KX-1GP 20KR2F-L-GP
PC4712
C C
1DY 2
SC47P50V2JN-3GP
Vo=0.8*(1+(R1/R2))
BOM merge 12/15

2N7002K-2-GP 12/9 EE change to
19,27,36,37 PM_SLP_S3# 1PR4711 2 PWR_1D8V_RT_R G
0R0402-PAD
D
1
PC4710
SCD1U10V2KX-5GP DY S
DIS
2
PQ4702
APL5930 for 1D8V_S0 UMA

MOS_N-FET
3D3V_S5
5V_S5
B B
1
PC4717
SC1U10V3KX-3GP UMA 1D8V_PWR
2
PU4703
19,45,46 RUNPWROK
VIN#5 5
6 VCNTL VOUT#4 4
7 POK VOUT#3 3
19,27,36,37 PM_SLP_S3# 1PR4712 2 1D8V_RUN_EN 8 EN UMA FB 2
0R0402-PAD 9 1
VIN#9 GND
SC4700P50V2KX-1GP
1
1
APL5930KAI-TRG-GP PR4714 PC4719
5912_1.8V_RUN_FB
PR4713 16K5R2F-2-GP SC68P50V2JN-1GP

PC4718
47KR2J-2-GP DY DY 74.05930.03D
UMA
2
UMA
2
2
1
PR4715
A UMA 13K3R2F-L1-GP <Core Design> A
Vout=0.8V*(R1+R2)/R2
2
Wistron Corporation
I/P cap: 4.7U 25V K0805 X5R/ 78.47522.51L Title

O/P cap: 22U 25V M0805 X5R/ 78.22610.51L APW7153B_ +1.8V_RUN
Inductor: 1.5U PCMC063T Cyntec 14mohm/15mohm Isat =18Arms 68.1R510.10K Size Document Number Rev
A3
5 4 3 2 1
5 4 3 2 1
APL5916 for VCCSA

11/18
11/18
1D05V_VTT
PG4801
5V_S5 PWR_VCCSA_VIN 1 2
D GAP-CLOSE-PWR-3-GP D
11/18
1
PR4801 PG4802
0R0402-PAD 1 2
GAP-CLOSE-PWR-3-GP
3D3V_S0
Iomax=6A
OCP>9A
2
PWR_VCCSA_VCNTL
VCCSA=0.9V
1
1
PC4801 PC4802 PC4803
1
PR4802 SC1U6D3V2KX-GP
2
1KR2F-L-GP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
2
2
2
6
PU4801 PG4803
1 2
VCNTL
D85V_PWRGD 7 5 GAP-CLOSE-PWR-3-GP 0D85V_S0
42 D85V_PWRGD POK VIN VCCSA_PWR
VIN 9
PG4804
37,45 1.05VTT_PWRGD 1PR4803 2 PWR_VCCSA_EN 8 EN VOUT 3 1 2
0R0402-PAD GAP-CLOSE-PWR-3-GP
VOUT 4 R1
1
PR4804 PC4804 PG4805
1
11/18 2 10KR2F-2-GP 1 2
GND
FB
SC100P50V2JN-3GP
DY PC4809 GAP-CLOSE-PWR-3-GP
2
SC1U6D3V2KX-GP
1
PWR_VCCSA_FB PC4805 PC4806 PT4801 PG4806
1
C X01-0209 dummy PC4809 for BBU result 1 2 C
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
APL5916KAI-TRL-GP GAP-CLOSE-PWR-3-GP
R2
2
1
DY
ST150U10VDM-4GP
1
PR4806 PG4807
PR4805 160KR2F-GP DY 1 2
80K6R2F-GP GAP-CLOSE-PWR-3-GP
2
PG4808
2
1 2
GAP-CLOSE-PWR-3-GP
PWR_VCCSA_SEL1
Vout=0.8*(1+R1/R2)
D
PQ4801
2N7002K-2-GP
11/25
DY
DY
PR4807
G
S
B PWR_VCCSA_SEL0 B
1 2 VCCSA_SEL 9
10KR2J-3-GP
1
DY PC4807
SCD1U10V2KX-4GP
A JV10-CS A
Wistron Corporation
Title
APL5916_VCCSA
5 4 3 2 1
SSID = VIDEO SSID = Inverter
DCBATOUT_LCD
INVERTER POWER
1 R4907
2
100KR2J-1-GP
RN4901 DCBATOUT DCBATOUT_LCD
LCD1 BLON_OUT_C 1 8 BLON_OUT 27
31 LCD_TST_C 2 7 F4901 POLYSW-1D1A24V-GP-U
LCD_TST 27
NP1 3 6
A00-0408 Add RN4903 for ESD issue. 1 30 LCD_BRIGHTNESS 4 5 L_BKLT_CTRL 17 1 2
2 29 SRN100J-4-GP
1
RN4903 BLON_OUT_C 3 28 69.50007.A31
SRN33J-5-GP-U LCD_BRIGHTNESS 4 27 2nd = 69.50007.A41 C4905 DY C4906
1 4 LVDS_DDC_DATA 5 26 SCD1U50V3KX-GP SC1KP50V2KX-1GP
17 LVDS_DDC_DATA_R
2
17 LVDS_DDC_CLK_R 2 3 LVDS_DDC_CLK 6 25
17 LVDSA_CLK 7 24
17 LVDSA_CLK# 8 23
17 LVDSA_DATA2 9 22 USB_CAMERA#
17 LVDSA_DATA2# 10 21 USB_CAMERA
17 LVDSA_DATA1 11 20 LCD_TST_C
12 19 LCDVDD 11/ 17 dummy C4905
17 LVDSA_DATA1# 3D3V_CAMERA_S0
17 LVDSA_DATA0 13 18 3D3V_S0
17 LVDSA_DATA0# 14 17
15 16
NP2
SCD1U10V2KX-5GP
1
2
C4901
C4904
32 LCD_BRIGHTNESS
SC1U6D3V2KX-GP
LCD_TST
ETY-CONN30E-2-GP-U2
1
AFTP4906 1 USB_CAMERA#
SC33P50V2JN-3GP
AFTP4907 1 USB_CAMERA 20.F0891.030
SC33P50V2JN-3GP
1
1
EC4905
EC4906
DY
2
For EMI request
3D3V_S0 3D3V_CAMERA_S0
0818
USB_CAMERA 3 4 USB_PP12 18
R49081 20R3J-0-U-GP
WCM2012F2S-GP-U2
USB_CAMERA# 2 1TR4901 USB_PN12 18 SSID = VIDEO
SC33P50V2JN-3GP
1
1
EC4903 C4903
DY SC10U6D3V5KX-1GP
LCD POWER
2
11/15 change LCDVDD source from S0 to S5
Close to LVDS connector
A00-0320 Change TR4901 to 120ohm. 3D3V_S5
12/2 modify +LCDVDD to LCDVDD
A00-0406 remove R4903, R4904
11/17 move RN1703 from P17 to P49 LCDVDD
A00-0408 SWAP TR4901 net and change part refernce Q4901
1 D D 6
2 D D 5
3D3V_S0 3 G S 4
R4912
15V_S5 1 2 330KR2J-L1-GP AO6402A-GP
FPVCC_CTL1
RN4902
1
1 2
1 4 LVDS_DDC_DATA_R C4909 SCD1U25V2KX-GP R4916
2 3 LVDS_DDC_CLK_R 150R3J-L-GP
2 DY 100KR2J-1-GP
1
2
SRN2K2J-1-GP R4906 Q4902
4 3 LCDVDD_1
5 2
Close to LVDS connector 12/22 swap net for layout 6 1
2N7002KDW-GP
LVDSA_CLK 5V_S5 1 2
LCD_BRIGHTNESS D4901 R4917 100KR2J-1-GP
LVDSA_CLK# 1 Q4903
LCD_TST_C 17 LVDS_VDD_EN FPVCC_CTL3
3
3LCDVCC_EN 1 R1
2
1
EC4907 EC4908 EC4901 EC4902 2 R2

27 LCD_TST_EN
DY DY PDTC144EU-1-GP
DY DY
SC5D6P50V2CN-1GP
SC5D6P50V2CN-1GP
BAT54CPT-GP
2
2
SC33P50V2JN-3GP
SC33P50V2JN-3GP
12/9 BOM merge

<Core Design>
Wistron Corporation
For EMI request
Title
LCD Connector
A3
5 4 3 2 1
SSID = VIDEO 3D3V_S0 5V_CRT_S0
11/ 17 Add RN5012 for SMbus pull high JVGA_VS

JVGA_HS AFTP501 1 5V_CRT_S0
1
2
AFTP502 1 DDC_DATA_CON
3
4
X01: change RN5012 from 0R to 2.2KR AFTP503 1 DDC_CLK_CON
SC18P50V2JN-1-GP
SC18P50V2JN-1-GP
1
1
C5017
RN5012 RN5001 AFTP504 1 CRT_R
C5018
SRN2K2J-1-GP SRN2K2J-1-GP AFTP505 1 CRT_G
DY DY AFTP506 1 CRT_B
2
3D3V_S0 AFTP507 1 JVGA_HS
4
3
D 11/3 Add RN5010 for CRT SMBus AFTP508 1 JVGA_VS D
2
1
X02-0303 change 0R to short pad Q5001
DDC_DATA_CON
DDC_CLK_CON
DDCDATA 4 3 DDC_DATA_CON
11/29 change CRT1 to 20.20927.015
1
1
5 2 DY DY C5014
17 PCH_CRT_DDCDATA 2 RN5010 3 C5013
1 4 6 1 SC22P50V2JN-4GP SC22P50V2JN-4GP
17 PCH_CRT_DDCCLK
2
2
0R4P2R-PAD 5V_CRT_S0_R
2N7002KDW-GP X02-0309 change AFTP
RN
DDCCLK
to follow DV14 AMD
DDC_CLK_CON CRT1
9 VCC_CRT NC#4 4
5V Tolerance NC#11 11
RN5006 DDC_DATA_CON 12
DDC_DATA_CON DDC_CLK_CON DDCDATA_ID1
85 CRT_GFX_DDCDAT 2 3 15 DDCCLK_ID3
DDC_CLK_CON
85 CRT_GFX_DDCCLK 1
DIS_CRT
4
CRT_R 1
GND 5
6
SRN0J-6-GP RN CRT_G CRT_RED GND
2 CRT_GREEN GND 7
1 RN5007 8 CRT_B 3 CRT_BLUE GND 8
17 PCH_CRT_BLUE 2 7 CRT_BLUE 10
CRT_GREEN JVGA_VS GND
17 PCH_CRT_GREEN 3 6 14 VSYNC GND 16
CRT_RED JVGA_HS AFTP509
Layout Note: 17 PCH_CRT_RED 4 5
0R8P4R-PAD
13 HSYNC GND 17 1
C C
D-SUB-15-111-GP
*Pi-filter & 150 Ohm pull-down
RN5005 20.20927.015
resistors should be as close 1 8
2 7
as to CRT CONN. 85 CRT_GFX_R
85 CRT_GFX_G 3
DIS_CRT
6
* RGB signal will hit 75 Ohm 85 CRT_GFX_B 4 5
first, then pi-filter, finally SRN0J-7-GP
CRT CONN. 11/15 remove F5501 base on brazos result.

11/18 change Fuse for CRT and HDMI share
11/ 17 Remove R5001
CRT_RED L5001 1 2 BLM15BA330SS1D-GP CRT_R
5V_CRT_S0_R 5V_CRT_S0 5V_S0
D5001
F5101
CRT_GREEN L5002 1 2 BLM15BA330SS1D-GP CRT_G 1 2 2 1
FUSE-1D1A6V-4GP-U CH551H-30PT-GP
CRT_BLUE L5003 1 2 BLM15BA330SS1D-GP CRT_B 69.50007.691
2nd = 69.50007.771
SC8P250V2CC-GP
SC8P250V2CC-GP
SC8P250V2CC-GP
SC10P50V2JN-4GP
SC10P50V2JN-4GP
SC10P50V2JN-4GP
4
3
2
1
C5007
C5008
C5009
1
1
C5004
C5005
C5006
RN5003
SRN150F-1-GP
DY DY DY
2
2
B B
5
6
7
8
5V_CRT_S0
5V_CRT_S0
D5002
17 PCH_CRT_HSYNC 2 RN5008 3 CRT_HSYNC
5V_CRT_S0 CRT_VSYNC
14
10
2 17 PCH_CRT_VSYNC 1 4
0R4P2R-PAD
CRT_R 3
DY
RN
9
DY 8
1
DY 1 RN5009
Hsync & Vsync level shift C5012 83,85 VGA_CRT_HSYNC 2 3 CRT_HSYNC
SCD01U16V2KX-3GP U5001C CRT_VSYNC
83,85 VGA_CRT_VSYNC 1
DIS_CRT
4
2
7
BAV99PT-GP-U TC74VHCT125AFTQK2M-GP
SRN0J-6-GP
D5003
14
U5001A 2 CLOSE TO
CRT_HSYNC HSYNC_5 CRT_G TRANSFORMER
2
DY 3 3
DY
1 5V_CRT_S0
TC74VHCT125AFTQK2M-GP
14
7
4
U5001B RN5011
JVGA_HS BAV99PT-GP-U
14
13
2 3
CRT_VSYNC VSYNC_5 JVGA_VS
A 5
DY 6 1
DY 4 D5004 DN15ATI Whistler A
SRN0J-6-GP
TC74VHCT125AFTQK2M-GP
2 12
DY 11
Wistron Corporation
7
CRT_B 3
DY U5001D 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
X00 9/23
7
1 TC74VHCT125AFTQK2M-GP Taipei Hsien 221, Taiwan, R.O.C.
R50021 2 33R2J-2-GP Title

R50031 BAV99PT-GP-U
2 33R2J-2-GP
CRT Connector
X01-0208 change R5002, R5003 to 33R A3
A00
Enrico Caruso 14
Wednesday, April 13, 2011
Date: Sheet 50 of 105
5 4 3 2 1
5 4 3 2 1
SSID = VIDEO HDMI Level Shifter & CONNECTOR HDMI CONN

R5101 RR5106 HDMI_PLL_GND HDMI1
HDMI_CLK_R_C 1 0R0402-PAD
2 HDMI_CLK_R_C_CON HDMI_DATA1_R_C 1 0R0402-PAD
2 HDMI_DATA1_R_C_CON 21 20
2
1 HDMI_DATA2_R_C_CON
Q5103 R5123
D
2N7002K-2-GP DY 0R2J-2-GP 2
RR5102 RR5105 84.2N702.J31 3 HDMI_DATA2_R_C#_CON
HDMI_CLK_R_C# 1 0R0402-PAD
2 HDMI_CLK_R_C#_CON HDMI_DATA1_R_C# 1 0R0402-PAD
2 HDMI_DATA1_R_C#_CON 2ND = 84.2N702.031 4 HDMI_DATA1_R_C_CON
1
D 5 D
HDMI 6 HDMI_DATA1_R_C#_CON
5V_S0 7 HDMI_DATA0_R_C_CON
8
9 HDMI_DATA0_R_C#_CON
S
A00-0407 remove TR5101, TR5102, TR5103, TR5104 PAD and remove 0R PAD. HDMI 10 HDMI_CLK_R_C_CON
11 11/18 change Fuse for CRT and HDMI share
12 HDMI_CLK_R_C#_CON
1
13
R5113 14 5V_CRT_S0_R
DY 100KR2J-1-GP 15 DDC_CLK_HDMI
16 DDC_DATA_HDMI
17
2
18
19
SCD1U10V2KX-5GP
23 22
1
11/19 change net Q5103_G to 5V_S0
C5102
RR5104 RR5108 SKT-HDMI19P-63-GP-U HDMI
HDMI_DATA0_R_C 1 0R0402-PAD
2 HDMI_DATA0_R_C_CON HDMI_DATA2_R_C 1 0R0402-PAD
2 HDMI_DATA2_R_C_CON
2
22.10296.171 X02-0309
Del AFTP test point to follow DV14 AMD
HPD_HDMI_CON
RR5103 RR5107
HDMI_DATA0_R_C# 1 0R0402-PAD
2 HDMI_DATA0_R_C#_CON HDMI_DATA2_R_C# 1 0R0402-PAD
2 HDMI_DATA2_R_C#_CON
3D3V_S0
12/9 BOM merge
12/23 BOM merge
C C
HDMI
3
HDMI Q5102
1 2HDMI_HPD_B 1 PMBS3904-1-GP
R5111 150KR2J-L1-GP 84.03904.L06
2ND = 84.03904.P11
2
1
R5110 HDMI_HPD_E 1 2 HDMI_PCH_DET 17
R5125 0R0402-PAD
200KR2J-L1-GP
DY
1
R5112
HDMI DISCRETE/ UMA Co-lay
2
HDMI 10KR2J-3-GP
C5103 1HDMI
2 SCD1U10V2KX-5GP HDMI_CLK_R_C#
2
17 HDMI_CLK_R# C5104 SCD1U10V2KX-5GP HDMI_CLK_R_C
17 HDMI_CLK_R 1HDMI
2
C5105 1HDMI
2 SCD1U10V2KX-5GP HDMI_DATA0_R_C#
17 HDMI_DATA0_R# C5106 SCD1U10V2KX-5GP HDMI_DATA0_R_C
17 HDMI_DATA0_R 1HDMI
2
66.68136.08L=>680ohm for UMA
66.47136.A8L=>470ohm for GPU
C5110 1HDMI
2
C5108 1HDMI
2
B B
8
7
6
5
8
7
6
5
RN5106 RN5107
HDMI SRN680J-GP HDMI SRN680J-GP
1
2
3
4
1
2
3
4
HDMI_PLL_GND
5V_CRT_S0_R
12/1 Modify 5V_HDMI to 5V_CRT_S0_R
4
3
3D3V_S0
HDMI RN5101
11/18 change RN5117 BOM control SRN2K2J-1-GP
property to HDMI
Q5104
1
2
DDC_CLK_Q 4 3 DDC_CLK_HDMI
5 HDMI 2
17 PCH_HDMI_CLK 2 RN5117 3
17 PCH_HDMI_DATA 1 4 6 1
0R4P2R-PAD
2N7002KDW-GP
RN
X02-0303 change 0R to short pad DDC_DATA_Q

<Core Design>
A 11/16 Del RN5112~5115 for no need to reserve for VGA 84.2N702.A3F A
DDC_DATA_HDMI
2nd = 84.DM601.03F
Wistron Corporation
Routing Guidelines:
Title
CTRLDATA must be routed longer than CTRLCLK within 1000 mils (25.4 mm).
The total delay on CTRLDATA should be longer than CTRLCLK. HDMI Level Shifter/Connector
A3
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
Wistron Corporation
Title
Reserved
A3
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
Wistron Corporation
Title
LVDS_Switch
A3
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
Wistron Corporation
Title
Reserved
A3
5 4 3 2 1
5 4 3 2 1
SSID = User.Interface
D D
C C
(Blanking)
B B
Wistron Corporation
Title

ITP/Fan Connector Rev
A3
5 4 3 2 1
SSID = SATA SATA HDD Connector 11/10 Change HDD1 CONN to 62.10065.031
12/22 Change HDD1 CONN to62.10065.H71
5V_S0 3D3V_S0
HDD1
3D3V_S0 P1 V33 16 16
C5605
C5606
P2 17
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SC10U6D3V5KX-1GP
SC10U10V5ZY-1GP
V33 17
P3 V33
C5601
C5604
NP1 NP1
5V_S0 P7 V5 NP2 NP2
1
P8
2
V5
P9 V5
DY DY
2
AFTP5607 1HDD1_20 P13 S1
AFTP5608 V12 GND
1HDD1_21 P14 V12 GND S4
AFTP5609 1HDD1_22 P15 S7
V12 GND
GND P4
GND P5
21 SATA_TXP0 S2 A+ GND P6
Close to HDD1 21 SATA_TXN0 S3 A- GND P10
GND P12
21 SATA_RXP0 C5615 1 2SCD01U16V2KX-3GP SATA_RXP0_C S6
C5616 B+
21 SATA_RXN0 1 2SCD01U16V2KX-3GP SATA_RXN0_C S5 B- DAS/DSS P11
SKT-SATA7P-15P-80-GP
62.10065.H71
ODD Connector
ODD_PWR_5V
ODD1
S1 P2
22 SATA_ODD_PWRGT SATA Zero Power ODD
GND +5V
S4 GND +5V P3
S7 U5601
GND SATA_ODD_PRSNT# G547F1P81U-GP ODD_PWR_5V
P5 GND DP P1
SATA_ODD_DA#_C
DY SATA_ODD_PRSNT# 22
5V_S0
P6 GND MD P4 1R5602 2 SATA_ODD_DA# 18
8 0R2J-2-GP 4 5
GND EN/EN# OC# ODD_PWR_5V
9 GND A- S3 SATA_TXN4 21 3 IN#3 OUT#6 6 100 mil
A+ S2 SATA_TXP4 21 2 IN#2 OUT#7 7
S5 SATA_RXN4_C C5607 1 2SCD01U16V2KX-3GP SATA_RXN4 21 1 8
B- GND OUT#8
1
S6 SATA_RXP4_C C5608 1 2SCD01U16V2KX-3GP SATA_RXP4 21 C5609
B+
1
SC10U6D3V5KX-1GP C5610
74.00547.C79 SC10U6D3V5KX-1GP
2
1
SKT-SATA7P+6P-26-GP-U 2ND = 74.02191.079
2
22.10300.201 R5604
DY 10KR2J-3-GP
12/21 ODD1 to 22.10300.201 Current limit
2
Active High
When the drive is powered on, the FET to the MD/DA pin drive is OFF.
typ =>2A
When the drive is powered off, the FET to the MD/DA pin is ON
3D3V_S0 3D3V_S0
3D3V_S0
A00-0408 Add R5606 to pull high 3.3V_S0

2
RN5601
SATA_ODD_PWRGT 4 1 R5605 R5606 Change pull high to 3.3V_S0
SATA_ODD_DA# 3 2 100KR2J-1-GP 10KR2J-3-GP
SRN10KJ-5-GP
1
SATA_ODD_DA#_C
ODD_PWRGT#
SUPPORT ZERO SATA ODD

6
Q5601 <Core Design>

2N7002KDW-GP
84.2N702.A3F
2nd = 84.DM601.03F
Wistron Corporation
1

Title
SATA_ODD_PWRGT SATA_ODD_DA#
HDD/ODD
A3
5 4 3 2 1
SSID = ESATA
D D
C C
(Blanking)
B B
A <Core Design> A
Wistron Corporation
Title
ESATA
A3
5 4 3 2 1
5 4 3 2 1
SSID = AUDIO
D Speaker Connector D
5
SPK1
1 ACES-CON4-4-GP
29 AUD_SPK_L-
29 AUD_SPK_L+ 2
29 AUD_SPK_R- 3
29 AUD_SPK_R+ 4
6
1
1
EC5801 EC5802 EC5803 EC5804
MLVG0402220NV05BP-GP-U
DY DY DY DY AFTP5805 1
2
2
20.F0765.004
C C
AFTP5801 1 AUD_SPK_L-
AFTP5802 1 AUD_SPK_L+
AFTP5803 1 AUD_SPK_R-
AFTP5804 1 AUD_SPK_R+
11/10 remove MIC1
B B
11/26 reserve MIC2
12/7 change MIC2 to 20.F1050.002
AFTP5808
MIC2
3
1
29,82 INT_MIC_L_R 1
MIC2
2
AFTP5809 1 4
ACES-CON2-19-GP
20.F1889.002
12/7 Change to digital GND

X02-0315 Change MIC2 to 20.F1889.002
Wistron Corporation
Title
SPEAKER CONN
A3
5 4 3 2 1
5 4 3 2 1
X01-0211 Add EMI solution for Surge

MDO2+
MDO2-
SSID = LOM
5
ER5910 ER5911 U5901
LAN TransFormer 75R2J-1-GP

10/100
75R2J-1-GP
10/100
LAN_MDI0P
LAN_MDI0N
1
2
MCT LAN_MDI1P 4 Surge
11/30 swap net LAN_MDI1N 6
MDO3+
D XF5901 MDO3- D
1
1CT:1CT MDO3+ ER5913 ER5912
31 LAN_MDI3P 2 23
75R2J-1-GP 75R2J-1-GP 11/27 Del U5902
1 24 MCT3 10/100 10/100 TVLST2304AD0-GP
Giga Main: 68.IH601.301
3 22 MDO3-
31 LAN_MDI3N
2
Giga 2nd: 68.05009.30A MCT
1CT:1CT MDO2+
31 LAN_MDI2P 5 20
10/100 Main: 68.HH035.301 4 21 MCT2
MCT3
MCT2
MCT1
MCT0
10/100 Main: 68.01284.30A 31 LAN_MDI2N 6 19 MDO2-
1CT:1CT MDO1+
31 LAN_MDI1P 8 17
C5906
C5905
R5906
R5905
7 18 MCT1
1
9 16 MDO1-
31 LAN_MDI1N
4
3
XFOM RN5901
Surge Surge
SC1KP3KV8KX-GP-U
2
2
1CT:1CT MDO0+
31 LAN_MDI0P 11 14 GIGA SRN75J-2-GP-U Non-Surge Non-Surge
0R3J-0-U-GP
0R3J-0-U-GP
SC1KP3KV8KX-GP-U
2
2
10 15 MCT0
1
2
LOM_TCT
12 13 MDO0-
31 LAN_MDI0N
C C
1MCT1_C
1MCT0_C
XFORM-24P-19-GP
2nd = 68.89240.30B
1
R5902 R5901
C5902 75R5F-1-GP 75R5F-1-GP
SCD1U10V2KX-5GP GD5901
12/6 change resistor package.
2
2
MDO0+ 1 2 MDO0-
Surge
GT1206150ASMD-GP
1 MCT
GD5902
Surge
1
MDO1+ 1 2 MDO1- Non-Surge
Surge C5901
SC1KP3KV8KX-GP-U C5911
2
SC1KP2KV6KX-GP
GT1206150ASMD-GP
11/27 Del GDT5903, GDT5904 11/25 modify to CRC circuit and divided
resistor as EMI suggest
11/29 Change C5911 to 78.1022S.22L
B
X02-0311 Change GDT5901& GDT5902 to GD5901& GD5902 B
0722 : change to gas tube
RJ45
RJ45
9
NP1
MDO0+ 1
MDO0- 2
MDO1+ 3
MDO2+ 4
MDO2- 5
MDO1- 6
A MDO3+ 7 DN15ATI Whistler A
MDO3- 8
NP2 MDO1+ 1 AFTP5901
MDO2+ AFTP5902
10
MDO2-
1
1 AFTP5903 Wistron Corporation
RJ45-12P-4-GP-U MDO1- 1 AFTP5904 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
MDO3+ AFTP5905 Taipei Hsien 221, Taiwan, R.O.C.
22.10277.D01 MDO3-
1
AFTP5906
1
MDO0+ 1 AFTP5907 Title
MDO0- 1 AFTP5908
XFOM&RJ45
11/29 change RJ45 to 22.10277.D01 Size Document Number Rev
A3
5 4 3 2 1
5 4 3 2 1
Notes:
SSID = Flash.ROM The total SPI interface signal between EC and PCH
SPI FLASH ROM (4M byte) for PCH 3D3V_S5 canˇt not exceed 6500mil. The mismatch between
11/18 Merge R6003, R6004, R6005 to RN6001 3D3V_S5 SPI signal must be within 500mil
1
C6001 C6002
SC10U6D3V5KX-1GP
DY
SCD1U10V2KX-5GP
D D
2
8
7
6
5
RN6001
SRN4K7J-10-GP
1
2
3
4
12/6 swap net for layout SPI_HOLD_0#
X01-0211 swap CS#, WP# for layout 3D3V_S5
X01: modify CS#, WP# U6001
21,27 SPI_CS0#_R 1 CS# VCC 8

21,27 SPI_SO_R 1 2 SPI_SO 2 7
R6001 33R2J-2-GP SPI_WP# DO HOLD# SPI_CLK
3 WP# CLK 6 1R6026 0R0402-PAD
2 SPI_CLK_R 21,27
4 5 SPI_SI 1R6025 0R0402-PAD
2 SPI_SI_R 21,27
VSS DI
2
11/1 Add R6026, R6025 for EMI
1
EC6004 DY DY R6002 W25Q32BVSSIG-1-GP X02-0309 Change 0R to short pad
1
SC4D7P50V2CN-1GP 10KR2J-3-GP
72.25Q32.A01 EC6003
DY DYEC6001
2
2nd = 72.25320.C01
SC4D7P50V2CN-1GP
SC4D7P50V2CN-1GP
1
2
3rd = 72.25032.D01
C C
11/18 reserve R6002 for WP# and change
change DO pin pull down to capacity
SSID = RBATT
3D3V_AUX_S5
B B
RTC_AUX_S5 Q6001
2
+RTC_VCC
3 RTC1
3
1 RTC_PWR 1 R6006
2 1
2
1KR2J-1-GP 2
C6003 CH715FPT-GP 4
SC1U6D3V2KX-GP
1
83.R0304.B81 ACES-CON2-31-GP
2nd = 83.00040.E81 20.F1606.002
Width=20mils
X02-0310 Del RTC AFTP to follow DV14 AMD

11/29 change RTC1 to 20.F1606.002
R6007 1 DY 2 100R2J-2-GP
2N7002K-2-GP
RTC_PWR G
A
VccRTC is now connected to VccDSW3_3 <Core Design> A
1
D RTC_SENSE# 22
R6008
10MR2J-L-GP S
through the Schottky diode instead of the 3.3V Sus well. Wistron Corporation
Q6002 Taipei Hsien 221, Taiwan, R.O.C.
2
84.2N702.J31
Title
2ND = 84.2N702.031
Flash/RTC
11/23 add RTC DET circuit Size Document Number Rev
A3
5 4 3 2 1
5 4 3 2 1
SSID = USB
USB20_VCCA USB20_VCCA
5V_S5 U6102
100 mil USB2
1 GND OUT#8 8 5
2 IN#2 OUT#7 7 1
D 3 IN#3 OUT#6 6 D
1
4 5 C6103 C6104 TC6101 DY TC6103 USB_PN1_R 2
EN/EN# OC#
1
C6102 USB_PP1_R 3
ST100U6D3VBML1GP
SCD1U16V2KX-3GP
SCD1U10V2KX-5GP
ST220U6D3VDM-15GP
SC1U10V3ZY-6GP 4
2
G547F2P81U-GP AFTP6102 1 6
2
74.00547.A79 SKT-USB6-16-GP
USB_OC#0_1 18
22.10321.S01
LOW ACTIVE TYPE!!
11/30 Add TC6103
27 USB_PWR_EN#
11/29 change USB2 to 22.10321.S01
12/22 change TC6101 to 100uF
AFTP6101 1 USB20_VCCA
11/18 remove R6101, R6104 11/10 Move USB power SW to Mainboard AFTP6103 1 USB_PN1_R
AFTP6104 1 USB_PP1_R
USB20_VCCB
5V_S5 U6103
100 mil
1 GND OUT#8 8
C 2 7 C
IN#2 OUT#7 TC6102
3 IN#3 OUT#6 6
1
4 5 C6105 C6106
EN/EN# OC#
1
C6107 DY
SCD1U16V2KX-3GP
SCD1U10V2KX-5GP
ST220U6D3VDM-15GP
SC1U10V3ZY-6GP
2
G547F2P81U-GP
2
74.00547.A79
USB_OC#8_9 18
LOW ACTIVE TYPE!!
11/18 dummy C6106

27 USB_PWR_EN#
X02-0314 stuff C6106
B B
11/1 Stuff TR6101 for EMI
U6105
USB_PP1_R 4 3 USB_PP1 18 USB_PN1_R 1 6 USB_PP1_R

ESD I/O1 ESD I/O4
2 GND VP 5 5V_S5
TR6101 3 DY 4
USB_PN1_R WCM2012F2S-GP-U2 ESD I/O2 ESD I/O3
1 2 USB_PN1 18
A00-0320 Change TR6101 120ohm. IP4220CZ6-GP
A00-0406 remove R6102, R6103

DN15ATI Whistler
A A
Wistron Corporation
A00-0408 Swap TR6101 net for layout Taipei Hsien 221, Taiwan, R.O.C.
Title
USB Power SW
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
Wistron Corporation
Title
Reserved
A3
5 4 3 2 1
5 4 3 2 1
D D
(Blanking)
C C
B B
Wistron Corporation
Title
Bluetooth
A3
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A <Core Design> A
Wistron Corporation
Title

RESERVED Rev
5 4 3 2 1
5 4 3 2 1
SSID = Wireless Mini Card Connector(802.11a/b/g)

11/10 Change WLAN1 to 62.10043.841
D 3D3V_S0 D
WLAN1
3D3V_S0 53
1D5V_S0 NP1 1D5V_S0
X02-0309 change AFTP to follow DV14 AMD 1 2
1
1
C6502 C6503 C6504 AFTP6505 1 WLAN_ACT 3 4
1
C6506 BT_ACT 5 6
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SC10U6D3V5KX-1GP
DY C6505 7 8
SCD1U10V2KX-5GP
20 CLK_PCIE_WLAN_REQ#
2
9 10
SC10U6D3V5KX-1GP
2
2
20 CLK_PCIE_WLAN# 11 12
20 CLK_PCIE_WLAN 13 14
15 16
11/18 add R65008 R6509 for E51_TX,RX DY

27 E51_RXD 1R6509 20R2J-2-GP E51_RX 17 18
27 E51_TXD 1R6508 20R2J-2-GP E51_TX 19 20 WIFI_RF_EN 27
DY 21 22 PLT_RST# 5,18,27,31,71,83
20 PCIE_RXN4 23 24 3D3V_S0
5V_S5 25 26
20 PCIE_RXP4
WLAN_ACT 27 28 1D5V_S0
29 30
SCD1U25V2KX-GP
SCD1U25V2KX-GP
PCH_SMBCLK 14,15,20
1
C6501 C6508 11/23 add R6511 to connect BT_ACT 20 PCIE_TXN4 31 32 PCH_SMBDATA 14,15,20
20 PCIE_TXP4 33 34
DY DY 35 36 USB_PN11_R
2
BT_ACT 1R6511 2 37 38 USB_PP11_R

0R2J-2-GP 3D3V_S0 39 40
41 42
43 44 CARD_WLAN_OUT# CARD_WLAN_OUT# 68
C
27 BLUETOOTH_EN 1R6510 2 45 46 CARD_WPAN_OUT# CARD_WPAN_OUT# 68
C
0R2J-2-GP 47 48 1D5V_S0
49 50
5V_S5 1R6503 2 +5V_MINI_DEBUG 51 52 3D3V_S0
DY 0R2J-2-GP NP2
54
11/18 change R6507 to close gap
R6506 SKT-MINI52P-41-GP
18 USB_PP11 1 2 USB_PP11_R 11/18 change R6510 R6503 from 0603 to 0402 11/22 change WLAN LED control to KBC
0R0402-PAD
62.10043.841 11/26 Add CARD_WLAN_OUT#
and CARD_WPAN_OUT#
A00-0406 remove TR6501
R6505
1 2 USB_PN11_R
18 USB_PN11
0R0402-PAD
B B
12/22 swap nets for layout
Wistron Corporation
Title
MINICARD(WLAN)/ITP CONN
A3
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
Wistron Corporation
Title
Reserved
A3
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
Wistron Corporation
Title
Reserved
A3
5 4 3 2 1
5 4 3 2 1
1 R6811 2 5V_S5
0R0402-PAD PLED1
FRONT POWER LED R6806
3
Q6801
R2
E LED_PWR 2 1 FPOWER_LED_A 2K A1
1 R6813 2 PWRLED#_C
27 PWRLED#
0R0402-PAD
B
DY
R1
C 330R2J-3-GP LED-W-27-GP
11/26 reserve R6813 to aviod LED turn on PDTA143ET-GP

83.01221.R70
when Q6801 install 84.00143.M11 A00-0320 Change resistor for LED brightness EC6801 SC220P50V2KX-3GP
LED_PWR
D 1
DY
2 D
EC6810 SC220P50V2KX-3GP
5V_S0
SATA_LED_R 1 2DY
11/26 Add R6810 to avoid LED turn on
Q6805 HDLED1 EC6807 SC220P50V2KX-3GP
R2
E R6812
WHITE_LED_BAT# 1 2 DY
3
21 SATA_LED# 1R6810 2 SATALED#_C B R1
15KR2J-1-GP C SATA_LED_R 2 1 HDD_LED_A 1A K2
EC6809 SC220P50V2KX-3GP
PDTA143ET-GP 330R2J-3-GP LED-W-27-GP AMBER_LED_BAT# 1 2 DY
SATA HDD LED(White) 84.00143.M11 83.01221.R70
Need change to LOW actived from KBC GPIO 11/18 add R6804 R6805 0ohm
and dummy Q6807, Q6808
12/3 Change LED part reference to follow standard
Battery LED2(WHITE_LED) 1 R6804 2
0R0402-PAD
X02-0303 change 0R to short pad
Q6807
R6801 WHITE
C WHITE_LED_BAT# 2 1 BAT_WHITE#
R1
27 BATT_WHITE_LED# B DY 330R2J-3-GP
E
R2 5V_S5
C PDTC124EU-1-GP CHLED1 C
11/16 Del RN6801 to follow DV15 AMD 84.00124.H1K 3
1 R6805 2 2
0R0402-PAD
R6803
Q6808 499R2F-2-GP LED-OW-3-GP
AMBER_LED_BAT# BAT_AMBER#
27 CHG_AMBER_LED# B R1
DY
C 2 1
83.00326.G70
E
R2
PDTC124EU-1-GP
AMBER
Battery LED1(AMBER_LED) 84.00124.H1K
A00-0413 change R6806, R6812, R6801, R6808 to 330ohm
Wireless LED
B
A00-0328 change R6814 to 10KR

Power button B
11/26 change WLANLED control circuit 11/26 remove R6835 PWRBT1
5V_S0
WHITE 6
1 2 KBC_PWRBTN#_C 4A 4B
27 KBC_PWRBTN#
D6801 X02-0315 Change R6808 to 499K R6802 3A 3B
1 Q6806 WLED1 100R2J-2-GP 2A 2B
65 CARD_WLAN_OUT# R6814
R2
E R6808
3
3WLAN_LED# 1 2 WLANLED#_C B
R1
AFTP6801 1 1A 1B
C WLAN_LED_R 2 1WLAN_LED 1A K2 5
2 10KR2J-3-GP
65 CARD_WPAN_OUT# PDTA143ET-GP 330R2J-3-GP LED-W-27-GP ACES-CONN8G-GP
BAT54A-7-F-1-GP
84.00143.M11 83.01221.R70
SCD1U25V2KX-GP
1 AFTP6802
27 KBC_WLAN_OUT# 1R6807 2
2
0R2J-2-GP
EC6806
DY DY 20.K0464.004
1
11/26 if WLAN LED control by KBC.

remove D6801 and short R6814, R6807 X01-0217 Change R6814 to 0R 12/10 change PWRBT1 pin define
Place EC6806 near LED2 12/21 change PWRBT1 to 20.K0464.004
A00-0316 modify WLED1 circuit for brightness
<Core Design>
A A
Wistron Corporation
Title
LED Bard/Power Button

A3
5 4 3 2 1
5 4 3 2 1
SSID = KBC SSID = Touch.Pad X01-0216 Modify pin define error
D KB1 1 AFTP6901 D
31
1 KB_DET# KB_DET# 21 TouchPad Connector
2 KROW7
3 KROW6
4 KROW4
5 KROW2
6 KROW5 5V_S0
7 KROW1
8 KROW3
9 KROW0
10 KCOL5
1
11 KCOL4 C6901
12 KCOL7 5V_S0 SCD1U10V2KX-5GP X01-0216 Modify pin define error
13 KCOL6 12/6 swap net for layout
2
14 KCOL8
15 KCOL3
2
1
16 KCOL1
17 KCOL2 AFTP6929 1 5V_S0
18 KCOL0 RN6903 AFTP6931 1 TPDATA
19 KCOL12 SRN10KJ-5-GP AFTP6930 1 TPCLK
20 KCOL16 20.K0464.004
21 KCOL15 ACES-CONN8G-GP
3
4
22 KCOL13 6
23 KCOL14 4A 4B
24 KCOL9 27 TPCLK 3A 3B
25 KCOL11 27 TPDATA 2A 2B
26 KCOL10 AFTP6927 1
C 27 CAP_LED_R 1A 1B C
28 5
29
1
30 DY DY TPAD1
32 C6904 C6903
SC33P50V2JN-3GP SC33P50V2JN-3GP
2
JAE-CON30-7-GP
X01-0216 exchange C6903& C6904 11/23 change TPAD1 to 20.K0320.004

20.K0565.030
X01-0208 change TPAD1 to 20.K0464.004
X01-0216 Modify pin define error
11/26 change KB1 to 20.K0597.030

12/8 Change KB1 to 20.K0565.030
CAP_LED_R 1 AFTP6957
GND 1 AFTP6972
B B
12/8 Add Cap LED control circuit
CAP LED CONTROL

5V_S5
Q6902
R2
R6905 E
1 2 Q6902_B
B
27 CAP_LED# R1
CAP_LED_Q CAP_LED_R
C 1 2
15KR2J-1-GP R6906 1KR2J-1-GP
PDTA143ET-GP
84.00143.M11
2nd = 84.02143.011
3rd = 84.00143.N11
R6907 DY100R2J-2-GP
1 2
A <Core Design> A
KCOL0 1 AFTP6918 Wistron Corporation

KROW7 1 AFTP6902 KCOL5 1 AFTP6910 KCOL12 1 AFTP6919 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
KROW6 1 AFTP6903 KCOL4 1 AFTP6911 KCOL16 1 AFTP6920 Taipei Hsien 221, Taiwan, R.O.C.
KROW4 1 AFTP6904 KCOL7 1 AFTP6912 KCOL15 1 AFTP6921
KROW2 1 AFTP6905 KCOL6 1 AFTP6913 KCOL13 1 AFTP6922 Title
KROW[0..7] 27
KROW5 AFTP6906 KCOL8 AFTP6914 KCOL14 AFTP6923
KROW1
1
1 AFTP6907 KCOL3
1
1 AFTP6915 KCOL9
1
1 AFTP6924 Key Board/Touch Pad
KROW3 1 AFTP6908 KCOL1 1 AFTP6916 KCOL11 1 AFTP6925 Size Document Number Rev
KCOL[0..16] 27
KROW0 AFTP6909 KCOL2 AFTP6917 KCOL10 AFTP6926 A3
1 1 1
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
DN15ATI Whistler
A A
Wistron Corporation
Title
Hall Sensor
A3
5 4 3 2 1
5 4 3 2 1
D D
11/18 remove RN7102, R7107 3D3V_S0
DB1
1
21,27 LPC_AD0 2
21,27 LPC_AD1 3
21,27 LPC_AD2 4
21,27 LPC_AD3 5
21,27 LPC_FRAME# 6
5,18,27,31,65,83 PLT_RST# 7 DB1
8
18 CLK_PCI_LPC 9
10
11
12
MLX-CON10-7-GP
20.D0183.110
C C
B B
DN15ATI Whistler
A A
Wistron Corporation
Title
Debug connector
A3
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
Wistron Corporation
Title
Reserved
A3
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
Wistron Corporation
Title
Reserved
A3
5 4 3 2 1
5 4 3 2 1
SSID = SDIO
3D3V_CARD_S0
CARD1
11 SD_VDD/MMC_VDD MS_DATA0 12 XD_D1/SD_D5/MS_D0 32

MS_DATA1 13 XD_D4/SD_D3/MS_D1 32
4 10 XD_D0/SD_CLK/MS_D2_R
MS_VCC MS_DATA2
MS_DATA3 7 XD_ALE/SD_D7/MS_D3 32
D 3D3V_CARD_S0 32 XD_WE#/SD_CD# 20 8 XD_RE#/MS_INS# 32 D

SD_CD MS_INS
32 XD_D4/SD_D3/MS_D1 3 SD_CD/DAT3/MMC_RSV MS_BS 15 XD_D6/MS_BS 32
MS_SCLK 5 XD_RDY/SD_WP/MS_CLK 32
XD_D0/SD_CLK/MS_D2_R 14
SC2D2U6D3V3KX-GP
SD_CLK/MMC_CLK
6
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
32 XD_D2/SD_CMD SD_CMD/MMC_CMD
C7404
C7405
GND 23
1
1
C7401
C7402
C7403
32 XD_CLE/SD_D0/MS_D7 18 SD_DAT0/MMC_DAT GND 24
DY DY DY 32 XD_CE#/SD_D1
32 XD_D5/SD_D2/MS_D5
19
1
SD_DAT1
21
2
2
SD_DAT2 SD_GND
32 XD_RDY/SD_WP/MS_CLK 22 SD_WP/SW MS_VSS 2
MS_VSS 16
NP1 NP1 SD_VSS/MMC_VSS1 9

NP2 NP2 SD_VSS/MMC_VSS2 17
CARD-PUSH-22P-GP
20.I0110.021
0810 Vendor Recommand

C C
XD_ALE/SD_D7/MS_D3
XD_D1/SD_D5/MS_D0
XD_CLE/SD_D0/MS_D7
XD_CE#/SD_D1
XD_D5/SD_D2/MS_D5
XD_D4/SD_D3/MS_D1
XD_D2/SD_CMD
XD_D0/SD_CLK/MS_D2_R
SC6D8P50V2CN-GP
XD_WE#/SD_CD#
SC4D7P50V2BN-GP
SC6D8P50V2CN-GP
SC6D8P50V2CN-GP
SC6D8P50V2CN-GP
SC6D8P50V2CN-GP
SC6D8P50V2CN-GP
SC6D8P50V2CN-GP
XD_RDY/SD_WP/MS_CLK
EC7410
SC6D8P50V2CN-GP
EC7401
EC7402
EC7403
EC7404
EC7405
EC7406
EC7407
EC7408
EC7409
SC6D8P50V2CN-GP
1
1
2
2
For EMI
11/18 Dummy EC7401, EC7403

11/20 vendor recommand to reserve 5P
B B
X01-0216 stuff EC7401~EC7410 for EMI
32 XD_D0/SD_CLK/MS_D2 R7407 2 1 33R2J-2-GP XD_D0/SD_CLK/MS_D2_R
For EMI
A <Core Design> A
Wistron Corporation
Title
SD/XD/MS/MMC Card CONN

A3
5 4 3 2 1
5 4 3 2 1
SSID = ExpressCard
D D
C C
B B
<Core Design>
A A
Wistron Corporation
Title
Express Card
A3
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
Wistron Corporation
Title
Reserved
A3
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
Wistron Corporation
Title
Reserved
A3
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
Wistron Corporation
Title
Reserved
A3
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
Wistron Corporation
Title
Free Fall Sensor

A3
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
Wistron Corporation
Title
Reserved
A3
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
Wistron Corporation
Title
Reserved
A3
5 4 3 2 1
5 4 3 2 1
11/10 modify B2B CONN and pin define

IOBD1 is for USB board
11/1 Stuff TR8201, TR8202 for EMI USB20_VCCB
X01-0214 add AFTP8201~8210
IOBD1
17
D D
USB_PP9_R 1 2 USB_PP9 18 1
WCM2012F2S-GP-U2 X02-0309 Del AFTP8201~8210
TR8202 2
USB_PN9_R 4 3 USB_PN9 18 3
4
5
6
USB_PN9_R 7
USB_PP9_R 8
9
USB_PN8_R 10
USB_PP8_R 11
A00-0406 remove R8201, R8202, R8203, R8204 pad 12
13
A00-0320 Change TR8201, TR8202 to 120ohm. 14
15
A00-0408 Swap net for layout 16
12/6 swap net for layout 18
PTWO-CON16-1-GP
20.K0429.016
USB_PP8_R 1 2 USB_PP8 18
C C
WCM2012F2S-GP-U2
USB_PN8_R 4 3TR8201 USB_PN8 18
IOBD2 is for Audio board
IOBD2 X02-0309 Del AFTP8201~8210

17
29,58 INT_MIC_L_R 1
2
29 AUD_HP1_JACK_L2 3
29 AUD_HP1_JACK_R2 4
5
29 MIC_IN_L 6
29 MIC_IN_R 7
8
11/1 Add EC2901~EC2904 for EMI request 29 EXT_MIC_JD# 9
29 AUD_HP1_JD# 10
11
MIC_IN_L 1 2 12
B SC10P50V2JN-4GP 27 LID_CLOSE# B
MIC_IN_R
DY EC8201 13
1 2 3D3V_S5 14
SC10P50V2JN-4GP DY EC8202 15
AUD_HP1_JACK_L2 1 2 16
SC10P50V2JN-4GP DY EC8203
AUD_HP1_JACK_R2 1 2 18
SC10P50V2JN-4GP DY EC8204 AUD_AGND PTWO-CON16-1-GP
20.K0429.016
12/10 Change pin defien for audio board 12/14 Change IOBD2 to 20.K0429.016 and
routing smooth. change pin define.
A <Core Design> A
Wistron Corporation
Title

IO Board Connector Rev
5 4 3 2 1
5 4 3 2 1
CONFIGURATION STRAPS RECOMMENDED SETTINGS

SSID = VIDEO VGA1A 1 OF 7
ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE GPIOS ARE USED,
0= DO NOT INSTALL RESISTOR
1 = INSTALL 3K RESISTOR
X = DESIGN DEPENDANT
THEY MUST NOT CONFLICT DURING RESET NA = NOT APPLICABLE
PLATFORM
STRAPS PIN DESCRIPTION OF DEFAULT SETTINGS RECOMMEND
PEG_TXP0 AH30 PEG_C_RXP0 C8306 2 SCD1U10V2KX-5GP
SETTING
4 PEG_TXP0
PEG_TXN0
AF30 PCIE_RX0P PCIE_TX0P DIS
1 PEG_RXP0 4
4 PEG_TXN0 AE31 PCIE_RX0N PCIE_TX0N AG31 PEG_C_RXN0 C8305 DIS
1 2 SCD1U10V2KX-5GP PEG_RXN0 4 Transmitter Power Savings Enable
TX_PWRS_ENB GPIO0 0: 50% Tx output swing 1: Full Tx output swing X 1
D 4 PEG_TXP1 PEG_TXP1 AE29 AG29 PEG_C_RXP1 C8303 DIS
1 2 SCD1U10V2KX-5GP PCIE TRANSMITTER DE-EMPHASIS ENABLED D
PCIE_RX1P PCIE_TX1P PEG_RXP1 4
PEG_TXN1 AD28 AF28 PEG_C_RXN1 C8304 DIS
1 2 SCD1U10V2KX-5GP TX_DEEMPH_EN GPIO1 X 1
4 PEG_TXN1 PCIE_RX1N PCIE_TX1N PEG_RXN1 4 0:Tx de-emphasis disabled 1:Tx de-emphasis enabled
0:Advertises the PCIe device as 2.5GT/s capable at power on.
PEG_TXP2 AD30 AF27 PEG_C_RXP2 C8310 DIS
1 2 SCD1U10V2KX-5GP BIF_GEN2_EN_A GPIO2 0 0
4 PEG_TXP2
PEG_TXN2 PCIE_RX2P PCIE_TX2P PEG_RXP2 4 1:Advertises the PCIe device as 5.0GT/s capable at power on.
4 PEG_TXN2 AC31 PCIE_RX2N PCIE_TX2N AF26 PEG_C_RXN2 C8309 DIS
1 2 SCD1U10V2KX-5GP PEG_RXN2 4
optional input allow the system to request a fast
PEG_TXP3
GPIO5_AC_BATT GPIO5 power reduction by setting GPIO5 to low. ? 0
4 PEG_TXP3 AC29 PCIE_RX3P PCIE_TX3P AD27 PEG_C_RXP3 C8308 DIS
1 2 SCD1U10V2KX-5GP PEG_RXP3 4
4 PEG_TXN3 PEG_TXN3 AB28 AD26 PEG_C_RXN3 C8307 DIS
1 2 SCD1U10V2KX-5GP
PCIE_RX3N PCIE_TX3N PEG_RXN3 4
GPIO8_ROMSO GPIO8 RESERVED 0 0
4 PEG_TXP4 PEG_TXP4 AB30 AC25 PEG_C_RXP4 C8315 DIS
1 2 SCD1U10V2KX-5GP 0:VGA Controller capacity enabled
PCI EXPRESS INTERFACE

PEG_TXN4 AA31 AB25 PEG_C_RXN4 C8316 DIS
1 2 SCD1U10V2KX-5GP VGA_DIS GPIO9 0 0
4 PEG_TXN4 PCIE_RX4N PCIE_TX4N PEG_RXN4 4 1:The device won't be recognized as the system's VGA controller
BIOS_ROM_EN=1, Config[2:0] defines the ROM type 0 0 1
4 PEG_TXP5 PEG_TXP5 AA29 Y23 PEG_C_RXP5 C8318 DIS
1 2 SCD1U10V2KX-5GP ROMIDCFG[2:0] GPIO[13:11] BIOS_ROM_EN=0, Config[2:0] defines the primary memory aperture size X X X
PEG_TXN5 PCIE_RX5P PCIE_TX5P
Y24 PEG_C_RXN5 C8317 2 SCD1U10V2KX-5GP
PEG_RXP5 4 (256MB)
4 PEG_TXN5 Y28 PCIE_RX5N PCIE_TX5N DIS
1 PEG_RXN5 4
GPIO21_BB_EN GPIO21 RESERVED 0 0

4 PEG_TXP6 PEG_TXP6 Y30 AB27 PEG_C_RXP6 C8314 DIS
1 2 SCD1U10V2KX-5GP
4 PEG_TXN6 PEG_TXN6 W31 AB26 PEG_C_RXN6 C8313 DIS
1 2 SCD1U10V2KX-5GP 0:Disable external BIOS ROM device
PCIE_RX6N PCIE_TX6N PEG_RXN6 4
BIOS_ROM_EN GPIO_22_ROMCSB X 0
1:Enable external BIOS ROM device
4 PEG_TXP7 PEG_TXP7 W29 Y27 PEG_C_RXP7 C8319 DIS
1 2 SCD1U10V2KX-5GP VIP Device Strap Enable indicates to the software driver that it sense
PEG_TXN7 V28 Y26 PEG_C_RXN7 C8320 DIS
1 2 SCD1U10V2KX-5GP VIP_DEVICE_STRAP_EN V2SYNC X 0
4 PEG_TXN7 PCIE_RX7N PCIE_TX7N PEG_RXN7 4 whether or not a VIP device is connected on the VIP Host interface.
C
V30 PCIE_RX8P PCIE_TX8P W24 RSVD H2SYNC RESERVED 0 0 C
U31 PCIE_RX8N PCIE_TX8N W23
RSVD GENERICC RESERVED 0 0

U29 PCIE_RX9P PCIE_TX9P V27
T28 PCIE_RX9N PCIE_TX9N U26
AUD[1] HSYNC X 1
AUD[1:0]:11-Audio for both DisplayPort and HDMI
T30 PCIE_RX10P PCIE_TX10P U24
R31 PCIE_RX10N PCIE_TX10N U23 AUD[0] VSYNC X 1
R29 PCIE_RX11P PCIE_TX11P T26 2010/06/11

P28 PCIE_RX11N PCIE_TX11N T27
P30 T24 3D3V_VGA_S0 3D3V_VGA_S0

PCIE_RX12P PCIE_TX12P
N31 T23 2010/06/11
PCIE_RX12N PCIE_TX12N
Need to check
PIN STRAPS
A00-0322 R8325
2 10KR2J-3-GP
N29
M28
PCIE_RX13P VGA1 PCIE_TX13P P27
P26
Dummy R8302 for disable de-emphasis 85 JTAG_TMS_VGA 1
DY
PCIE_RX13N PCIE_TX13N R8301 1 DIS 3KR2J-2-GP R8328
85 TX_PWRS_ENB 2
1 10KR2J-3-GP
M30 P24 85 TX_DEEMPH_EN R8302 1 DY 2 3KR2J-2-GP
2
DY
PCIE_RX14P PCIE_TX14P 2010/07/13 Stuff for 5.0GT/S
L31 PCIE_RX14N PCIE_TX14N P23 84 TESTEN
85 BIF_GEN2_EN_A R8303 1 DIS 2 10KR2J-3-GP R8327
1DIS 2 5K11R2F-L1-GP
L29 M27 85 GPIO8_ROMSO R8304 1 DY 2 10KR2J-3-GP
PCIE_RX15P PCIE_TX15P
K30 PCIE_RX15N PCIE_TX15N N26
B R8305 B
DY 2 10KR2J-3-GP R8326 1 2 10KR2J-3-GP
85 VGA_DIS 1 85 JTAG_TRST#_VGA DY
11/18 Add R8311, R8312 and dummy 20,85 JTAG_TCK_VGA
R8329 1 2 10KR2J-3-GP
CLOCK
R8319, R8310 to follow DN13 85 CONFIG0 R8306 1 DIS 2 10KR2J-3-GP DY
20 CLK_PCIE_VGA AK30 PCIE_REFCLKP
AK32 85 CONFIG1 R8307 1 DY 2 10KR2J-3-GP
20 CLK_PCIE_VGA# PCIE_REFCLKN
1V_VGA_S0 85 CONFIG2 R8308 1 DY 2 10KR2J-3-GP
CALIBRATION
PCIE_CALRP Y22 PCIE_CALRP 1 DIS 2 50,85 VGA_CRT_VSYNC
R8309 1 DY 2 10KR2J-3-GP
R8321 1K27R2F-L-GP
1DIS PWRGOOD AA22 PCIE_CALRN R8310 2 10KR2J-3-GP
JTAG SIGNAL OPTION
2 N10 PWRGOOD PCIE_CALRN 1 DIS 2 50,85 VGA_CRT_HSYNC 1 DY
R8314 10KR2F-2-GP R8315 2KR2F-3-GP Normal Debug pilot run
Signal mode mode mode
ATI_RST# 2 R8316 1VGA_RST# AL27
0R0402-PAD PERST# R8311
85 VSYNC_DAC2 1 DY 2 10KR2J-3-GP
1
TESTEN "1"(PU) "1"(PU) "0"(PD)

C8312 Seymour-S3-XT R8312 2 10KR2J-3-GP
DY SC47P50V2JN-3GP P/N: FJPJP 11/18 Del R8322 and dummy
85 HSYNC_DAC2 1 DY
2
R8324, U8301, U8302 85 BIOS_ROM_EN R8313 1 DY 2 10KR2J-3-GP JTAG_TRST# "0"(PD) "1"(PU) NC

85 GPIO5_AC_BATT R8318 1 DY 2 10KR2J-3-GP
JTAG_TCK CLK "1"(PU) NC
11/2 change to 1D5V_VGA_PWOK X02-0311 Change R8316, R8331 to short pad 85 GPIO21_BB_EN R8317 1 DY 2 10KR2J-3-GP
PLT_RST# 2 1R8323 ATI_RST#
DY 0R2J-2-GP
18 DGPU_HOLD_RST# 2 R8331 1 JTAG_TMS "1"(PU) "1"(PU) NC
86 1D5V_VGA_PWOK 2 DY 1R8330 0R0402-PAD
0R2J-2-GP
U8301 3D3V_VGA_S0 3D3V_VGA_S0
A <Core Design> A
93 1D8V_S0_VGA_PG 2 DY 1R8324 1D8V_S0_VGA_PG_R 1
B
U8302
0R2J-2-GP 5 1
VCC B
1
C8311 2 ADY VCC 5

Wistron Corporation
DY SCD1U10V2KX-4GP
Y 4 U8301_Y 2 DY
A PE_GPIO0
3 4 ATI_RST# 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
ATI_RST# 85
2
GND Y
3 GND dGPU mode H Taipei Hsien 221, Taiwan, R.O.C.
74LVC1G08GW-1-GP
73.01G08.L04 74LVC1G08GW-1-GP IGPU L Title
73.01G08.L04
5,18,27,31,65,71 PLT_RST# 2ND =
2ND =
GPU_PCIE/STRAPPING(1/5)
IGPU with BACO H Size Document Number Rev
A3
5 4 3 2 1
5 4 3 2 1
SSID = VIDEO 88 MDA[0..31]

VGA1C 3 OF 7
MDA0 K27 K17 MAA0 88,89

MDA1 DQA_0 MAA_0
J29 DQA_1 MAA_1 J20 MAA1 88,89
MDA2 H30 H23 MAA2 88,89
MDA3 DQA_2 MAA_2
H32 DQA_3 MAA_3 G23 MAA3 88,89
MDA4 G29 G24
DQA_4 MAA_4 MAA4 88,89
MDA5 F28 H24 MAA5 88,89
MEMORY INTERFACE
MDA6 DQA_5 MAA_5
F32 DQA_6 MAA_6 J19 MAA6 88,89
MDA7 F30 K19 MAA7 88,89
MDA8 DQA_7 MAA_7
C30 DQA_8 MAA_8 J14 MAA8 88,89
MDA9 F27 K14 MAA9 88,89
MDA10 DQA_9 MAA_9
D A28 DQA_10 MAA_10 J11 MAA10 88,89 D
MDA11 C28 J13 MAA11 88,89
MDA12 DQA_11 MAA_11
E27 DQA_12 MAA_12 H11 MAA12 88,89
MDA13 G26 G20 MAA13 88,89
MDA14 DQA_13 MAA_13
D26 DQA_14 MAA_14/BA0 J16 A_BA0 88,89
PLACE MVREF DIVIDERS AND CAPS CLOSE TO ASIC MDA15 F25 L15 A_BA1 88,89
MDA16 DQA_15 MAA_15/BA1
A25 DQA_16 MAA_BA2 G11 A_BA2 88,89
MDA17 C25
MDA18 DQA_17
E25 DQA_18 DQMA_0 E32 DQMA0 88
MDA19 D24 E30
1D5V_VGA_S0 1D5V_VGA_S0 DQA_19 DQMA_1 DQMA1 88
MDA20 E23 A21 DQMA2 88
MDA21 DQA_20 DQMA_2
F23 DQA_21 DQMA_3 C21 DQMA3 88
MDA22 D22 E13 DQMA4 89
DQA_22 DQMA_4
1
1
Ra R8410 Ra R8411 MDA23 F21 D12 DQMA5 89
40D2R2F-GP 40D2R2F-GP MDA24 DQA_23 DQMA_5
E21 DQA_24 DQMA_6 E3 DQMA6 89
DIS DIS MDA25 D20 F4 DQMA7 89
MDA26 DQA_25 DQMA_7
F19 DQA_26
MDA27 A19 H28 QSAP_0 88
2
2
MVREFDA MVREFSA MDA28 DQA_27 RDQSA_0
D18 DQA_28 RDQSA_1 C27 QSAP_1 88
MDA29 F17 A23
DQA_29 RDQSA_2 QSAP_2 88
1
1
Rb R8414 C8402 Rb R8415 C8403 MDA30 A17 DQA_30 RDQSA_3 E19 QSAP_3 88
100R2F-L1-GP-U SCD1U10V2KX-5GP 100R2F-L1-GP-U SCD1U10V2KX-5GP MDA31 C17 E15 QSAP_4 89
89 MDA[32..63] DQA_31 RDQSA_4
DIS DIS DIS DIS MDA32 E17 D10 QSAP_5 89
2
2
MDA33 DQA_32 RDQSA_5
D16 DQA_33 RDQSA_6 D6 QSAP_6 89
MDA34 F15 G5 QSAP_7 89
2
MDA35 DQA_34 RDQSA_7

A15 DQA_35
MDA36 D14 H27 QSAN_0 88
MDA37 DQA_36 WDQSA_0
F13 A27
DDR3/GDDR3 Memory Stuff Option (ROBSON-S3/SEYMOUR-XT-S3) MDA38 A13
DQA_37
DQA_38
WDQSA_1
WDQSA_2 C23
QSAN_1
QSAN_2
88
88
MDA39 C13 C19
DQA_39 WDQSA_3 QSAN_3 88
MDA40 E11 C15 QSAN_4 89
DDR5 DDR3 A11 DQA_41 WDQSA_5 E9 QSAN_5 89
MDA42 C11 C5 QSAN_6 89
F11 DQA_43 WDQSA_7 H4 QSAN_7 89
MVDDQ 1.5V 1.5V/1.8V MDA44 A9
MDA45 DQA_44
C9 DQA_45 ODTA0 L18 ODTA0 88
C MDA46 C
F9 DQA_46 ODTA1 K16 ODTA1 89
Ra 40.2R 40.2R MDA47 D8
MDA48 E7
DQA_47 VGA1 H26
MDA49 DQA_48 CLKA0 CLKA0 88
A7 DQA_49 CLKA0# H25
CLKA0# 88
Rb 100R 100R MDA50 C7 DQA_50
MDA51 F7 G9
MDA52 DQA_51 CLKA1 CLKA1 89
A5 DQA_52 CLKA1# H9 CLKA1# 89
MDA53 E5
MDA54 DQA_53
C3 DQA_54 RASA0# G22
MDA55 RASA0# 88
E1 DQA_55 RASA1# G17 RASA1# 89
MDA56 G7
MDA57 DQA_56
G6 DQA_57 CASA0# G19 CASA0# 88
MDA58 G1 G16
DQA_58 CASA1# CASA1# 89
DPC_CALR (Park/Robson-S3): MDA59 G3 DQA_59
 (1%)
1D5V_VGA_S0 MDA60 J6 H22
Analog calibration. MDA61 J1
DQA_60 CSA0#_0
J22
CSA0#_0 88
Connect DPxx_CALR to GND through a 150- MDA62 DQA_61 CSA0#_1
J3 DQA_62
resistor. MDA63 J5 G13
150R2F-1-GP DQA_63 CSA1#_0 CSA1#_0 89
CSA1#_1 K13
R8403 1 DIS 2 243R2F-2-GP MEM_CALRN0 R8407 1 DIS 2 MVREFDA K26
MEM_CALRP0 MVREFSA MVREFDA
1 2 J26 K20
R8408 DIS 243R2F-2-GP MVREFSA CKEA0
J17
CKEA0 88
MEM_CALRN0 J25 CKEA1 CKEA1 89
TESTEN MEM_CALRN0
83 TESTEN K7 TESTEN WEA0# G25
WEA0# 88
WEA1# H10 WEA1# 89
R_MEM_2 R_MEM_1 MEM_CALRP1/DPC_CALR J8
MEM_CALRP0 MEM_CALRP1/DPC_CALR PX_EN_R
K25 MEM_CALRP0 PX_EN AB16 1R8440 2 PX_EN 86
R8405 R8402 0R0402-PAD
1 DIS 2 DRAM_RST_1 1 DIS 2 DRAM_RST L10
88,89 MEM_RST DRAM_RST
2
11/16 change part reference
51R2J-2-GP 10R2J-2-GP TPAD14 TP8401 1CLKTESTA K8 G14 R8441
CLKTESTA RSVD#G14 to R8441 and stuff
** This basic topology should be used for DRAM_RST for TPAD14 TP8402 1CLKTESTB L7 CLKTESTB DIS 10KR2J-3-GP
2
DDR3/GDDR3/GDDR5.These Capacitors and Resistor values C8401

are an example only. The Series R and || Cap values SC120P50V2JN-1GP DIS R8409 11/18 move R8441 before R8440
1
will depend on the DRAM load and will have to be 5K1R2F-2-GP DIS Seymour-S3-XT
1
B
calculated for different Memory ,DRAM Load and board C_MEM R_MEM_3 B
2
to pass Reset Signal Spec.

P/N: FJPJP
2010/07/06
Schematics check list:
Designator For SEYMOUR For Robson Place all these components very close to GPU A pull-down resistor is required.
C8407
(Within 25mm) and keep all component close SCD1U10V2KX-5GP
to each Other (within 5mm) except R_MEM_2 CLKTESTA_C 1 2 CLKTESTA
R_MEM_1 10R 10R DY C8406
SCD1U10V2KX-5GP
R_MEM_2 50R 50R CLKTESTB_C 1 2CLKTESTB
DY
1
R_MEM_3 5K 5K
R8419 DY DY
51R2J-2-GP R8418
C_MEM 120pF 120pF 51R2J-2-GP
2
For normal GPU operation, these signals can be left

floating (do not populate the capacitors and resistors).
A A
DN15ATI Whistler
Wistron Corporation
Title
GPU Memory(2/5)
Custom
5 4 3 2 1
5 4 3 2 1
MEMORY ID Table SSID = VIDEO

DVPDATA[3:0] Description VGA1B 2 OF 7 LVDS Interface
VGA1F 6 OF 7
0000 DDR3 SAMSUNG-K4W1G1646G-BC11(900MHz)64M*16
M93-S3/M92-S2 TXCAP_DPA3P
AF2
AE9 AF4
DVCNTL_0/DVPDATA_18 TXCAM_DPA3N
0001 DDR3 Hynix-H5TQ1G63DFR-11C (900MHz) 64M*16 L9
DVCNTL_1/NC#L9
N9 AG3 LVDS CONTROL AB11
DVCNTL_2/TESTEN#2 TX0P_DPA2P VARY_BL
AE8
DVDATA_12/DVPDATA_16 DPA TX0M_DPA2N
AG5
DIGON
AB12
0010 DDR3 SAMSUNG K4W2G1646C-HC11 (900MHz) 128M*16 AD9
DVDATA_11/DVPDATA_20
AC10 AH3
DVDATA_10/DVPDATA_22 TX1P_DPA1P
AD7 AH1
DVDATA_9/DVPDATA_12 TX1M_DPA1N
0011 DDR3 Hynix-H5TQ2G63BFR-11C (900MHz) 128M*16 1D8V_VGA_S0 0923 Modify for DV14 Config AC8
DVDATA_8/DVPDATA_14
AC7 AK3 AH20
DVDATA_7/DVPCNTL_0 TX2P_DPA0P TXCLK_UP_DPF3P
AB9 AK1 AJ19
DVDATA_6/DVPDATA_8 TX2M_DPA0N TXCLK_UN_DPF3N
DVPDATA[0:3] Default:Pull down AB8
DVDATA_5/DVPDATA_6
D AB7 AK5 AL21 D
R8527 1 DY MEM_ID3 DVDATA_4DVPDATA_4 TXCBP_DPB3P TXOUT_U0P_DPF2P
2 10KR2J-3-GP AB4 AM3 AK20
MEM_ID2 DVDATA_3/DVPDATA_19 TXCBM_DPB3N TXOUT_U0N_DPF2N
For Seymour, R8522 1 DY 2 10KR2J-3-GP AB2
DVDATA_2/DVPDATA_21
DPC_PVDD is DPC_VDD18 2010/06/11 R8519 11GVRAM2 10KR2J-3-GP MEM_ID1 Y8
DVDATA_1/DVPDATA_2 TX3P_DPB2P
AK6
TXOUT_U1P_DPF1P
AH22
R8518 1 Hynix 2 10KR2J-3-GP MEM_ID0 Y7 AM5 AJ21
DPC_PVSS and all DPC_VSSR are DP_VSSR DVDATA_0/DVPDATA_0 TX3M_DPB2N TXOUT_U1N_DPF1N
DPB
AJ7 AL23
TX4P_DPB1P TXOUT_U2P_DPF0P
MEM_ID Control DVO TX4M_DPB1N
AH6
TXOUT_U2N_DPF0N
AK22
2010/07/15 Modify: AK8 AK24

THERMTRIP_R
Q8501 change to dual 2n7002. DPB_VDD18 TX5P_DPB0P TXOUT_U3P

AL7 AJ23
Add R8512,R8521,C8529 for Q8501 pin2 TX5M_DPB0N TXOUT_U3N
turn on timming control. THERMTRIP_VGA 2010/06/11 M93-S3/M92-S2
1
LVTMDP
R8526
W6
DPC_PVDD/DVPDATA_11 VGA1
V6
DPC_PVSS/GND M92-S2/M93-S3
10KR2J-3-GPDY 1V_VGA_S0 V4 AL15
DVPDATA_3/TXCCP_DPC3P TXCLK_LP_DPE3P
AC6 U5 AK14
DPC_VDD18#1/DVPDAT10 DVPCNTL_2/TXCCM_DPC3N TXCLK_LN_DPE3N
AC5
2
6
DPC_VDD18#2/DVPDAT23
W3 AH16
Q8501 L8507 DIS DVPDATA_7/TX0P_DPC2P TXOUT_L0P_DPE2P
DY (1.0V@110mA DPC_VDD10) AA5
DPC_VDD10#1/DVPDAT15 DVPDATA_1/TX0M_DPC2N
V2
TXOUT_L0N_DPE2N
AJ15
2N7002KDW-GP 1 2 DPC_VDD10 AA6
BLM15BD121SS1D-GP DPC_VDD10#2/DVPDAT17
Y4 AL17
84.2N702.A3F DVPCNTL_MV1/TX1P_DPC1P TXOUT_L1P_DPE1P
C8526
C8527
C8528
W5 AK16
SC1U6D3V2KX-GP
SC10U6D3V5KX-1GP
SCD1U10V2KX-5GP
1
2nd = DVPDATA_9/TX1M_DPC1N TXOUT_L1N_DPE1N
1
U1 AA3 AH18
DPC_VSSR#1/DVPCLK DVPDATA_13/TX2P_DPC0P TXOUT_L2P_DPE0P
W1 Y2 AJ17
DPC_VSSR#2/DVPDAT5 DVPCNTL_1/TX2M_DPC0N TXOUT_L2N_DPE0N
DIS DIS DIS
Q5801_2
U3
2
DPC_VSSR#3/GND
5,22,36 H_THERMTRIP# Y6 AA12 AL19
R8525 DPC_VSSR#4/GND NC#AA12 TXOUT_L3P
AA1 AK18
DPC_VSSR#5/DVPCNTL_MV0 TXOUT_L3N
2 DY 1
SCD1U10V2KX-5GP
83 ATI_RST#
C8529
1
0R2J-2-GP DPC
2010/07/07 Remove TP8517,TP8518,TP8506,TP8519,TP8512
DY Seymour-S3-XT
2
Vendor suggest to TPAD14 TP8507 1 GPU_SCL R1

SCL
P/N: FJPJP
X01: dummy VGA thermal circuit base on DN15 reserve test point TPAD14 TP8513 1 GPU_SDA R3
SDA
I2C
3D3V_VGA_S0 11/18 Del C8529 to follow DN13 09/06 R
AM26 CRT_GFX_R 50
GENERAL PURPOSE I/O AK26
R#
83 TX_PWRS_ENB U6
GPIO_0 1D8V_VGA_S0
C
83 TX_DEEMPH_EN U10 AL25 CRT_GFX_G 50 C
1
GPIO_1 G
83 BIF_GEN2_EN_A T10 AJ25
GPIO_VGA_03_DATA GPIO_2 G#
DIS R8503 SMBUS U8
GPIO_3_SMBDATA
AVDD
10KR2J-3-GP GPIO_VGA_04_CLK U7 AH24
GPIO_4_SMBCLK B CRT_GFX_B 50
83 GPIO5_AC_BATT T9 AG25 L8502 DIS (1.8V@65mA AVDD)
GPIO_5_AC_BATT B#
TPAD14 TP8505 1 GPIO6_VGA T8 DAC1 1 2
2
VGA_BLEN GPIO_6 BLM15BD121SS1D-GP

T7 AH26 VGA_CRT_HSYNC 50,83
GPIO17_VGA GPIO_7_BLON HSYNC
83 GPIO8_ROMSO P10 AJ27 VGA_CRT_VSYNC 50,83
5
6
7
8
1
GPIO_8_ROMSO VSYNC C8501 C8503 C8504
P4
SC1U6D3V2KX-GP
SCD1U10V2KX-5GP
SC4D7U6D3V3KX-GP
83 VGA_DIS GPIO_9_ROMSI
P2 DIS RN8502 DIS DIS DIS
GPIO_10_ROMSCK GPU_RSET
83 CONFIG0 N6 AD22 1 2 SRN150F-1-GP
DIS_CRT
2
GPIO_11 RSET R8514 499R2F-2-GP
83 CONFIG1 N5
GPIO_12 AVDD
83 CONFIG2 N3 AG24
GPIO_13 AVDD VDD1DI
Y9 AE22 AVSSQ
4
3
2
1
GPIO_6,GPIO_15_PWRCNTL_0,GPIO_16_SSIN,GPIO_20_PWRCNTL_1: GPIO_14_HPD2 AVSSQ AVSSQ
92 PWRCNTL_0 N1
Voltage control signals for the core (VDDC and VDDCI). TPAD14-GP TP8502 GPIO16_SSIN GPIO_15_PWRCNTL_0
At Reset, these signals will be inputs with weak internal pull-down resistors.
1
GPIO17_VGA
M4
R6
GPIO_16_SSIN VDD1DI
AE23
AD23
Modified 9/1
VBIOS can define all voltage control signals to be either 3.3-V or open drain outputs (all signals TPAD14-GP TP8506 GPIO18_VGA GPIO_17_THERMAL_INT VSS1DI AVSSQ
1 W10
must be the same type). The output state (high/low) of these signals is programmable for each PowerPlay state. THERMTRIP_VGA GPIO_18_HPD3
M2
GPIO_19_CTF M92-S2/M93-S3
P8 AM12 VDD1DI
92 PWRCNTL_1 GPIO_20_PWRCNTL_1 R2/NC#AM12
83 GPIO21_BB_EN P7 AK12
GPIO_21_BB_EN R2#/NC#AK12 L8503 DIS
83 BIOS_ROM_EN N8
GPIO_22_ROMCSB (1.8V@100mA VDD1DI)
20 PEG_CLKREQ# N7 AL11 1 2
GPIO_23_CLKREQB G2/NC#AL11
G2#/NC#AJ11
AJ11 12/20 NC R-,G-,B- on SSI and try to BLM15BD121SS1D-GP
R8517
co-layout with Rosbson in PT stage
1
AK10 2 1 C8502 C8506 C8507
SC1U6D3V2KX-GP
SCD1U10V2KX-5GP
SC4D7U6D3V3KX-GP
B2/NC#AK10 0R0402-PAD
R8520 1 PWRCNTL_0
83 JTAG_TRST#_VGA
JTAG_TDI
L6
JTAG_TRST# B2#/NC#AL9
AL9 DIS DIS DIS
DY 23KR2J-2-GP TPAD14 TP8510 1 L5
2
JTAG_TDI
20,83 JTAG_TCK_VGA L3
R8521 1 PWRCNTL_1 JTAG_TCK
DY 23KR2J-2-GP 83 JTAG_TMS_VGA L1 AH12 AVSSQ
JTAG_TMS C/NC#AH12
2010/07/07 TPAD14 TP8503 1 JTAG_TDO_VGA K4
JTAG_TDO
DAC2 Y/NC#AM10
AM10
TPAD14 TP8511 1 RSVD AF24 AJ9
Change to RSVD based RSVD#AF24 COMP/NC#AJ9 VDD2DI
R8523 1 DY 210KR2J-3-GP VGA_BLEN on DS v3.05 TPAD14 TP8504 1 GEN_A AB13
GEN_B GENERICA
1D8V_VGA_S0 TPAD14 TP8508 1 W8
GENERICB H2SYNC
AL13 HSYNC_DAC2 83 12/20 Add R8504 for Robson.
W9 AJ13 VSYNC_DAC2 83
GENERICC V2SYNC
12/17 dummy R8523 for panel interface unused. W7
VGA1
1
TPAD14 TP8509 GENERICE_HPD4 AD10 GENERICD A2VDD VDD2DI

PLACE VREFG DIVIDER AND CAP 1
GENERICE_HPD4
R8515 AD19
CLOSE TO ASIC VDD2DI/NC#AD19 AC19_GND
DIS 499R2F-2-GP AC14 AC19 1R8504 2 0R2J-2-GP A2VDDQ R8507 ROB (1.8V@100mA VDD2DI)
HPD1 VSS2DI/NC#AC19
B
ROB 1 2
B
1D8V_VGA_S0 DPLL_PVDD
2
(1.8V@75mA DPLL_PVDD) GPU_VREFG AE20 0R2J-2-GP
1
L8501 A2VDD/NC#AE20 C8508 C8509
1
1 DIS 2 R8516 C8514 AE17 DY DY

1
BLM18PG471SN1D-GP 249R2F-GP SCD1U10V2KX-5GP A2VDDQ/NC#AE17 SCD1U10V2KX-5GP SC1U6D3V2KX-GP

AC16
2
1
VREFG
C8515 C8516 DIS DIS AE19 12/9 chnage R8501 to ROB
SC1U6D3V2KX-GP
SCD1U10V2KX-5GP
1
C8505 A2VSSQ
DIS DIS DIS
2
SC4D7U6D3V3KX-GP R8501
2
AG13 R2SET 1ROB 2

2
R2SET/NC#AG13
715R2F-GP
M92-S2/M93-S3 M92-S2/M93-S3 0820
AE6 CRT_GFX_DDCCLK 50
PLL/CLOCK DDC1CLK
AE5 CRT_GFX_DDCDAT 50
DDC1DATA A2VDDQ
AF14
DPLL_PVDD
AE14 AD2
1V_VGA_S0 DPLL_VDDC DPLL_PVSS AUX1P L8505
AUX1N
AD4 ROB (1.8V@2mA A2VDDQ)
(1.0V@125mA DPLL_VDDC) DDC/AUX
DIS 1 2
1 2 AD14 AC11
L8506 BLM18PG471SN1D-GP DPLL_VDDC DDC2CLK BLM15BD121SS1D-GP
AC13
SC1U6D3V2KX-GP
SCD1U10V2KX-5GP
SC1U6D3V2KX-GP
1
1
DDC2DATA
11/18 Del 27M CLK circuit from PCH 12/16 change R8507, R8505 and R8513 to ROB C8510 C8511
1
XTALIN AM28 AD13 0723 Add SMBUS DY DY

XTALOUT XTALIN AUX2P
C8518
C8519
C8517 DY DIS DIS AK28 AD11 SCD1U10V2KX-5GP
2
SC4D7U6D3V3KX-GP XTALOUT AUX2N
2
DDCCLK_AUX5P
AE16 AUXP PD 100K
AD16
R8510 1 20R2J-2-GP NC#AC22/XO_IN DDCDATA_AUX5N AUXN PU 100K
DY AC22
NC#AC22/XO_IN
R8511 1 DY 20R2J-2-GP NC#AB22/XO_IN2 AB22
NC#AB22/XO_IN2 DDC6CLK
AC1 Draw on EDP circuit page
AC3
DDC6DATA
28 P2800_VGA_DXP Change to DY AD20 3D3V_VGA_S0
1
NC#AD20/DDCCLK_AUX3P
DY 9/20 THERMAL NC#AC20/DDCDATA_AUX3N
AC20 3D3V_VGA_S0 A2VDD
C8523
SC2200P50V2KX-2GP T4 R8513 ROB (3.3V@130mA A2VDD)
2
DPLUS
28 P2800_VGA_DXN T2 1 2
DMINUS
2010/07/06 1D8V_VGA_S0 TSVDD 4 0R2J-2-GP
3
1
Schematics check list: L8504 DIS TPAD14 TP8512 1 FAN_PWM_C R5 C8512 C8513
SC1U6D3V2KX-GP
TS_FDO RN8501 SCD1U10V2KX-5GP
A 1-M ohm resistor must be connected 1 2 (1.8V@20mA TSVDD) AD17
TSVDD DY DY
BLM15BD121SS1D-GP AC17 SRN4K7J-8-GP DIS
2
between XTALIN and XTALOUT when a crystal is used. C8521 C8522 TSVSS
1
A A
DIS DIS Seymour-S3-XT
C8520 DY SC1U6D3V2KX-GP SCD1U10V2KX-5GP DIS
Q8503
1
2
SC4D7U6D3V3KX-GP
P/N: FJPJP
2
GPIO_VGA_04_CLK 1 6 SML1_CLK 20,27

2 5 <Core Design>
1DIS 2R8502
1MR2F-GP Clock Input Configuraiton -GDDR3/DDR3 3 4
X8501 a) 27MHz crystal connected to XTALIN or XTALOUT or 2N7002KDW-GP

Wistron Corporation
DIS XTALIN 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
C8524 1 2 1 4
b) 27MHz (1.8V) oscillator connected to XTALIN or 84.2N702.A3F Taipei Hsien 221, Taiwan, R.O.C.
SC12P50V2JN-3GP c) 27MHz (3.3V) oscillator connected to XO_IN (Park, Madison, and Broadway only) 2nd =
Title
GPIO_VGA_03_DATA SML1_DATA 20,27
C8525 DIS 11/2 Stuff X8501, R8502
2 3 XTALOUT 1 2
C8524, C8525
GPU_DP/LVDS/CRT/GPIO(3/5)
SC12P50V2JN-3GP A2
XTAL-27MHZ-85-GP 11/29 change X8501 to 82.30034.641 Enrico Caruso 14 A00
5 4 3 2 1
5 4 3 2 1
SSID = VIDEO
12/28 Yellow mark for OPI change
1D5V_VGA_S0
C8609
C8610
C8611
C8612
SC1U6D3V2KX-GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP SCD1U10V2KX-5GP
1
1
VGA1D 4 OF 7 1D8V_VGA_S0
DY DIS DIS DIS PCIE_PVDD
MEM I/O
2
PCIE L8707
(1.8V@504mA PCIE_VDDR)
H13 AB23 1 DIS 2
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SCD1U10V2KX-5GP
SC4D7U6D3V3KX-GP
VDDR1 PCIE_VDDR
C8613
C8615
C8616
C8637
H16 AC23
1
VDDR1 PCIE_VDDR
H19 AD24
VDDR1 PCIE_VDDR HCB2012KF-221T30-GP
C8626
C8627
J10 AE24 DIS DIS DIS DIS
SCD1U10V2KX-5GP
VDDR1 PCIE_VDDR
C8624
C8625
J23 AE25
SC1U6D3V2KX-GP
SCD1U10V2KX-5GP
2
VDDR1 PCIE_VDDR
D J24 AE26 D
1
VDDR1 PCIE_VDDR
J9 AF25
VDDR1 PCIE_VDDR 1V_VGA_S0
DIS DIS DIS DIS K10
VDDR1 PCIE_VDDR
AG26
K23
2
VDDR1
K24
VDDR1 (1.0V@1920mA PCIE_VDDC)
K9 L23
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
VDDR1 PCIE_VDDC
C8697
C8698
C8628
C8629
C8630
C8631
C8632
L11 L24
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
1
VDDR1 PCIE_VDDC
L12 L25
1
VDDR1 PCIE_VDDC
L13
VDDR1 PCIE_VDDC
L26 DIS DIS DIS DIS DIS
DIS DIS L20 M22
2
VDDR1 PCIE_VDDC
L21 N22
2
VDDR1 PCIE_VDDC
L22 N23
VDDR1 PCIE_VDDC
N24
PCIE_VDDC
R22
PCIE_VDDC
T22
1D8V_VGA_S0 VDDC_CT LEVEL PCIE_VDDC
U22
TRANSLATION PCIE_VDDC
V22
PCIE_VDDC VGA_CORE
AA20
L8601 VDD_CT
(1.8V@110mA VDD_CT) AA21
VDD_CT
1 DIS 2 AB20 AA15
SC4D7U6D3V3KX-GP
VDD_CT CORE VDDC
C8699
C8652
C8653
BLM15BD121SS1D-GP AB21 N15
SC1U6D3V2KX-GP
SCD1U10V2KX-5GP
1
VDD_CT VDDC
68.00084.F81 N17
1
VDDC
2ND = DIS M93-S3/M92-S2 R13
POWER
VDDC
DIS DIS R16
2
VDDC
AA17 R18
2
VDDR3 VDDC
AA18
VDDR3 I/O VDDC
Y21
AB17 T12
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SCD1U10V2KX-5GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SCD1U10V2KX-5GP
SC1U6D3V2KX-GP
SCD1U10V2KX-5GP
3D3V_VGA_S0 VDDR3 VDDC
AB18 T15
VDDR3 VDDC
T17
VDDC
C8646
C8649
C8665
C8669
C8647
C8670
C8645
C8648
C8672
C8675
C8671
V12 T20
SC4D7U6D3V3KX-GP
1
VDDR4/VDDR5 VDDC
C8601
C8666
C8667
Y12 U13
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
1
1
VDDR4 VDDC
U12
VDDR4/VDDR5 VDDC
U16 DY DIS DIS DIS DIS DIS DIS DIS DIS DIS DIS
DIS DIS DIS U18
2
VDDC
AA11 V21
2
NC#AA11/VDDR4 VDDC
Y11 V15
DVCLK/VDDR4 VDDC
V17
SC1U6D3V2KX-GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
VDDC
V11 V20
NC#V11/VDDR5 VDDC
C8679
C8680
C8676
C8677
U11 Y13
1
NC#U11 VDDC BIF_VDDC
Y16
VDDC
VDDC
Y18 DIS DY DIS EMI
C8673
C8674
12/6 remove tp8604, 8605 VGA1 R21 12/2 change property to EMI for BOM control
SC1U6D3V2KX-GP
SCD1U10V2KX-5GP
2
VDDC/BIF_VDDC
C U21 C
1
1
MEM CLK VDDC/BIF_VDDC
MPV18 DIS DIS L17
L8604 VDDRHA
(Park: 1.8V@75mA MPV18)
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC4D7U6D3V5KX-3GP
2
2
ISOLATED
C8651
C8654
C8661
1 DIS 2 L16
1
BLM15BD121SS1D-GP VSSRHA CORE I/O
C8604
C8603
C8690
SC4D7U6D3V3KX-GP
1
68.00084.F81 PCIE_PVDD M13 DIS DIS DIS

SC1U6D3V2KX-GP
SCD1U10V2KX-5GP
PLL VDDCI
2ND = DIS DIS DIS M15
2
VDDCI
AM30 M16
2
MPV18 PCIE_PVDD VDDCI

M17
VDDCI
M18
VDDCI
L8 M20
SPV18 MPV18 VDDCI
M21
VDDCI
N20
1V_VGA_S0 VDDCI
(120mA SPV10) H7
SPV18
L8606 12/28 Yellow mark for OPI change Close to VGA pin R21, U21
1 DIS 2 SPV10 H8
BLM15BD121SS1D-GP SPV10 VGA_CORE
C8634
C8635
C8636
SC1U6D3V2KX-GP
SCD1U10V2KX-5GP
SC4D7U6D3V3KX-GP
68.00084.F81 J7 (GDDR3/DDR3 1.12V@4A VDDCI) 2010/07/13 Modify:
SC1U6D3V2KX-GP
SCD1U10V2KX-5GP
1
1
SPVSS BIF_VDDC Add C8601 for BIF_VDDC
2ND =
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
C8657
C8659
DIS DIS DIS
C8655
C8656
2
1
BACK BIAS
SPV18 M11 DIS DIS DIS DIS
SC4D7U6D3V2MX-GP
L8605 BBP#1
C8700
(1.8V@75mA SPV18) M12
SC10U6D3V3MX-GP
2
1
BBP#2 C8696
1 DIS 2
SC4D7U6D3V3KX-GP
C8605
C8692
C8694
VGA_CORE DIS DIS

SC1U6D3V2KX-GP
SCD1U10V2KX-5GP
1
BLM15BD121SS1D-GP
2
68.00084.F81 DIS DIS DIS ROB Seymour-S3-XT
2ND = 1 2 M11_M12
SC10U6D3V5KX-1GP
2
R8602 0R2J-2-GP
P/N: FJPJP
C8695
1
DIS
2
X01: add capacity for BIF_VDDC
2010/06/17_1 AO4468 MAX 3.1A
B B
Rds(on) = 1ow Rds(on) = 101~155mOhm 2010/07/08
VGS=0.7~1.5V VGS=+/-12V
3D3V_S5 3D3V_VGA_S0
BIF_VDDC U8601 U8603 VGA_CORE BIF_VDDC U8604 1V_VGA_S0
AO3400A-GP AO3400A-GP
U8606
AO3418-GP 1D5V_VGA_PWOK 11/18 dummy 1D5V_VGA_PWOK
AO3418-GP
circuit
DIS BIF_VDDC_CORE
DIS DIS BIF_VDDC_1V
DIS
S D D S S D D S
84.03400.B37 84.03400.B37 84.03418.031 84.03418.031
1
R8607 R8606
10KR2J-3-GP 10KR2J-3-GP
G
5V_S0 3D3V_VGA_S0 5V_S0 3D3V_VGA_S0 DY DY

0629 Modify
Change polarity ,
2
Q8603 11/2 change net name to 1D5V_VGA_PWOK
switch pin D and pin S. Q8603_G G
1
R8605 R8603 R8609 R8604 9/6 DY D 1D5V_VGA_PWOK 83

1KR2J-1-GP 1KR2J-1-GP 1KR2J-1-GP 1KR2J-1-GP
DIS DY DIS DY S
2
3
PX_EN## PX_EN# 2N7002K-2-GP
1R8608 2 Q8604_B 1 DY Q8604
1D5V_VGA_S0
PMBS3904-1-GP
X02-0302 Add R8605, R8609 PU 5V for lower Rdson DY 0629 Modify
X01: modify to DGPU_PWROK 2K2R2J-2-GP
2
SCD1U10V2KX-5GP
1
C8693
1R8601 2 1D5V_VGA_PWOK_R DY
22,92,93 DGPU_PWROK
0R0402-PAD
2
3D3V_VGA_S0
1D5V_VGA_PWOK
U8605 Q8602 DIS Non-BACO= HIGH
1
B BACO = LOW
5 4 3
VCC
92,93 8209A_EN/DEM_VGA 2
A DY PX_EN#
4 5 2
Y
3
GND PX_EN 8209A_EN/DEM_VGA1D5V_VGA_PWOK_R PX_EN# PX_EN##
PX_EN## 6 1
Q8601 74LVC1G08GW-1-GP
A 84 PX_EN G 73.01G08.L04 2N7002KDW-GP Non-BACO 0 1 1 0 1 A
DIS D 2ND = 84.2N702.A3F

BACO 1 0 0 1 0
S 2nd =
2N7002K-2-GP PX_EN# = High, BIF_VDDC = 1V_VGA_S0 <Core Design>
12/16 dumy U8605 and stuff R8601 to follow standard schematic. PX_EN## = High, BIF_VDDC = VGA_CORE
Wistron Corporation
Title
GPU_POWER(4/5)
A2
5 4 3 2 1
5 4 3 2 1
SSID = VIDEO Vendor suggest

Vendor suggest LVDS mode(1.8V@440mA DPEF_VDD18) 09/23
09/23 DP mode(1.8V@300mA DPEF_VDD18)
DPAB_VDD18 1D8V_VGA_S0
VGA1E 5 OF 7 DPEF_VDD18
1D8V_VGA_S0
VGA1G 7 OF 7 (1.8V@300mA DPAB_VDD18)
D 1R8714 2 D
SC4D7U6D3V3KX-GP
DP E/F POWER DP A/B POWER
C8714
C8712
C8713
AA27 A3 1R8711 2 0R0402-PAD
SC1U6D3V2KX-GP
SCD1U10V2KX-5GP
PCIE_VSS GND
1
C8717
C8718
C8719
AB24 A30 0R0402-PAD
SC1U6D3V2KX-GP
SCD1U10V2KX-5GP
SC4D7U6D3V3KX-GP
PCIE_VSS GND
1
AB32 PCIE_VSS GND/EVDDQ AA13 AG15 DPE_VDD18 DPA_VDD18 AE11 DY DY DY
AC24 AA16 DY DY DY AG16 AF11
2
PCIE_VSS GND DPE_VDD18 DPA_VDD18
AC26 AB10
2
PCIE_VSS GND DPEF_VDD10 DPAB_VDD10
AC27 PCIE_VSS GND/EVDDQ AB15
AD25 AB6 1V_VGA_S0 1V_VGA_S0
PCIE_VSS GND
AD32 PCIE_VSS GND AC9 AG20 DPE_VDD10 DPA_VDD10 AF6
AE27 PCIE_VSS GND AD6 AG21 DPE_VDD10 DPA_VDD10 AF7
AF32 PCIE_VSS GND AD8 (1.0V@220mA DPAB_VDD10)
AG27 PCIE_VSS GND AE7 1R8713 2 1R8716 2
C8721
C8720
C8725
C8702
C8703
C8705
AH32 AG12 0R0402-PAD AG14 AE1 0R0402-PAD
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SC10U6D3V5KX-1GP
SC4D7U6D3V3KX-GP
PCIE_VSS GND DPE_VSSR DPA_VSSR
1
K28 PCIE_VSS GND AH10 AH14 DPE_VSSR DPA_VSSR AE3
K32 PCIE_VSS GND AH28 DY DY DY AM14 DPE_VSSR DPA_VSSR AG1 DY DY DY
L27 B10 AM16 AG6
2
PCIE_VSS GND DPE_VSSR DPA_VSSR
M32 PCIE_VSS GND B12 AM18 DPE_VSSR VGA1 DPA_VSSR AH5
N25 PCIE_VSS GND B14
N27 B16 DPEF_VDD18 DPAB_VDD18
PCIE_VSS GND
P25 PCIE_VSS GND B18 LVDS mode(1V@240mA DPEF_VDD10)
P32 B20 AF16 AE13
R27
PCIE_VSS GND
B22
DP mode(1V@220mA DPEF_VDD10) AG17
DPF_VDD18 DPB_VDD18
AF13
PCIE_VSS GND DPF_VDD18 DPB_VDD18
T25 PCIE_VSS GND B24
T32 B26 DPEF_VDD10 DPAB_VDD10
PCIE_VSS GND
U25 PCIE_VSS GND B6
U27 PCIE_VSS GND B8 AF22 DPF_VDD10 DPB_VDD10 AF8
V32 PCIE_VSS GND C1 AG22 DPF_VDD10 DPB_VDD10 AF9
W25 PCIE_VSS GND C32
W26 PCIE_VSS GND E28
C W27 F10 AF23 AF10 C
PCIE_VSS GND DPF_VSSR DPB_VSSR
Y25 PCIE_VSS GND F12 2010/07/09 N11 and N12: in Seymour is NC AG23 DPF_VSSR DPB_VSSR AG9
Y32 PCIE_VSS GND F14 AM20 DPF_VSSR DPB_VSSR AH8
GND F16 AM22 DPF_VSSR DPB_VSSR AM6
GND F18 AM24 DPF_VSSR DPB_VSSR AM8
GND F2
F20 N11_GND 1ROB 2
GND R8703
M6 GND GND F22
N11_GND N11 F24 R8702 0R2J-2-GP DIS 150R2F-1-GP
N12_GND GND GND N12_GND
N12 GND GND F26 1ROB 2 1 2DPCD_CALR AF17 DPEF_CALR DPAB_CALR AE10 DPAB_CALR 1DIS 2
N13 F6 R8701 150R2F-1-GP
GND GND R8704 0R2J-2-GP DPAB_VDD18
N16
N18
N21
GND
GND
GND
GND GND
GND
GND
F8
G10
G27
DPEF_VDD18
AG18 DPE_PVDD
DP PLL POWER
DPA_PVDD AG8
P6 GND GND G31 AF19 DPE_PVSS DPA_PVSS AG7
P9 G8 DPEF_VDD18 DPAB_VDD18
GND GND
R12 GND VGA1 GND H14
R15 GND GND H17
R17 GND GND H2 AG19 DPF_PVDD DPB_PVDD AG10
R20 GND GND H20 AF20 DPF_PVSS DPB_PVSS AG11
T13 GND GND H6
T16 GND GND J27
T18 GND GND J31
T21 GND GND K11 Seymour-S3-XT
T6
U15
GND
GND
GND
GND
K2
K22 P/N: FJPJP
U17 GND GND K6
U20 GND GND T11
U9 GND GND R11
B B
V13 GND
V16 GND
V18 GND
Y10
Y15
GND Vendor suggest
GND
Y17 GND VSS_MECH A32 VSS_MECH1 1 TP8701TPAD14 1D8V_VGA_S0 9/23 DPB_VDD18
Y20 GND VSS_MECH AM1 VSS_MECH2 1 TP8702TPAD14
VSS_MECH AM32 VSS_MECH3 1 TP8703TPAD14
(1.8V@150mA DPB_VDD18)
1R8715 2
0R0402-PAD
Seymour-S3-XT
P/N: FJPJP
11/18 Del R8709, C8710,C8711
A <Core Design> A
Wistron Corporation
Title
GPU_DPPWR/GND(5/5)
A3
5 4 3 2 1
5 4 3 2 1
SSID = VIDEO
1D5V_VGA_S0 1D5V_VGA_S0
VRAM1 VRAM2
MDA[0..31] 84 MDA[0..31] 84
K8 E3 MDA3 K8 E3 MDA27
VDD DQL0 MDA7 VDD DQL0 MDA29
K2 VDD DQL1 F7 K2 VDD DQL1 F7
N1 F2 MDA1 N1 F2 MDA31
R9 VDD DQL3 F8 R9 VDD DQL3 F8
B2 H3 MDA2 B2 H3 MDA28
D9 VDD DQL5 H8 D9 VDD DQL5 H8
D MDA0 MDA30 D
G7 VDD DQL6 G2 G7 VDD DQL6 G2
R1 H7 MDA5 R1 H7 MDA26
VDD DQL7 VDD DQL7
N9 VDD N9 VDD
D7 MDA21 D7 MDA12
DQU0 MDA19 DQU0 MDA10
A8 VDDQ DQU1 C3 A8 VDDQ DQU1 C3
A1 C8 MDA23 A1 C8 MDA13
VDDQ DQU2 MDA18 VDDQ DQU2 MDA11
C1 VDDQ DQU3 C2 C1 VDDQ DQU3 C2
C9 A7 MDA20 C9 A7 MDA8
D2 VDDQ DQU5 A2 D2 VDDQ DQU5 A2
E9 B8 MDA22 E9 B8 MDA9
F1 VDDQ DQU7 A3 F1 VDDQ DQU7 A3
H9 VDDQ H9 VDDQ
H2 VDDQ DQSU C7 QSAP_2 84 H2 VDDQ DQSU C7 QSAP_1 84
DQSU# B7 QSAN_2 84 DQSU# B7 QSAN_1 84
VRAM1_VREF H1 VRAM1_VREF H1
VRAM2_VREF VREFDQ VRAM2_VREF VREFDQ
M8 VREFCA DQSL F3 QSAP_0 84 M8 VREFCA DQSL F3 QSAP_3 84
1 2 VRAM_ZQ1 L8 G3 QSAN_0 84 1 2 VRAM_ZQ2 L8 G3 QSAN_3 84
R8801 243R2F-2-GP ZQ DQSL# R8802 243R2F-2-GP ZQ DQSL#
DIS DIS
ODT K1 ODTA0 84 ODT K1 ODTA0 84
84,89 MAA0 N3 A0 84,89 MAA0 N3 A0
84,89 MAA1 P7 A1 84,89 MAA1 P7 A1
84,89 MAA2 P3 A2 CS# L2 CSA0#_0 84 84,89 MAA2 P3 A2 CS# L2 CSA0#_0 84
84,89 MAA3 N2 A3 RESET# T2 MEM_RST 84,89 84,89 MAA3 N2 A3 RESET# T2 MEM_RST 84,89
84,89 MAA4 P8 A4 84,89 MAA4 P8 A4
84,89 MAA5 P2 A5 84,89 MAA5 P2 A5
84,89 MAA6 R8 A6 NC#T7 T7 84,89 MAA6 R8 A6 NC#T7 T7
84,89 MAA7 R2 A7 NC#L9 L9 84,89 MAA7 R2 A7 NC#L9 L9
84,89 MAA8 T8 A8 NC#L1 L1 84,89 MAA8 T8 A8 NC#L1 L1
84,89 MAA9 R3 A9 NC#J9 J9 84,89 MAA9 R3 A9 NC#J9 J9
C 84,89 MAA10 L7 A10/AP NC#J1 J1 84,89 MAA10 L7 A10/AP NC#J1 J1 C
84,89 MAA11 R7 A11 84,89 MAA11 R7 A11
84,89 MAA12 N7 A12/BC# 84,89 MAA12 N7 A12/BC#
84,89 MAA13 T3 A13 VSS J8 84,89 MAA13 T3 A13 VSS J8
M7 NC#M7 VSS M1 M7 NC#M7 VSS M1
VRAM1 VSS M9 VRAM2 VSS M9
VSS J2 VSS J2
84,89 A_BA0 M2 BA0 VSS P9 84,89 A_BA0 M2 BA0 VSS P9
84,89 A_BA1 N8 BA1 VSS G8 84,89 A_BA1 N8 BA1 VSS G8
84,89 A_BA2 M3 BA2 VSS B3 84,89 A_BA2 M3 BA2 VSS B3
VSS T1 VSS T1
VSS A9 VSS A9
84 CLKA0 J7 CK VSS T9 84 CLKA0 J7 CK VSS T9
84 CLKA0# K7 CK# VSS E1 84 CLKA0# K7 CK# VSS E1
VSS P1 VSS P1
84 CKEA0 K9 CKE 84 CKEA0 K9 CKE
1
R8804 R8803 G1 G1
56R2F-1-GP 56R2F-1-GP VSSQ VSSQ
VSSQ F9 VSSQ F9
DIS DIS 84 DQMA2 D3 DMU VSSQ E8 84 DQMA1 D3 DMU VSSQ E8
84 DQMA0 E7 DML VSSQ E2 84 DQMA3 E7 DML VSSQ E2
D8 D8
2
VSSQ VSSQ
VSSQ D1 VSSQ D1
GPU_CLKA0_T 84 WEA0# L3 B9 84 WEA0# L3 B9
WE# VSSQ WE# VSSQ
84 CASA0# K3 CAS# VSSQ B1 84 CASA0# K3 CAS# VSSQ B1
84 RASA0# J3 RAS# VSSQ G9 84 RASA0# J3 RAS# VSSQ G9
1
C8802
SCD01U16V2KX-3GP
DIS H5TQ2G63BFR-11C-GP H5TQ2G63BFR-11C-GP
2
B B
X01-0211 change VRAM symbol for layout (larger package)
1D5V_VGA_S0
1D5V_VGA_S0
1
1
R8808
R8805 2K1R2F-GP
2K1R2F-GP
DIS
DIS
2
2
VRAM2_VREF
VRAM1_VREF
1
1
C8805 DY C8807
1
R8806 C8803 C8806 R8807 SCD1U10V2KX-5GP

2K1R2F-GP SCD1U10V2KX-5GP SC1000P50V3JN-GP-U 2K1R2F-GP SC1000P50V3JN-GP-U
DIS
2
DIS DY DIS
2
DIS
2
2
A A
DN15ATI Whistler
Wistron Corporation
Title
GPU-VRAM1,2 (1/4)
Custom
5 4 3 2 1
5 4 3 2 1
SSID = VIDEO
Simulation 10/07 VRAM3 VRAM4
Simulation 10/07
MDA[32..63] 84 MDA[32..63] 84
K8 E3 MDA35 K8 E3 MDA61
VDD DQL0 VDD DQL0
C8902
C8906
C8909
C8908
C8911
C8910
C8913
C8912
C8919
C8917
C8921
C8920
C8923
C8922
C8915
C8914
MDA39 MDA59
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
K2 VDD DQL1 F7 K2 VDD DQL1 F7
N1 F2 MDA33 N1 F2 MDA62
VDD DQL2 VDD DQL2
1
1
R9 F8 MDA36 R9 F8 MDA57
DIS DIS DIS DIS DIS DIS DIS DIS B2 VDD DQL4 H3 DIS DIS DIS DIS DIS DIS DIS B2 VDD DQL4 H3
D9 H8 MDA37 DIS D9 H8 MDA56
2
2
D VDD DQL5 MDA32 VDD DQL5 MDA60 D
G7 VDD DQL6 G2 G7 VDD DQL6 G2
R1 H7 MDA38 R1 H7 MDA58
VDD DQL7 VDD DQL7
N9 VDD N9 VDD
D7 MDA45 D7 MDA52
DQU0 MDA40 DQU0 MDA53
C8905
C8907
C8916
C8918
MDA47 MDA49
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
C1 VDDQ DQU3 C2 MDA41 12/28 Yellow mark for OPI change C1 VDDQ DQU3 C2 MDA54
1
C9 A7 MDA44 C9 A7 MDA48
Simulation 10/07 DIS DIS D2 VDDQ DQU5 A2
MDA46
DIS DIS D2 VDDQ DQU5 A2
MDA50
E9 B8 E9 B8
2
F1 VDDQ DQU7 A3 F1 VDDQ DQU7 A3
12/28 Yellow mark for OPI change H9 VDDQ H9 VDDQ
H2 VDDQ DQSU C7 QSAP_5 84 H2 VDDQ DQSU C7 QSAP_6 84
DQSU# B7 QSAN_5 84 DQSU# B7 QSAN_6 84
VRAM3_VREF H1 VRAM3_VREF H1
VRAM4_VREF VREFDQ VRAM4_VREF VREFDQ
M8 VREFCA DQSL F3 QSAP_4 84 M8 VREFCA DQSL F3 QSAP_7 84
1 2 VRAM_ZQ3 L8 G3 QSAN_4 84 1 2 VRAM_ZQ4 L8 G3 QSAN_7 84
R8903 243R2F-2-GP ZQ DQSL# R8904 243R2F-2-GP ZQ DQSL#
DIS DIS
ODT K1 ODTA1 84 ODT K1 ODTA1 84
84,88 MAA0 N3 A0 84,88 MAA0 N3 A0
84,88 MAA1 P7 A1 84,88 MAA1 P7 A1
84,88 MAA2 P3 A2 CS# L2 CSA1#_0 84 84,88 MAA2 P3 A2 CS# L2 CSA1#_0 84
84,88 MAA3 N2 A3 RESET# T2 MEM_RST 84,88 84,88 MAA3 N2 A3 RESET# T2 MEM_RST 84,88
84,88 MAA4 P8 A4 84,88 MAA4 P8 A4
84,88 MAA5 P2 A5 84,88 MAA5 P2 A5
84,88 MAA6 R8 A6 NC#T7 T7 84,88 MAA6 R8 A6 NC#T7 T7
84,88 MAA7 R2 A7 NC#L9 L9 84,88 MAA7 R2 A7 NC#L9 L9
84,88 MAA8 T8 A8 NC#L1 L1 84,88 MAA8 T8 A8 NC#L1 L1
84,88 MAA9 R3 A9 NC#J9 J9 84,88 MAA9 R3 A9 NC#J9 J9
C 84,88 MAA10 L7 A10/AP NC#J1 J1 84,88 MAA10 L7 A10/AP NC#J1 J1 C
84,88 MAA11 R7 A11 84,88 MAA11 R7 A11
84,88 MAA12 N7 A12/BC# 84,88 MAA12 N7 A12/BC#
84,88 MAA13 T3 A13 VSS J8 84,88 MAA13 T3 A13 VSS J8
M7 NC#M7 VSS M1 M7 NC#M7 VSS M1
VRAM3 VSS M9 VRAM4 VSS M9
VSS J2 VSS J2
84,88 A_BA0 M2 BA0 VSS P9 84,88 A_BA0 M2 BA0 VSS P9
84,88 A_BA1 N8 BA1 VSS G8 84,88 A_BA1 N8 BA1 VSS G8
84,88 A_BA2 M3 BA2 VSS B3 84,88 A_BA2 M3 BA2 VSS B3
VSS T1 VSS T1
VSS A9 VSS A9
84 CLKA1 J7 CK VSS T9 84 CLKA1 J7 CK VSS T9
84 CLKA1# K7 CK# VSS E1 84 CLKA1# K7 CK# VSS E1
VSS P1 VSS P1
84 CKEA1 K9 CKE 84 CKEA1 K9 CKE
1
R8907 R8908 G1 G1
56R2F-1-GP 56R2F-1-GP VSSQ VSSQ
VSSQ F9 VSSQ F9
DIS DIS 84 DQMA5 D3 DMU VSSQ E8 84 DQMA6 D3 DMU VSSQ E8
84 DQMA4 E7 DML VSSQ E2 84 DQMA7 E7 DML VSSQ E2
D8 D8
2
VSSQ VSSQ
VSSQ D1 VSSQ D1
GPU_CLKA1_T 84 WEA1# L3 B9 84 WEA1# L3 B9
WE# VSSQ WE# VSSQ
84 CASA1# K3 CAS# VSSQ B1 84 CASA1# K3 CAS# VSSQ B1
84 RASA1# J3 RAS# VSSQ G9 84 RASA1# J3 RAS# VSSQ G9
1
C8903
SCD01U16V2KX-3GP
DIS H5TQ2G63BFR-11C-GP H5TQ2G63BFR-11C-GP
2
B X01-0211 change VRAM symbol for layout (larger package) B
1D5V_VGA_S0
1D5V_VGA_S0
1
1
R8905
R8901 2K1R2F-GP
2K1R2F-GP
DIS
DIS
2
2
VRAM4_VREF
VRAM3_VREF
1
1
C8904 C8925
1
R8902 C8901 C8924 R8906 SCD1U10V2KX-5GP SC1000P50V3JN-GP-U

2K1R2F-GP SCD1U10V2KX-5GP SC1000P50V3JN-GP-U 2K1R2F-GP DIS DY
2
DIS DY
2
DIS DIS
2
2
A A
DN15ATI Whistler
Wistron Corporation
Title
GPU-VRAM3,4 (2/4)
Custom
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
Wistron Corporation
Title
GPU-VRAM5,6 (3/4)
A3
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
Wistron Corporation
Title
GPU-VRAM7,8 (4/4)
A3
5 4 3 2 1
5 4 3 2 1
SSID = PWR.Plane.Regulator_VGACORE
VGA_CORE VGA_CORE_PWR VGA_CORE
PG9202 PG9203
1 2 1 2
DCBATOUT PWR_DCBATOUT_VGA_CORE
PG9205 PG9206
PG9204 1 2 1 2
1 2 GAP-CLOSE-PWR-3-GP GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
PG9208 PG9209
PG9207 1 2 1 2
GAP-CLOSE-PWR-3-GP
PG9211 PG9214
PWR_DCBATOUT_VGA_CORE
D PG9210 X02-0310 stuff PC9205 1 2 1 2 D
GAP-CLOSE-PWR-3-GP 11/18
PG9201 PG9217
PG9213 5V_S5 1 2 1 2
SCD1U25V2KX-GP
SC10U25V5KX-GP
SC10U25V5KX-GP
SC10U25V5KX-GP
2
2
GAP-CLOSE-PWR-3-GP
PC9202
PC9203
PC9204
PC9205
12/15 DIS DIS DIS PG9216 PG9220
PG9215 1 2 1 2
1
PU9202 GAP-CLOSE-PWR-3-GP GAP-CLOSE-PWR-3-GP
1 2
5
6
7
8
Freq=360KHz
GAP-CLOSE-PWR-3-GP
RJK03B9DPA-00-J5A-GP
D
D
D
D
PC9206
DIS Design Current = 13.6A PG9219 PG9212
PG9218 SC1U10V2KX-1GP 1 2 1 2
21.3A<OCP< 25.3A
2
PR9202
GAP-CLOSE-PWR-3-GP DIS
PWR_VGA_CORE_TON
G
1 2 4
DIS
S
S
S
200KR2F-L-GP
3
2
1
PU9201 PR9203 PC9201 12/15
2D2R3-1-U-GP SCD1U25V3KX-GP
PR9204 16 13 PWR_VGA_CORE_BOOT 2 1PWR_VGA_CORE_BOOT_C 1 2
2
DIS 1 9
TON BOOT DIS DIS PL9201 VGA_CORE_PWR
10R2F-L-GP VDDP
12 PWR_VGA_CORE_UGATE BOM merge 11/18
PWR_VGA_CORE_VDD UGATE PWR_VGA_CORE_PHASE
2 11 1 2
VDD PHASE DIS
GAP-CLOSE-PWR-3-GP
8 PWR_VGA_CORE_LGATE
LGATE
12/15 COIL-D68UH-9-GP
1
PG9221
PWR_VGA_CORE_PGOOD 4 7 PC9207
1
PGOOD G0 PWRCNTL_0 85 PU9203
PWR_VGA_CORE_CS 10 3 PWR_VGA_CORE_FB DYPR9206 PT9201 PT9202 PT9203
5
6
7
8
CS FB
SCD1U10V2KX-5GP
ST330U2VDM-3GP
ST330U2VDM-4-GP
SE330U2VDM-L-GP
DIS 14 PWRCNTL_1 85 DIS DIS DIS
1
G1
D
D
D
D
RJK03D4DPA-00-J5A-GP
PWR_VGA_CORE_D1 2D2R5F-2-GP
5 DY
2
1
PR9205 8209A_EN/DEM_VGA D1 PWR_VGA_CORE_D0
1PR9206_2
15 6
DIS DIS
2
EM/DEM D0 PWR_VGA_CORE_VOUT
PC9208 10KR2F-L1-GP 11/10
SC1U10V2KX-1GP 17 1 PWR_VGA_CORE_VOUT
2
GND VOUT
G
4 DIS
2
S
S
S
12/2
1
RT8208BGQW-GP
3
2
1
PC9213
X01-0217 PR9205 to 10K (F)
DY SC560P50V-GP PR9201
2
10R2J-2-GP
DIS
12/17 change PR9208 to 5% for meet standard schematic.
2
X01-0217 change PT9202 -->79.33719.20L
2PR9201_2
C C
11/18 PT9203 -->79.33719.L01
PC9209 PC9210
PR9208 PR9218
1
DIS
SC10P50V2JN-4GP
SC10P50V2JN-4GP
1 2 10KR2F-2-GP
DIS DY DY
2
10KR2J-3-GP
1
1
PR9209
10KR2J-3-GP PWR_VGA_CORE_FB
PD9201 DIS
93 DGPU_PWR_EN 2 DY1 8209A_EN/DEM_VGA
8209A_EN/DEM_VGA 86,93 I/P cap: 10U 25V K0805 X5R/ 78.10622.51L
Inductor: 0.68UH PCMB063T-R68MS Cyntec 4.8mohm/5.3mohm Isat =17Arms 68.R6810.20J
2
1
CH551H-30PT-GP PC9211
1
DY SCD1U10V2KX-4GP PWR_VGA_CORE_PGOOD 2 PR9212 1 O/P cap: 330U2V EEFCX0D331R 15mOhm 2.7Arms Panasonic/79.33719.20D
DGPU_PWROK22,86,93
1
11/18 Stuff PD9201 0R0402-PAD PR9213 H/S: SIR172DP / 10.3mohm/12.4mOhm@4.5Vgs/ 84.00172.037
2
PR9210 PR9211 49K9R2F-L-GP

L/S: SiR460DP / 0.49mohm/0.61mOhm@4.5Vgs/ 84.00460.037
1
12/16 Dummy PD9201 to follow DN13, 15 11/15 DIS DIS DIS
75KR2F-GP
150KR2F-L-GP
PC9212 DIS
2
SC100P50V2JN-3GP
1GND_SENSE_1
PWR_VGA_CORE_D1
PWR_VGA_CORE_D0
RT8208B for Seymour-XT RT8208B for Robson-XT PR9216

DIS
10R2J-2-GP
PWRCNTL_1 PWRCNTL_0 VGA_CORE_PWR PWRCNTL_1 PWRCNTL_0 VGA_CORE_PWR
2
L L 1.05V L L 1.12V
L H 1.0V H L 0.95V
H H 0.9V H H 0.9V
B B
For Robson:
PR9218=10K Vout=0.75V*(R1+R2)/R2
PR9213=49.9K
PR9211=150K
PR9210=44.2K
11/15
A A
<Core Design>
Wistron Corporation
Title
RT8208B_+VGA_CORE
A2
5 4 3 2 1
5 4 3 2 1
3D3V_S0 to 3D3V_VGA_S0 Transfer AO4468, SO-8
Change DUMMY Reference Name to PX_BACO

1D8V_VGA_S0 Id=??A, Qg=9~12nC
Rdson=17.4~22m ohm
1D8V_S0
1D8V_VGA_S0
PU9306
8 D DIS S 1
DY 7 D S 2
1 PR9301
2 6 D S 3
1
0R2J-2-GP 5 D G 4 PC9331
1
DMP2130L-7-GP 3D3V_VGA_S0 PC9330
PQ9302 SC10U6D3V3MX-GP DIS AO4468-GP SC10U6D3V3MX-GP
2
3D3V_S0 S 84.04468.037 DIS
2
D 2nd = 84.08882.037
D
84.02130.031
G
2ND = 84.03413.A31
2
1
DIS
G
D PR9316 DIS 3D3V_VGA discharge 3D3V_AUX_S5 D
10KR2J-3-GP 2
DIS PC9324 PQ9302_G 1 2 1D8V_VGA_EN# 1D8V_ENABLE_RC
SCD1U10V2KX-5GP PR9334 100KR2J-1-GP
1
PR9333
DIS D G S
PR9319 2 1
PR9319_1 1 2 DIS
4
DIS
1
10KR2J-3-GP PQ9306 15V_S5 20KR2F-L-GP
DIS
2N7002KDW-GP PC9329
2
SCD01U50V2KX-1GP
84.2N702.A3F
2
6
4
PR9314 DIS
2
PQ9303 470R2J-2-GP 2nd = 84.DM601.03F
2N7002KDW-GP
DIS
G9731_PGOOD_1V 1PR9320 2 1D8V_VGA_EN S G D PR9335
84.2N702.A3F DIS 0R0402-PAD 100KR2J-1-GP
1
2nd = 84.DM601.03F PC9323 DIS
1
SCD1U10V2KX-5GP
1
DY
2
3.3V_RUN_VGA_1 1D8V_ENABLE
PR9321
3D3V_S0 1 2
DIS PD9303
10KR2J-3-GP
DGPU_PWR_EN
92 DGPU_PWR_EN 2 DY 1
CH551H-30PT-GP
1D8V_VGA_S0
3D3V_S5 3D3V_VGA_S0
Discharge Circuit
DGPU_PWR_EN 92
1D8V_VGA_S0_PG
10KR2J-3-GP
PR9339
PQ9312
1
1 6 DGPU_PWR_EN PR9338 PR9337
1
100KR2J-1-GP 470R2J-2-GP
18 DGPU_PWR_EN# 2 5 1D8V_VGA_EN# DY
DIS DY DIS
2
DIS_1D8V_VGA_S0 3 4
2N7002K-2-GP
2
C C
2N7002KDW-GP
DIS_1D8V_VGA_S0
PQ9310_C G DY
84.2N702.A3F
2nd = 84.DM601.03F D 1D8V_S0_VGA_PG 83
S
DGPU_PWR_EN# 11/18 Merge PQ9803 PQ9804 to PQ9312 DY
3
PQ9310_B 1
DY PQ9309
dGPU mode L 1D8V_VGA_S0 1 PR9340 2 PQ9310 84.2N702.J31
PMBS3904-1-GP
2ND = 84.2N702.031
IGPU H
2
2K2R2J-2-GP
SCD1U10V2KX-5GP
1
PC9301
IGPU with BACO L DY
84.03904.L06
2nd = 84.03904.P11
3rd = 84.03904.T11
2
1D5V_VGA_S0 change low Rds(on) MOSFET G9731 for 1V_VGA_S0
1D5V_S3 1D5V_VGA_S0 Park_Madison Does Not Support BACO, So follow Old Sequence
PU9305
Seymour_Whistler_Robson Support BACO, So Change Sequence
AO4468, SO-8 8 D S 1
7 D S 2 1D5V_S3 1V_VGA_S0_LDOIN
1V_VGA_S0
Id=?A, Qg=9~12nC 6 D S 3
1
Rdson=17.4~22m ohm 5 D G 4 PC9332 PG9301 Design current = 2.445A

1
1D5V_ENABLE_RC
PC9327 DIS 1 2
DIS AO4468-GP SC10U6D3V3MX-GP GAP-CLOSE-PWR-3-GP
2
84.04468.037 DIS
SC10U6D3V3MX-GP
2
1D5V_S3 to 1D5V_VGA_S0 trace need increase 2nd = 84.08882.037

1
PG9302
2 Vout=0.8V*(R1+R2)/R2= 1.0036V
GAP-CLOSE-PWR-3-GP
to avoid 1D5V_VGA_S0 DROP Voltage.
PG9303
1 2 PU9303 Vo(cal.)=1.0036V 1V_PWR
B PR9330 B
Park_Madison Does Not Support BACO, So follow Old Sequence GAP-CLOSE-PWR-3-GP 1V_VGA_S0
Seymour_Whistler_Robson Support BACO, So Change Sequence 1 2 5
VIN DIS PG9305
PG9304 6 4 1 2
Discharge Circuit GAP-CLOSE-PWR-3-GP 1 2
5V_S5
PWR_1V_PGOOD 7 VPP VO#4
3 GAP-CLOSE-PWR-3-GP
1
1
20KR2F-L-GP POK VO#3
DIS 3D3V_VGA_S0 should ramp-up before VGA_Core 8 2 PC9012
1
3D3V_AUX_S5 1D5V_VGA_S0 VEN ADJ
PC9326 DIS 9
GND GND
1 DY DIS
SCD01U50V2KX-1GP VGA_Core should ramp-up before 1V_VGA_S0 PC9303 PC9313 DIS PG9306
SCD01U16V2KX-3GP
2
2
1
1 2 1D5V_VGA_EN# SC10U10V5KX-2GP SC1U10V2KX-1GP PC9317 PC9316 1 2
1
PR9332 100KR2J-1-GP 1V_VGA_S0 should ramp up before 1D8V_VGA_S0 DIS DIS G9731F11U-GP PR9322 GAP-CLOSE-PWR-3-GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
1
DIS D G S 74.G9731.03D 1K27R2F-L-GP

PR9336 DIS
2
470R2J-2-GP so 1V_VGA_S0 EN have to fine tune RC delay 2nd = 74.05930.03D PG9307
2
6
PQ9305 1 2
15V_S5 DIS after VGA_Core
2N7002KDW-GP DIS GAP-CLOSE-PWR-3-GP
DIS_1D5V_VGA_S02
84.2N702.A3F DIS 2ND = 84.2N702.031 3D3V_VGA_S0 1 2

2nd = 84.DM601.03F PR9304 100KR2J-1-GP PWR_1V_ADJ
84.2N702.J31 DIS PG9308
1
PD9301 2N7002K-2-GP 1 2 G9731_PGOOD_1V 1 PR9311 2 1 2

3D3V_VGA_S0
92 DGPU_PWR_EN 2 DY 1 S G D PR9331 PR9312 10KR2J-3-GP 0R0402-PAD GAP-CLOSE-PWR-3-GP
1
100KR2J-1-GP G 1D5V_VGA_EN#
CH551H-30PT-GP DIS PR9315
X01 :dummy PR9326 PR9326 D PWR_1V_EN 4K99R2F-L-GP
1
1 2 1D5V_VGA_EN DIS
22,86,92 DGPU_PWROK 0R2J-2-GP S
2
DY 1D5V_ENABLE DIS PC9318
SCD1U10V2KX-5GP
PQ9307 PD9302
92 DGPU_PWR_EN 2 DY 1 DIS
2
1PR9327 2 CH551H-30PT-GP
86,92 8209A_EN/DEM_VGA 0R0402-PAD
11/18 Add PR9327 for 8209A_EN/DEM_VGA turn on

1D5V_VGA_S0 power.
PR9318 Discharge Circuit
3D3V_AUX_S5 1 2 PWR_1V_EN#
DIS
A 100KR2J-1-GP A
6
PQ9311
2N7002KDW-GP DIS <Core Design>
84.2N702.A3F
1
2nd = 84.DM601.03F
Wistron Corporation
PR9317 Taipei Hsien 221, Taiwan, R.O.C.
PQ9311_3 2 DIS 1 Title

PWR_1V_EN
1V_VGA_S0
DISCRETE VGA POWER
470R2J-2-GP Size Document Number Rev
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
DN15ATI Whistler
A A
Wistron Corporation
Title
LVDS_Switch
A3
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
DN15ATI Whistler
A A
Wistron Corporation
Title
CRT_Switch
A3
5 4 3 2 1
5 4 3 2 1
SSID = SDIO
D D
C C
(Blanking)
B B
Wistron Corporation
Title
TOUCH PANEL
A3
5 4 3 2 1
5 4 3 2 1
H1 H3 H4 H5 H6 H7
H2
HT85BE85R29-U-5-GP HOLE256R115-GP HT85BE85R29-U-5-GP HT85BE85R29-U-5-GP HT85BE85R29-U-5-GP HT85BE85R29-U-5-GP HT85B95X975R29-S-GP X01-0208 stuff SPR1 and add SPR2
SSID = Mechanical
A00-0406 dummy SPR2
1
1
SPR1 DY SPR2
SPRING-62-GP SPRING-58-GP
34.4B312.002
1
34.39S07.003
D X02-0314 stuff SPR2 D
12/17 add SPR1 for EMI

12/21 change SPR1 to 34.4B312.002
12/22 change SPR1 to 34.39S07.003
X01-0211 change SPR2, SPR3 to 34.4B312.002
X01-0210 add SPR3
SPR4 SPR5
For CPU BRACKET VGA Stand-Off PCH Stand-Off SPRING-13-GP-U SPRING-13-GP-U
SPR3
SPRING-58-GP
H11
34.4B312.002 34.43E24.001 34.43E24.001
1
STF237R117H83-1-GP H12 H13
H8 H9 H10
HOLE197R166-1-GP HOLE197R166-1-GP HOLE197R166-1-GP STF217R113H162-GP STF237R117H83-1-GP
DIS
DY
1
1
1
1
X01-0211 add SPR4, SPR5
C C
A00-0412 dummy H12, H13 for remove PCH Heatsink

A00-0413 change H12 to 34.4HL17.001
12/2 Delete SPR1, SPR2
DCBATOUT
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
2
2
EC9701
EC9702
EC9703
EC9704
EC9705
EC9706
EC9707
EC9708
EC9709
EC9710
EC9711
EC9712
EC9713
EC9714
EC9715
EC9716
EC9717
EC9718
EC9719
EC9742
EC9743
EC9744
EC9745
EC9746
1
1
DY DY DY DY DY
DY DY DY DY DY
1
2
2
AUD_AGND
5V_S5 X02-0314 stuff EC9722 PWR_3D3V_DCBATOUT 3D3V_S5 1D5V_S3 VCC_GFXCORE
B B
X01-0208 add EC9742~EC9746
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
EC9732
1
EC9720
EC9721
EC9722
EC9723
EC9724
EC9725
EC9726
EC9727
EC9728
EC9729
EC9730
EC9731
1
1
DY DY DY DY DY DY DY
2
2
12/15 Stuff EC9727

VCC_CORE 1D05V_VTT 5V_S5 BT+
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
EC9733
EC9734
EC9735
EC9736
EC9737
EC9740
EC9741
1
1
EC9738
EC9739
1
1
2
2
2
3D3V_S5
12/6 Add EMI capacities
12/17 Add EC9741
12/20 change EMI caps to 0402 package
A <Core Design> A
Wistron Corporation
Title
UNUSED PARTS/EMI Capacitors

A3
5 4 3 2 1
5 4 3 2 1
Huron River Platform Power Sequence

(AC mode) red word: KBC GPIO
(DC mode) red word: KBC GPIO
+RTC_VCC
+RTC_VCC T1 >9ms
T1 >9ms
RTC_RST#
RTC_RST#
DCBATOUT
DCBATOUT T2
T2
Within logic high level and disable if
3D3V_AUX_S5
it is less than the logic low level.
3D3V_AUX_S5
KBC GPIO34 control power on by 3V_5V_EN
D D
S5_ENABLE Sense the power button status
Press Power button
KBC_PWRBTN# Platform to KBC PSL_IN2
5V_S5 T3
V5REF_Sus must be powered up before EC_ENABLE#_1(GPIO31) keep low
VccSus3_3, or after VccSus3_3 within
0.7 V. Also, V5REF_Sus must power
3D3V_S5 T4 3D3V_AUX_KBC
down after VccSus3_3, or before
T3 KBC GPIO34 control power on by 3V_5V_EN
VccSus3_3 within 0.7 V.
+5VA_PCH_VCC5REFSUS T5 S5_ENABLE
KBC GPIO43 to PCH
PM_RSMRST#(EC Delay 40ms) T6 >10ms 5V_S5 T4
PCH to KBC GPIO00 V5REF_Sus must be powered up before
+5V_ALW & +3.3V_ALW need meet 0.7V difference
VccSus3_3, or after VccSus3_3 within
PCH_SUSCLK_KBC T7 >5ms 0.7 V. Also, V5REF_Sus must power
3D3V_S5 T5
KBC GPO84 to PCH down after VccSus3_3, or before
+5V_ALW & +3.3V_ALW need meet 0.7V difference
Not floating. VccSus3_3 within 0.7 V.
AC_PRESENT 0ms<T8 <90ms +5VA_PCH_VCC5REFSUS T6
T7 >16ms KBC GPIO20 to PCH

Press Power button
3D3V_AUX_KBC PM_PWRBTN#
Platform to KBC PSL_IN2
Sense the power button status
AC KBC_PWRBTN#
KBC GPIO43 to PCH
This signal has an internal T9 >16ms PM_RSMRST# T8 >10ms
pull-up resistor and has an KBC GPIO20 to PCH
internal 16 ms de-bounce on the PCH to KBC GPIO00
input. AC PM_PWRBTN#
PCH_SUSCLK_KBC T9 >5ms
AC PM_PWRBTN# DC PCH_RSMRST#
T10 T10
PCH to KBC GPIO44 PCH to KBC GPIO44
PM_SLP_S4# PM_SLP_S4#
T11 PCH to KBC GPIO01 T11 PCH to KBC GPIO01
PM_SLP_S3# >30us PM_SLP_S3# >30us
KBC GPIO23 to LAN KBC GPIO23 to LAN
PM_LAN_ENABLE PM_LAN_ENABLE
Enable by PM_SLP_S4# Enable by PM_SLP_S4#
1D5V_S3 T12 1D5V_S3 T12
DDR_VREF_S3(0.75V) T13 DDR_VREF_S3(0.75V) T13

C
+5V_RUN & +3.3V_RUN need meet 0.7V difference +5V_RUN & +3.3V_RUN need meet 0.7V difference C
5V_S0 T14 5V_S0 T14
V5REF must be powered up before 3D3V_S0 T15 V5REF must be powered up before 3D3V_S0 T15
Vcc3_3, or after Vcc3_3 within 0.7 V. Vcc3_3, or after Vcc3_3 within 0.7 V.
Also, V5REF must power down after Also, V5REF must power down after
Vcc3_3, or before Vcc3_3 within 0.7 V. Vcc3_3, or before Vcc3_3 within 0.7 V.
+5VS_PCH_VCC5REF T16 +5VS_PCH_VCC5REF T16
1D5V_S0 T17 1D5V_S0 T17
1D8V_S0 T18 1D8V_S0 T18
0D75V_S0 T19 0D75V_S0 T19

1D8V_S0 & 1D5V_S3 power ready 1D8V_S0 & 1D5V_S3 power ready
RUNPWROK T20 RUNPWROK T20
1D05V_VTT T21 1D05V_VTT T21

VT357FCX PGOOD VT357FCX PGOOD
1.05VTT_PWRGD T22 1.05VTT_PWRGD T22
0D85V_S0 T23 0D85V_S0 T23
0D85V_S0 0D85V_S0
T24 TPS51461RGER PGOOD T24 TPS51461RGER PGOOD
D85V_PWRGD D85V_PWRGD
CPU SVID BUS SetVID ACK SetVID ACK

50us< T25 <2000us CPU SVID BUS 50us< T25 <2000us
VCC_CORE VCC_CORE
VCC_GFXCORE VCC_GFXCORE
T26 T26
<5ms
ISL95831 PGOOD to system <5ms
ISL95831 PGOOD to system
IMVP_PWRGD IMVP_PWRGD
CLK_EXP_P CLK_EXP_P
ALL_SYS_PWRGD=D85V_PWRGD ALL_SYS_PWRGD=D85V_PWRGD
B This signal represents the Power T27 >99ms KBC GPIO77 to PCH This signal represents the Power T27 >99ms KBC GPIO77 to PCH B
Good for all the non-CORE and Good for all the non-CORE and
non-graphics power rails.
PWROK non-graphics power rails.
PWROK
T28 >0us T28 >0us
D85V_PWRGD D85V_PWRGD
2ms< T29 <650ms PCH to CPU 2ms< T29 <650ms PCH to CPU
VDDPWRGOOD VDDPWRGOOD
T30 >1ms T30 >1ms
T31 >2ms T31 >2ms
1D8V_S0 1D8V_S0
5ms< T32 <650ms PCH to CPU 5ms< T32 <650ms PCH to CPU
H_CPUPWRGD H_CPUPWRGD
SYS_PWROK T33 >0ms SYS_PWROK T33 >0ms

T34 >1ms+60us T34 >1ms+60us
1ms< T35 <100ms PCH to all system 1ms< T35 <100ms PCH to all system
PLT_RST# PLT_RST#
T36 <200us T36 <200us
DMI DMI
Robson XT Power-Up/Down Sequence
3D3V_S0
PCH GPIO54 output
DGPU_PWR_EN#(Discrete only)
3D3V_VGA_S0(Discrete only)
3D3V_VGA_S0 above VT357 VIH
8209A_EN/DEM_VGA(Discrete only)
A
VGA_CORE(Discrete only) Ta >0ms A
1V_VGA_S0(Discrete only)
RT9035 PGOOD
9035_PGOOD_1V(Discrete only)
Tb >0ms
1D8V_VGA_S0(Discrete only)
Tc >0ms
VT357 PGOOD
DGPU_PWROK(Discrete only) <Core Design>
1D5V_VGA_S0(Discrete only) Td <20ms Wistron Corporation

Title
For power-down, reversing the ramp-up sequence is recommended.
Power Sequence
A1
5 4 3 2 1
5 4 3 2 1
Wistron HURON RIVER POWER UP SEQUENCE DIAGRAM

5V_S5 DCBATOUT
-6
AC AD+
Adapter in
Page38
-3.1 -3.1 -3.1
VDDP VIN 1D5V_S3
D PWR_5V3D3V_ENC 3V_5V_EN S5_ENABLE VOUT D
3
PM_SLP_S4#
EN
-3.2 -3.3 DDR_VREF_S3
PWR_CHG_ACOK REF
SWITCH ENC 5V_S5 15V_S5
LL1 PUMP
Page40
3D3V_S5 TPS51116RGER
LL2
0D75V_S0
5V_AUX_S5 VTT
RT8223MGQW VREG5
DC/DC 3D3V_AUX_S5 -5
-6.1 (3V/5V) VREG3 3 RUNPWROK
PGD
DCBATOUT 3V_5V_POK PM_SLP_S4#

VIN PGOOD -2 Page46
5
Page41
4 5V_S5 3D3V_S5
DC BQ24745 5V_S0
BT+ PM_SLP_S3#
Battery Charger SWITCH
Page39 -3 BJT Page37
3D3V_AUX_KBC -3.1 VDD VIN 1D8V_S0
VOUT
Page40 ACOK 3D3V_S0 4
S5_ENABLE SWITCH
-4 Page37 PM_SLP_S3# TPS53311RGTR
EN
RUNPWROK
AC_IN# GPIO34 PGD
GPIO70 1D5V_S0
Page47
C SWITCH C
Page37 5
1 SLP_S4# SLP_S3#
-1 KBC
KBC_PWRBTN#
GPIO6 NPCE795P -2.1
11 AND GATE
Power Button PM_RSMRST# 0D75V_EN
PM_SLP_S4# GPIO43 RSMRST# B VDDPWRGOOD
GPIO44 PM_PWRBTN# PM_DRAM_PWRGD Y SM_DRAMPWROK
PM_SLP_S3# GPIO20 PWRBTN# DRAMPWRGD A
GPIO01
2 H_CPUPWRGD H_CPUPWRGD_R
PROCPWRGD UNCOREPWRGOOD
Page27 Cougar Point 12
GPIO77 PCH Sandy Bridge
13 CPU
S0_PWR_GOOD
APWROK
PWROK PLT_RST# BUF_CPU_RST#
PLTRST# RSTIN#
SYS_PWROK SVID
SYS_PWROK
SVID
10
8
5V_S5 DCBATOUT
B B
V5IN VIN 1D05_VTT
VOUT
5 AND GATE 10
S0_PWR_GOOD
RUNPWROK TPS51218DSCR A SYS_PWROK
EN 1.05VTT_PWRGD IMVP_PWRGD Y
Page45 PGOOD B
5V_S5 DCBATOUT 5a
VDDP VIN 0D85_S0 -5

VOUT
5a -7 3D3V_AUX_S5
1.05VTT_PWRGD RT8208BGQW RTC_AUX_S5
EN D85V_PWRGD
Page48 PGOOD -8
+RTC_VCC
6
DCBATOUT
RTC battery
8 VIN VCC_CORE
OUTPUT
SVID
A
SVID
VR OUTPUT VCC_GFXCORE A
6 7 ISL95831HRTZ
D85V_PWRGD IMVP_VR_ON 9 DN15ATI Whistler
VR_ON IMVP_PWRGD
Page42 & 43 & 44 PGOOD
Wistron Corporation
Power Up Sequence: -8 ~ 13 Title

Power Sequence Diagram
Rev
A2
5 4 3 2 1
5 4 3 2 1
DCBATOUT
Adapter
TPS51218DSCR TPS51216RUKR RT8208BGQW

D AO4407A D
Charger
BQ24707 1D05V_VTT
Battery +PBATT 1D5V_S3 0D75V_S0 VGA_CORE
APL5916
0D85V_S0
RT9035 TPCA8062
1V_VGA_S0 1D5V_S0
C C
TPS51125ARGER
15V_S5 3D3V_AUX_S5 5V_AUX_S5 5V_S5 3D3V_S5
G547F2P81 AO4468 VT1316+VT1317 VT1317 AO4468

AO3403
TPS51311
5V_USB2_S0 5V_S0 3D3V_S0

3D3V_LAN_S5
1D8V_S0
VCC_CORE VCC_GFXCORE
B B
AO4468
ODD_PWR_5V G5285T11 RTS5138 DMP2130L

1D8V_VGA_S0
LCDVDD 3D3V_CARD_S0 3D3V_VGA_S0
Power Shape
Regulator LDO Switch Wistron Corporation

Title

Power Block Diagram Rev
A3
5 4 3 2 1
A B C D E
3D3V_S0 KBC SMBus Block Diagram


PCH SMBus Block Diagram SRN10KJ-5-GP
TouchPad Conn.


PSDAT1 TPDATA TPDATA TPDATA
1 PSCLK1 TPCLK TPCLK TPCLK 1
3D3V_AUX_KBC

3D3V_S0 5V_HDMI
PCH  
SRN4K7J-8-GP
SRN100J-3-GP Battery Conn.

SRN2K2J-1-GP 3D3V_S0 GPIO17/SCL1 BAT_SCL BATA_SCL_1 CLK_SMB
 SRN1K5J-GP GPIO22/SDA1 BAT_SDA BATA_SDA_1 DAT_SMB SMBus address:16
SRN0J-6-GP
SDVO_CTRLCLK PCH_HDMI_CLK DDC_CLK_HDMI

HDMI CONN BQ24745
SDVO_CTRLDATA PCH_HDMI_DATA DDC_DATA_HDMI
KBC SCL
SDA
SMBus address:12
2N7002SPT
NPCE795P
3D3V_S0
 GPU Seymou -XT

3D3V_S0
SML1_CLK GPIO_VGA_04_CLK GPIO_3_SMBDATA
 GPIO_VGA_03_DATA GPIO_4_SMBCLK 2
SRN2K2J-1-GP 2N7002SPT
SML1_DATA


L_DDC_CLK LVDS_DDC_CLK_R CLK
L_DDC_DATA LVDS_DDC_DATA_R DATA

LCD CONN GPIO73/SCL2 SML1_CLK SCL
GPIO74/SDA2 SML1_DATA SDA PCH

CRT_DDC_CLK CRT_DDC_CLK
CRT_DDC_DATA CRT_DDC_DATA
3D3V_S0 5V_S0
 
3D3V_S5 3D3V_S0
3D3V_S0  

SRN2K2J-1-GP
SRN2K2J-1-GP SRN10KJ-6-GP
PCH 3D3V_S0
 SRN2K2J-1-GP
  
SRN0J-6-GP
DIMM 1
    
CRT_DDCCLK_CON
VGA CRT CONN

 
3 CRT_DDCDATA_CON SMBCLK SMB_CLK PCH_SMBCLK 3
SCL
SMBDATA SMB_DATA PCH_SMBDATA SDA
3D3V_S5
2N7002DW-1-GP
SMBus Address:A0
 SRN2K2J-8-GP
2N7002SPT
3D3V_S5
DDC1CLK CRT_GFX_DDCCLK
SRN0J-6-GP
DDC_CLK_CON NPCE795 
CRT_GFX_DDCDAT DDC_DATA_CON SML1CLK SML1_CLK GPIO73/SCL2
DDC1DATA
DIMM 2

SML1DATA SML1_DATA GPIO74/SDA2
DIS_CRT SRN2K2J-1-GP

PCH_SMBCLK
SCL
SML0CLK SML0_CLK PCH_SMBDATA SDA
SML0DATA SML0_DATA
SMBus Address:A4
Minicard
PCH_SMBCLK
SMB_CLK
PCH_SMBDATA SMB_DATA
4 4
DN15ATI Whistler
Wistron Corporation
Title
SMBUS Block Diagram

A B C D E
A B C D E
Thermal Block Diagram Audio Block Diagram

1 1
SPKR_PORT_D_L-
PAGE28 DXP P2800_DXP SPKR_PORT_D_R+ SPEAKER

MMBT3904-3-GP
SC2200P50V2KX-2GP
DXN P2800_DXN
UMA Place near CPU
Codec
Thermal PWM CORE
92HD79B1
P2800 HP1_PORT_B_L HP
MMBT3904-3-GP HP1_PORT_B_R
PAGE27 GPIO5 SYS_THRM TDR T8

OUT
2
KBC GPIO92 CPU_THRM TDL
OTZ THERM_SYS_SHDN#
2N7002
D
PURE_HW_SHUTDOWN#
EN 3V/5V 2
NPCE795P S
G
IMVP_PWRGD PGOD
VR
Put under CPU(T8 HW shutdown)
GPIO94 GPIO56
GPIO4 VGA_THRM TDR
PAGE28
HP0_PORT_A_L MIC
P2800_VGA_DXP HP0_PORT_A_R
DXP THRMDA
VREFOUT_A_OR_F IN
FAN_TACH1
SC2200P50V2KX-2GP SC2200P50V2KX-2GP
VGA DXN
P2800_VGA_DXN
THRMDC
VGA
Thermal
FAN1_DAC
TACH Place near GPU(DISCRETE only).

P2800
FAN
VIN
MMBT3904-3-GP DMIC_CLK/GPIO1 Digital
5V
3
DMIC0/GPIO2
MIC 3
PH
OTZ
VSET VOUT
VIN
FAN CONTROL
P2793 PORTC_L
PAGE28 PORTC_R
Analog
VREFOUT_C MIC
4 4
DN15ATI Whistler
Wistron Corporation
Title
Size
Thermal/Audio Block Diagram
Document Number Rev
Custom
A B C D E
5 4 3 2 1
DATA PAGE Change Description Version
12/28 85 dummy VGA thermal circuit X01
12/28 86 modify to DGPU_PWROK X01
12/28 86 add capacity for BIF_VDDC X01

D D
12/28 93 dummy PR9326 X01
1/14 93 modify CS#, WP# X01
1/27 5 Add C504 for noise couple. X01
1/27 8 Stuff C812, C822, C831, C834 for VCC core noise issue. X01
1/27 27 Del R2757 to follow standard 10mW circuit X01
1/27 31 change Q3101 base power rail for leakage issue. X01
1/27 40 X01-0127 DY PQ4007, PR4038, PR4039 for new version BQ24707 X01
2/8 21 Add RN2101, R2127 for LPC EA result X01
2/8 27 Dummy R2769 X01
C 2/8 50 change R5002, R5003 to 33R X01 C
2/8 69 TPAD1 to 20.K0464.004 X01
2/8 27 change R5002, R5003 to 33R X01
2/8 97 add EC9742~EC9746 X01
2/8 97 stuff SPR1 and add SPR2 X01
2/9 28 dummy U2805 circuit X01
2/9 46 PT4603 UMA-->220uF DIS-->470uF X01
2/9 48 dummy PC4809 for BBU result. X01
2/10 5 Merge R512 R514 X01
2/10 21 change RN2101 to RN2104 RN2105 X01

B B
2/10 27 change R2724 to meet X01 PCB ver X01
2/10 46 del PT4602 X01
2/10 46 change PC4610 from 0.22uF to 10uF X01
2/10 97 add SPR3 X01
2/10 21 Merge R5115 R2116 X01
2/11 31 add C3122 for soft-sart X01
2/11 59 Add EMI solution for Surge X01
2/11 19,27 Change R1925, R1924, R1906, R1913, R2720, R2758, R2759, R2760 to short-pad X01
2/14 82 add AFTP8201~8210 X01
Wistron Corporation
Title
Change History
A3
5 4 3 2 1
5 4 3 2 1
0212 40 Change charger IC to new version X01
0302 31 Dummy PCIE_CLK_LAN_REQ# circuit X02
0302 86 Add R8605, R8609 PU 5V for lower Rdson X02

14,15,17,18
D 0303 19,22,23,24 Change R1404, R1405,R1504, R1503,RN1704, R1807, R1903, R1910, R1912, R2214, R2304, R2305, R2306, R2307, R2404, R2405, R2406, R2409, R2702, R2735,R2762, R2756, X02 D
27,29,31,36 R2911,R2914, R2917, R3104, R3115, R3117, R3614, R3710, RN5010, RN5117, R6811, R6813, R6804, R6805 0R to short pad
37,50,51,68
0309 86 Change AFTP test point to follow DV14 AMD X02
0310 41,45,92,97 Stuff PC4120, EC4501, PC9205, EC9708, EC9709, EC9714, EC9715, EC9716, EC9717, EC9718, EC9720, EC9724, EC9725, EC9740 X02
0311 28 Add R2816& R2817 to option VGA_THRM and DY the circuit X02
0311 83 Change R8316, R8331 to short pad X02
0311 59 Change GDT5901& GDT5902 to GD5901& GD5902 X02
0311 18 dummy R1804 X02
0311 31 add rest circuit to provent leakage. X02
0311 32 Stuff TR3201 and change symbol to 68.00201.141 X02

C C
0314 38 Del short pad PAD1 to prevent system burn. X02
0314 97 Stuff SPR2 X02
0314 61,97 Stuff EC9722,C6106 X02
0314 36 Change U3606 footprint. X02
0315 58 Change MIC2 to 20.F1889.002 X02
0315 88,89 Modify VRAM property PN and footprint X02
0315 32,59 Modify part reference problem of ER5912& TR3201. X02
0316 68 Modify WLED1 cirucit for brightness. A00
0320 31 Change R3118 for LOM power sequence A00
B
0320 49 Change TR4901 to 120ohm. A00 B
0320 61 Change TR601 120ohm. A00
0320 68 Change resistor for LED brightness A00
0320 82 Change TR8201, TR8202 to 120ohm. A00
0320 83 Dummy R8302 for disable de-emphasis A00
0329 27 change R2735 to 10R and C2711 to 220p A00
0329 68 Change R6814 to 10KR A00
0406 97 Dummy SPR2 A00

32, 49, 61,
0406 65,82 Remove R3206, R3207, R4903, R4904, R6102, R6103, TR6501, R8201, R8202, R8203, R8204 PAD A00
DN15ATI Whistler
A A
Wistron Corporation
Title
Change History
A3
5 4 3 2 1
5 4 3 2 1
0407 51 remove HDMI common mode choke PAD A00
0408 49,61,82 Swap TR4901, TR6101, TR8201, TR8202 net for layout A00
0408 49 Add RN4903 for ESD issue. A00
D 0408 56 Add R5606 to pull high 3.3V_S0 and change R5605 pull high to 3.3V_S0 A00 D
0412 40 Change PR4027 to 19.6K Change PR4029 to 54.9K Change PR4013 to 49.9K A00
0412 40 Dummy PR4037 and stuff PR4030, PR4032, PQ4005 A00
0412 97 dummy H12, H13 for remove PCH Heatsink A00
5,28,29,31
0412 50,65,85 Change R504,R2807,R3105, R6505, R6506, R8601,R2902,R2903,R2904,R8440,R8517,R8711,R8713,R8714,R8715,R8716,RN2010,RN2012,RN2014,RN2016,,RN5007,RN5008 to short-PAD A00
84,86,87
0412 21,29 Change ER2111,ER2930 to short-PAD A00
41,42,45
0412 46,47,48 Change PR4121,PR4122,PR4125,PR4217,PR4218,PR4219,PR4220,PR4254,PR4502,PR4607,PR4801,PR4803,PR4711,PR9311,PR9320,PR9327,PR4712 to short-PAD A00
93
0413 97 change H12 to 34.4HL17.001 A00

C C
0413 27 change R2724 to 47K for PCB ver
0413 68 change R6806, R6812, R6801, R6808 to 330ohm

41,,45,47
0413 89,93 Change close-GAP to green cover-GAP
0413 28 update P2800 thermal option.
0413 20 SWAP RN2014 net for layout
B B
A A
Title
<Title>

A3 <Doc> A00

5 4 3 2 1

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5 4 3 2 1

Muxless/UMA Schematics Document D

DIS: MUXLESS solution installed.

##OnMainBoard Block Diagram SYSTEM DC/DC

VRAM gDDR3 900NHz

gDDR3 Revision : 10315-SC SYSTEM DC/DC

PCIE x 1 Mini-Card DCBATOUT VCC_GFXCORE

USB Table SMBus ADDRESSES

12 CAMERA Table of Content

PCI EXPRESS* - GRAPHICS

D 62R2J-GP SRN1KJ-7-GP X01-0210 MergeR512 R514 D

JTAG & BPM

22,36 H_CPUPWRGD 1R504 2H_CPUPWRGD_R TDI AR28 XDP_TDI

19 XDP_DBRESET# XDP_DBRESET# 1 2 R516

DDR SYSTEM MEMORY B

M_A_DQ33 SA_DQ32 SA_ODT3 M_B_DQ33 SB_DQ32 SB_ODT3

RSVD#G25 RSVD#AK32 R705

PEG AND DDR

AD33 VCC VCCIO F11

AD32 VCC VCCIO E14

AD31 VCC VCCIO E12

AC30 VCC VCCIO B14

AC29 VCC VCCIO B12

AC28 VCC VCCIO A14

Y35 VR_SVID_ALERT# R805 1 2 75R2J-1-GP

VCC H_CPU_SVIDCLK R806

V34 VCC VIDALERT# AJ29 1 VR_SVID_ALERT# 42

V33 AJ30 H_CPU_SVIDCLK

V32 AJ28 H_CPU_SVIDDAT

VAXG Output Decoupling Recommendation:

DDR3 -1.5V RAILS

AT35 VSS VSS AJ22

M_B_A9 85 for DM2 can't boot up issue(only DN15/DQ15)

M_B_A14 A13 CK0 SA0_DIM1

M_B_DQ12 22 199 SO-DIMMA TS Address is 0x34

M_B_DQ24 DQ23 VDD3 10KR2J-3-GP

M_B_DQ54 174 43 Layout Note:

M_B_DQ58 DQ57 VSS

15,37 DDR3_DRAMRST# 30 RESET#

M_A_DQ50 DQ49 VSS

169 DQS6# VSS 139

M_A_DQS#7 186 144

M_A_DQS1 DQS0 VSS

Digital Display Interface

EC1802 EC1801 EC1803

KBC CLK EMI P/N: ND27V

X02-0303 change 0R to short pad OC[3:0]# for Device 29 (Ports 0-7)

5,27,31,65,71,83 PLT_RST# 1 R1807 2 PCI_PLTRST#

R1816 RN1802 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

USB_OC#10_11 3 8 USB_OC#12_13 Title

System Power Management

27 SUS_PWR_ACK K16 SUSWARN#/SUSPWRDNACK/GPIO30 SLP_S3# F4 PM_SLP_S3# 27,36,37,47 RTC_AUX_S5

27 PM_PWRBTN# E20 G10 PM_SLP_A# 1

27 AC_PRESENT H20 G16 PM_SLP_SUS# 1

PM_RI# A10 K14 PM_SLP_LAN# 1

CLKOUT_PCIE7P CLK_48_USB30 R2016 1

2 3 C37 LPC_AD3_R 2 3 LPC_AD3

29 HDA_SPKR T10 SPKR SATA1RXN AM10

AB13 SATA3_COMP R2113 1 2 49D9R2F-GP

+3VS_+1.5VS_HDA_IO 1 2 PCH_SPI_CLK T3 AH1 RBIAS_SATA3 R2114 1 2 750R2F-GP

11/1 Add R2111 for EMI request COUGAR-GP-U2-NF

G 12/6 Separate RN2103 to

HDA_CODEC_SYNC S 33R2J-2-GP 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,