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Set 7
Opamp Design
References: “Analog Integrated Circuit Design” by D. Johns and K. Martin
and “Design of Analog CMOS Integrated Circuits” by B. Razavi
All figures in this set of slides are taken from the above books
Shahriar Mirabbasi
Department of Electrical and Computer Engineering
University of British Columbia
shahriar@ece.ubc.ca
SM 1
EECE488 Set 7 - Opamp Design
General Considerations
• Gain
• Small-signal bandwidth
• Large-signal performance
• Output swing
• Input common-mode range
• Linearity
• Noise/offset
• Supply rejection
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EECE488 Set 7 - Opamp Design
One-Stage Op Amps
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EECE488 Set 7 - Opamp Design
One-Stage Op Amp in Unity Gain
Configuration
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EECE488 Set 7 - Opamp Design
Cascode Op Amps
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EECE488 Set 7 - Opamp Design
Unity Gain One Stage Cascode
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EECE488 Set 7 - Opamp Design
Folded Cascode Op Amps
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EECE488 Set 7 - Opamp Design
Folded Cascode Stages
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EECE488 Set 7 - Opamp Design
Folded Cascode (cont.)
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EECE488 Set 7 - Opamp Design
Folded Cascode (cont.)
| Av |≈ gm1 {[(gm 3 + gmb3 )ro3 (ro1 || ro5 )]||[(gm 7 + gmb 7 )ro7 ro9 ]}
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EECE488 Set 7 - Opamp Design
Telescopic versus Folded Cascode
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EECE488 Set 7 - Opamp Design
Example Folded-Cascode Op Amp
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EECE488 Set 7 - Opamp Design
Single-Ended Output Cascode Op Amps
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EECE488 Set 7 - Opamp Design
Triple Cascode
Av app. (gmro)3/2
Complex biasing
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EECE488 Set 7 - Opamp Design
Output Impedance Enhancement
Rout = A1 g m 2 ro 2 ro1
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EECE488 Set 7 - Opamp Design
Gain Boosting in Cascode Stage
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EECE488 Set 7 - Opamp Design
Differential Gain Boosting
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EECE488 Set 7 - Opamp Design
Differential Gain Boosting
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EECE488 Set 7 - Opamp Design
Differential Gain Boosting
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EECE488 Set 7 - Opamp Design
Two-Stage Op Amps
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EECE488 Set 7 - Opamp Design
Single-Ended Output Two-Stage Op Amp
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EECE488 Set 7 - Opamp Design
Two-Stage CMOS Opamp
• Popular opamp design approach
• A good example to review many important design concepts
• Output buffer is typically used to drive resistive loads
• For capacitive loads (typical case in CMOS) buffer is not
required.
C
c
V in A1 – A2 1 V
out
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EECE488 Set 7 - Opamp Design
Two-Stage CMOS Opamp Example
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EECE488 Set 7 - Opamp Design
Gain of the Opamp
• First Stage
Differential to single-ended
• Second Stage
Common-source stage
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EECE488 Set 7 - Opamp Design
Gain of the Opamp
Third Stage
• Source follower
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EECE488 Set 7 - Opamp Design
Frequency Response
Q5
300
Vbias
vin+
Q1 Q2
vin– 300 300
CC
v1 v2
A3 ≅ 1
–A2 A3 vout
150
150 i = g m1 vin
Ceq = CC ( 1 + A 2 )
Q3 Q4
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EECE488 Set 7 - Opamp Design
Frequency Response
Simplifying assumptions:
• CC dominates
• Ignore Q16 for the time being (it is used for lead compensation)
• At midband frequencies
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EECE488 Set 7 - Opamp Design
Frequency Response
• Overall gain (assuming A3 ≈1)
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EECE488 Set 7 - Opamp Design
Frequency Response
• First-order model
20 log ( A1 A 2 )
Gain – 20 dB/decade
(dB)
ω ta ≅ gm 1 ⁄ C C
0 Freq
ωp 1 ω ta (log)
ωp 1
0 Freq
Phase ω ta
(log)
(degrees)
– 90
– 180
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EECE488 Set 7 - Opamp Design
Slew Rate
• Maximum rate of output change when input signal is large.
Q5
300
Vbias
vin+
Q1 Q2
vin– 300 300
CC
v1 v2
A3 ≅ 1
–A2 A3 vout
150
150 i = g m1 vin
Q3 Q4
• All the bias current of Q5 goes either into Q1 or Q2.
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EECE488 Set 7 - Opamp Design
Slew Rate
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EECE488 Set 7 - Opamp Design
Slew Rate
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EECE488 Set 7 - Opamp Design
Systematic Offset Voltage
• To ensure inherent (systematic) offset voltage does not exist,
nominal current through Q7 should equal to that of Q6 when the
differential input is zero.
Q5 VDD Q6
Vbias 300
300
I b ia s
Q1 Q2
Vin – 300 300
Vin +
Vo ut
300
150 150
Q3 Q4 Q7
VSS
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EECE488 Set 7 - Opamp Design
Systematic Offset Voltage
• Avoid systematic offset by choosing:
• Found by noting
and
then setting
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EECE488 Set 7 - Opamp Design
N-Channel versus P-Channel Input Stage
• Complimentary opamp can be designed with an n-channel input
differential pair and p-channel second-stage
• Overall gain would be roughly the same in both designs
P-channel Advantages
• Higher slew-rate: for fixed bias current, Veff is larger (assuming
similar widths used for maximum gain)
• Higher frequency of operation: higher transconductance of
second stage which results in higher unity-gain frequency
• Lower 1/f noise: holes less likely to be trapped; p-channel
transistors have lower 1/f noise
• N-channel source follower is preferable (less voltage drop and
higher gm)
N-channel Advantage
• Lower thermal noise — thermal noise is lowered by high
transconductance of first stage
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EECE488 Set 7 - Opamp Design
Feedback and Opamp Compensation
Y H ( s)
( s) =
X 1 + βH ( s )
| βH ( jω ) |= 1
∠βH ( jω ) = −180
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EECE488 Set 7 - Opamp Design
Stable and Unstable Systems
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EECE488 Set 7 - Opamp Design
Time-domain response of a feedback system
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EECE488 Set 7 - Opamp Design
One-pole system
A0
H ( s) =
1+ s
ω0
A0
Y 1 + β A0
( s) =
X s
1+
ω 0 (1 + βA0 )
S p = −ω 0 (1 + β A0 )
Bode plot of the Loop gain
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EECE488 Set 7 - Opamp Design
Multi-pole system
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EECE488 Set 7 - Opamp Design
Phase Margin
(dB)
20 log (LG (j ω))
0 Freq
(log)
ωp 1 ωt
GM
(gain margin)
ωp 1 ωt
Phase Freq
0 (log)
Loop Gain
(degrees)
–90
PM
(phase margin)
–180
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EECE488 Set 7 - Opamp Design
Phase Margin
β H ( ω1 ) = 1× e − j175
Y 11.5
(s) =
X β
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EECE488 Set 7 - Opamp Design
Phase Margin (Cont.)
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EECE488 Set 7 - Opamp Design
Frequency Compensation
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EECE488 Set 7 - Opamp Design
Telescopic Opamp (single-ended) -example
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EECE488 Set 7 - Opamp Design
Compensation (Cont.)
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EECE488 Set 7 - Opamp Design
Compensation of a two-stage opamp
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EECE488 Set 7 - Opamp Design
Compensating Two-Stage Opamps
Q5 Q6
300 VDD
Vbias1 300
Q1 Q2
Vin- 300 300 Vin+ Vout2
Vbias2
Q16 Cc
300
150 150
Q3 Q4 Q7
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EECE488 Set 7 - Opamp Design
Compensating Two-Stage Opamps
v RC CC
1
g v R C1 g v R C2
m1 in 1 m7 1 2
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EECE488 Set 7 - Opamp Design
Compensating Two-Stage Opamps
• Using RC (through Q16) places zero at
• satisfied by letting
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EECE488 Set 7 - Opamp Design
Design Procedure
Design example: Find CC with RC=0 for a 55o phase margin
– Arbitrarily choose C’C=1pF and set RC=0
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EECE488 Set 7 - Opamp Design
Design Procedure
Next: Choose RC according to
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EECE488 Set 7 - Opamp Design
Design Procedure
Next: Replace RC by a transistor
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EECE488 Set 7 - Opamp Design
Process and Temperature Independence
• Can show non-dominant pole is roughly given by
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EECE488 Set 7 - Opamp Design
Process and Temperature Independence
• Need to ensure Veff16/Veff7 is independent of process and
temperature variations
Q11 Q6
Vbias 25 300
Q12
25
Va
25 Q16 CC
Q13
Vb 300
Q7
Vb
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EECE488 Set 7 - Opamp Design
Stable Transconductance Biasing
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EECE488 Set 7 - Opamp Design
Stable Transconductance Biasing
• Transconductance of Q13 (to the first order) is determined by
geometric ratios only.
• Independent of power-supply voltages, process parameters,
temperature, etc.
• For special case (W/L)15=4(W/L)13
gm13=1/RB
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EECE488 Set 7 - Opamp Design