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Digital Logic Design MCQs

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10/1/2018 PDB EBooks: Free ebook sample of "Digital Logic Design MCQs: Multiple Choice Questions and Answers (Quiz & Tests with Answe…
Multiple Choice Questions and Answers (Quiz & Tests

with Answer Keys)
By Arshad Iqbal
Table of Contents
Chapter 1: Algorithmic state machine

Chapter 2: Asynchronous sequential logic
Chapter 3: Binary Systems
Chapter 4: Boolean Algebra and Logic Gates
Chapter 5: Combinational logics
Chapter 6: Digital integrated circuits
Chapter 7: DLD Lab Equipment and experiments
Chapter 8: MSI and PLD components
Chapter 9: Registers counters and memory units
Chapter 10: Simplification of Boolean Functions
Chapter 11: Standard graphic symbols
Chapter 12: Synchronous Sequential Logics
Chapter 1
Algorithmic state machine
MCQ 1: State box without decision and conditional box is
A. ASM block
B. defined block
C. simple block
D. both a and b
MCQ 2: ASM chart resembles with
A. map
B. data
C. flowchart
D. operation
MCQ 3: Control sequence state is indicated by

A. state box
B. decision box
C. data box
D. conditional box
MCQ 4: Control information gives knowledge about the

A. command signals
B. data
C. metadata
D. operation
MCQ 5: If system is performing no function then it is in

A. clear state
B. initial state
C. enable state
D. reset state
MCQ 6: ASM chart has
A. 4 exits
B. 3 exits
C. 2 exits
D. any number of exits
MCQ 7: ASM chart is composed of
A. 2 elements
B. 3 elements
C. 4 elements
D. 5 elements
MCQ 8: In designing ASM with multiplexers, the registers hold

A. present binary state
B. input
C. next binary state

D. output
MCQ 9: All inputs are synchronized with

A. master clock
B. clock pulses
C. counter
D. latch
MCQ 10: A state table for a controller is a list of present states and inputs and their corresponding
A. Pervious states and output
B. next states and outputs

C. current states
D. None
MCQ 11: State box of ASM chart represents
A. condition
B. clock
C. state
D. pulse
MCQ 12: In state table when input pulses is greater than 5 it is necessary to use
A. Small maps
B. medium maps
C. Large maps
D. None
MCQ 13: One that is not present in the list of state table is
A. present state
B. input
C. next state
D. previous state
MCQ 14: Another possible method of control logic design is to use

A. 1 flip-flop
B. 2 flip-flop
C. 1 flip-flop per state
D. None
MCQ 15: Binary information is classified into
A. data
B. control information
C. metadata
D. both a and b
MCQ 16: Difference in conventional flowchart and ASM chart is

A. master clock
B. flow
C. time relationship
D. clock
MCQ 17: The logic design consists of
A. 1 part
B. 2 parts
C. 3 parts
D. 4 parts
MCQ 18: Design ASM with multiplexers, is the method consists of

A. 1 level
B. 2 levels
C. 3 levels
D. 4 levels
MCQ 19: Sequential circuit is also called
A. state
B. encoder
C. flip-flop
D. state machine
MCQ 20: ASM chart takes entire block as
A. 1 unit
B. 2 unit
C. 3 unit
D. 4 unit
MCQ 21: ASM chart is very same to
A. state diagram
B. flowchart
C. data box
D. operation
MCQ 22: To continue the count E must be
A. enabled
B. reset
C. stopped
D. cleared
MCQ 23: At E=1, register R will be

A. enabled
B. reset
C. stopped
D. cleared
MCQ 24: The rounded corners of conditional box differentiate it from
A. state box
B. decision box
C. data box
D. conditional box
MCQ 25: For going to the next state flip-flop is set to

A. 1
B. 0
C. y
D. don't cares
MCQ 26: Control implementation method is
A. practical
B. impractical
C. enabled
D. cleared
MCQ 27: The timing for all flip-flops in digital system is controlled by
A. Memory
B. latches
C. Master clock Generator
D. None
MCQ 28: Symbolic notation R←0 represents
A. Clear Register
B. Move register
C. Add contents to Register

D. None
MCQ 29: The first level of design with multiplexer determines the registers'
A. present state
B. input
C. next state
D. output
MCQ 30: The number of inputs and outputs in a state table are
A. equal
B. same
C. unequal
D. not present
MCQ 31: One that is a digital component is
A. latch
B. encoder
C. flip-flop
D. processor
MCQ 32: The third level of design with multiplexer consists of
A. Demultiplexer
B. mux
C. encoder
D. decoder
MCQ 33: ASM stands for
A. algorithmic state machine
B. algorithmic solid machine

C. arithmetic state machine
D. arithmetic solid machine
MCQ 34: In ASM design flip-flops are considered to be
A. negative edge triggered

B. negative level triggered
C. positive edge triggered
D. negative level triggered
MCQ 35: ASM chart has

A. 4 entrances
B. 3 entrances
C. 2 entrances
D. 1 entrance
MCQ 36: Discrete element of information is
A. data
B. control information
C. metadata
D. operation
MCQ 37: A method used to specify the sequence of algorithm is

A. map
B. data
C. flowchart
D. operation
MCQ 38: State box is a shape of
A. square
B. rectangle
C. rhombus
D. pentagon
MCQ 39: Conditional box has a shape of
A. square
B. rectangle
C. oval
D. pentagon
MCQ 40: One that is not a digital component is
A. decoder
B. encoder
C. flip-flop
D. mux
MCQ 41: With every clock pulse count is
A. decremented
B. stopped
C. incremented
D. enabled
MCQ 42: A command used to start signals operation is indicated by

A. INITIAL
B. GO
C. BEGIN
D. START
MCQ 43: Box that tells the effect of input on control subsystem is called
A. state box
B. decision box
C. data box
D. conditional box
MCQ 44: Symbolic notation A←B represents

A. Clear Register
B. Set Flip-flop
C. Increment register A
D. Transfer contents of register B into A

MCQ 45: Timings for registers are controlled by
A. master clock
B. slave clock
C. serial clock
D. parallel clock
MCQ 46: One that is not the element of ASM chart is
A. state box
B. decision box
C. data box
D. conditional box
MCQ 47: One that is not a type of register
A. storage
B. shift register
C. counter
D. latch
MCQ 48: Large maps are used if flip-flops and inputs become greater than
A. 2
B. 3
C. 5
D. 8
MCQ 49: The change of state in ASM chart is performed in

A. control logic
B. slave clock
C. metadata
D. processor
MCQ 50: Sequential operations in digital system are described by
A. map
B. ASM chart
C. flowchart
D. graph
Answers Key:
1. C
2. C
3. A
4. A
5. B
6. D
7. B
8. A
9. B
10. A
11. C
12. D
13. D
14. B
15. D
16. C
17. B
18. C
19. D
20. A
21. A
22. D
23. D
24. A
25. A
26. B
27. B
28. D
29. C
30. A
31. B
32. D
33. A
34. C
35. D
36. A
37. C
38. B
39. C
40. C
41. C
42. D
43. B
44. D
45. A
46. C
47. D
48. C
49. A
50. B
Chapter 2
Asynchronous sequential logic
MCQ 1: Asynchronous circuits are useful in application where the input signals may
A. change at any time
B. never change
C. both a and b
D. None
MCQ 2: The SR latch consists of

A. 1 input
B. 2 inputs
C. 3 inputs
D. 4 inputs
MCQ 3: Table that is not a part of asynchronous analysis procedure is
A. transition table
B. state table
C. flow table
D. excitation table
MCQ 4: The making of transition table consists of
A. 2 steps
B. 4 steps
C. 5 steps
D. 6 steps
MCQ 5: The output of SR latch is
A. x and y
B. a and b
C. s and r
D. q and q'
MCQ 6: In asynchronous circuit, the changes occur with the change of

A. input
B. output
C. clock pulse
D. time
MCQ 7: In synchronous circuits, present state is determined by
A. Unclocked flip-flops
B. clocked flip-flops
C. flip-flops
D. latches
MCQ 8: The present states and next state of asynchronous circuits are also called
A. secondary variables
B. primary variables
C. excitation variables
D. short term memory
MCQ 9: The race in which stable state depends on order is called

A. critical race
B. identical race
C. non critical race

D. defined race
MCQ 10: Unclocked flip-flops are called

A. Latches
B. register
C. Transition tables
D. None
MCQ 11: In primitive flow table for gated latch, each state has
A. 1 row
B. 2 rows
C. 3 rows
D. 4 rows
MCQ 12: In all the cases final stable state is
A. changed
B. same
C. inverted
D. undefined
MCQ 13: The complexity of asynchronous circuit is involved in timing problems of
A. inputs
B. outputs
C. clock pulses
D. feedback path
MCQ 14: Instability condition can be determined from
A. table
B. map
C. graph
D. logic diagram
MCQ 15: Transition table consists of
A. squares
B. rectangles
C. circles
D. oval
MCQ 16: A Condition occurs when an Asynchronous sequential circuit changes two or more
binary states variables
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Digital Logic Design MCQs

Multiple Choice Questions and Answers (Quiz & Tests

Chapter 1: Algorithmic state machine

Algorithmic state machine

MCQ 1: State box without decision and conditional box is

MCQ 3: Control sequence state is indicated by

MCQ 4: Control information gives knowledge about the

MCQ 5: If system is performing no function then it is in

MCQ 7: ASM chart is composed of

MCQ 8: In designing ASM with multiplexers, the registers hold

C. next binary state

MCQ 9: All inputs are synchronized with

A. Pervious states and output

B. next states and outputs

MCQ 14: Another possible method of control logic design is to use

MCQ 16: Difference in conventional flowchart and ASM chart is

MCQ 18: Design ASM with multiplexers, is the method consists of

MCQ 23: At E=1, register R will be

MCQ 25: For going to the next state flip-flop is set to

C. Add contents to Register

B. algorithmic solid machine

A. negative edge triggered

MCQ 35: ASM chart has

MCQ 37: A method used to specify the sequence of algorithm is

MCQ 42: A command used to start signals operation is indicated by

MCQ 44: Symbolic notation A←B represents

D. Transfer contents of register B into A

MCQ 46: One that is not the element of ASM chart is

MCQ 49: The change of state in ASM chart is performed in

MCQ 50: Sequential operations in digital system are described by

Asynchronous sequential logic

MCQ 2: The SR latch consists of

MCQ 3: Table that is not a part of asynchronous analysis procedure is

MCQ 6: In asynchronous circuit, the changes occur with the change of

D. short term memory

MCQ 9: The race in which stable state depends on order is called

C. non critical race

MCQ 10: Unclocked flip-flops are called

MCQ 13: The complexity of asynchronous circuit is involved in timing problems of

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