Sualaptop365.Edu - VN - Axioo Neon HNW W251HUQ (W240HUMB-0D)

Schematic Diagrams
System Block Diagram

CLICK BOARD
6 -7 1- W2 40 2-D 01
AUDIO BOARD
Huron River System Block Diagram VDD3,VDD5
U SB +E AR PH ONE +E XT .M IC
6 -7 1- C4 50 8-D 03
5V,3V,5VS,3VS,1.5VS,
1.5VS_CPU
POWER SWITCH BOARD Memory Termination
P OW ER S WI TCH +H OT KE Y X 3 Sandy Bridge 800/1067 MHz 1.5V,0.75VS(VTT_MEM)
6 -7 1- E5 1Q S-D 02 DDR3 / 1.5V 1.8VS
37.5*37.5 mm DDR3
EXTERNAL ODD BOARD SO-DIMM0
E XT . OD D PROCESSOR 1.05VS, 1.05VS_VTT
6 -7 1- E5 1Q N-D 01
SYSTEM SMBUS
rPGA989/988 0 .1 "~1 3 DDR3
SO-DIMM1
VCORE, 0.85VS
B.Schematic Diagrams
FDI DMI*4
HD MI 0. 5" ~6 .5 " <= 8" VGFX_CORE
CLICK BOARD AU DI O BO AR D
Sheet 1 of 43 T OU CH P AD
CR T CO NN EC TO R
<1 5"
CougarPoint
System Block S yn ap ti c
810602-1703 Platform
MIC
IN
HP
OUT
L CD C ON NE CT OR ,
Diagram <8 "
Controller
Hub (PCH) INT SPK R
32.768 KHz
Az al ia C od ec
EC INT SPK L
S PI T PM 25x25x0.6 mm ALC269/
IT E 85 18 E Sh ar e RO M VT1802P
128pins LQFP SHEET 23 989 Balls FCBGA Co-layout
14 *14*1 .6 mm 33 MHz INT MIC
LPC
0. 5" ~1 1" AZALIA LINK 24 MHz
I NT . K/ B EC SMBUS
PCIE <1 2" 100 MHz
TH ER MA L S MA RT S MA RT
SE NS OR F AN B AT TE RY
32.768KHz
W 83 L7 71 AW G
Mi ni P CI E Mi ni P CI E JMICRO
S OC KE T S OC KE T
< 12 "
USB2.0 3 G CA RD WL AN JMC251 C
SATA I/II 3.0Gb/s 480 Mbps ( US B9 ) ( US B2 )
LAN CARD READER 25
1" ~1 6" (Optional)
MH z
9 IN 1
RJ-45
SO CK ET
USB P OR T U SB P OR T US B PO RT C CD
S AT A HD D SA TA O DD NEC
(U SB 0) (U SB 1) ( US B9 ) (U SB 5)
uPD720200
USB3.0 IC
US B3 .0 A UD IO
(Optional) B OA RD
(Optional)
B - 2 System Block Diagram
http://sualaptop365.edu.vn
www.teknisi-indonesia.com
Schematic Diagrams
CPU 1/7 (DMI, PEG, FDI)

Sandy Bridge Processor 1/7
( DMI,PEG,FDI )
1 .0 5V S _V TT
U 3 4A 20 mil
J22 P E G_ C OM P R6 3 2 4 .9_ 1 % _ 04
P E G_ IC OM P I J21
B2 7 P E G_ I CO MP O H 22
[ 15 ] D MI_ T X N 0 B2 5 D MI_ RX # [0 ] P E G _R CO MP O
[ 15 ] D MI_ T X N 1 A2 5 D MI_ RX # [1 ]
[ 15 ] D MI_ T X N 2 B2 4 D MI_ RX # [2 ] K3 3
[ 15 ] D MI_ T X N 3 D MI_ RX # [3 ] P E G_ R X # [ 0 ] M 35
B2 8 P E G_ R X # [ 1 ] L34
[ 15 ] D MI_ T X P 0 B2 6 D MI_ RX [0 ] P E G_ R X # [ 2 ] J35
[ 15 ] D MI_ T X P 1 A2 4 D MI_ RX [1 ] P E G_ R X # [ 3 ] J32
[ 15 ] D MI_ T X P 2 B2 3 D MI_ RX [2 ] P E G_ R X # [ 4 ] H 34
[ 15 ] D MI_ T X P 3 D MI_ RX [3 ] P E G_ R X # [ 5 ] H 31
DMI
G2 1 P E G_ R X # [ 6 ] G 33
[ 15 ] D MI_ R XN 0 E2 2 D MI_ T X# [0 ] P E G_ R X # [ 7 ] G 30
[
[
15 ]
15 ]
D
D
MI_ R
MI_ R
XN
XN
1
2
F21 D MI_ T X# [1 ] P E G_ R X # [ 8 ] F35 Q1 7 SC70-5 & SC70-3 Co-lay
D2 1 D MI_ T X# [2 ] P E G_ R X # [ 9 ] E3 4 5 1
[ 15 ] D MI_ R XN 3 D MI_ T X# [3 ] P E G_ R X# [1 0 ] E3 2 G ND NC 2
G2 2 P E G_ R X# [1 1 ] D 33 GN D
[ 15 ] D MI_ R XP 0 D2 2 D MI_ T X[ 0] P E G_ R X# [1 2 ] D 31 4 3
[ 15 ] D MI_ R XP 1 F20 D MI_ T X[ 1] P E G_ R X# [1 3 ] B3 3 VC C V O
[ 15 ] D MI_ R XP 2 C2 1 D MI_ T X[ 2] P E G_ R X# [1 4 ] C 32 *T MP 2 0
[ 15 ] D MI_ R XP 3 D MI_ T X[ 3] P E G_ R X# [1 5 ] 3 .3 V
J33
PCI EXPRESS* - GRAPHICS

Q1 6
P E G_ RX [ 0 ] L35 2 1
P E G_ RX [ 1 ] VC C O UT 1: 2 (4 mi ls :8 mi ls ) T H E RM _ V OL T [2 7 ]
K3 4
A2 1 P E G_ RX [ 2 ] H 35 C9 9
[1 5 ] FD I_T X N 0 H1 9 FD I0 _T X # [0 ] P E G_ RX [ 3 ] H 32 3 C 10 0
[1 5 ] FD I_T X N 1 E1 9 FD I0 _T X # [1 ] P E G_ RX [ 4 ] G 34 G ND
0 .1 u_ 1 0 V _ X7 R _0 4
[1 5 ] FD I_T X N 2 F18 FD I0 _T X # [2 ] P E G_ RX [ 5 ] G 31
[1 5 ] FD I_T X N 3 G 71 1 S T 9 U 0 .1 u _1 0 V _ X 7R _ 04
B2 1 FD I0 _T X # [3 ] P E G_ RX [ 6 ] F33
[1 5 ] FD I_T X N 4 FD I1 _T X # [0 ] P E G_ RX [ 7 ] 1
C2 0 F30
3
Sheet 2 of 43
Intel(R) FDI
[1 5 ] FD I_T X N 5 FD I1 _T X # [1 ] P E G_ RX [ 8 ]
D1 8 E3 5
[1 5 ] FD I_T X N 6 E1 7 FD I1 _T X # [2 ] P E G_ RX [ 9 ] E3 3
[1 5 ] FD I_T X N 7 FD I1 _T X # [3 ] P E G_ R X [1 0 ]
A2 2
P E G_ R X [1 1 ]
P E G_ R X [1 2 ]
F32
D 34
E3 1
9/20
EVT
PLACE NEAR U3 2
CPU 1/7
[1 5 ] FD I_T X P 0 G1 9 FD I0 _T X [0 ] P E G_ R X [1 3 ] C 33
CAD NOTE: DP_COMPIO and ICOMPO signals

[1 5 ]
[1 5 ]
FD
FD
I_T X P 1
I_T X P 2
E2 0
G1 8
FD
FD
I0 _T X [1 ]
I0 _T X [2 ]
P E G_ R X [1 4 ]
P E G_ R X [1 5 ]
B3 2 (DMI, PEG, FDI)
should be shorted near balls and routed with [1 5 ] FD I_T X P 3 B2 0 FD I0 _T X [3 ] M 29
[1 5 ] FD I_T X P 4 C1 9 FD I1 _T X [0 ] P E G _ TX # [ 0 ] M 32
- typical impedance < 25 mohms [1 5 ] FD I_T X P 5 D1 9 FD I1 _T X [1 ] P E G _ TX # [ 1 ] M 31
[1 5 ] FD I_T X P 6 F17 FD I1 _T X [2 ] P E G _ TX # [ 2 ] L32
[1 5 ] FD I_T X P 7 FD I1 _T X [3 ] P E G _ TX # [ 3 ] L29
1 .05 V S _ V T T 1 . 0 5V S _ V TT J18 P E G _ TX # [ 4 ] K3 1
[1 5 ] F D I_ F S Y NC 0 J17 F D I0 _F S Y N C P E G _ TX # [ 5 ] K2 8
[1 5 ] F D I_ F S Y NC 1 F D I1 _F S Y N C P E G _ TX # [ 6 ] J30
H2 0 P E G _ TX # [ 7 ] J28
[ 1 5 ] F DI _IN T F D I_ INT P E G _ TX # [ 8 ] H 29
J19 P E G _ TX # [ 9 ] G 27
R 3 89 R3 9 0
[1 5 ] F D I_ L S Y NC 0 H1 7 F D I0 _L S Y N C P E G_ T X# [1 0 ] E2 9 On Board CPU Thermal Sensor
[1 5 ] F D I_ L S Y NC 1 F D I1 _L S Y N C P E G_ T X# [1 1 ] F27
1 K_ 0 4 24 .9 _ 1 %_ 0 4
P E G_ T X# [1 2 ] D 28 3.3 V
EDP Function Disable P E G_ T X# [1 3 ] F26
EDP_HPD: Pull-up10K- DISABLED P E G_ T X# [1 4 ]
P E G_ T X# [1 5 ]
E2 5 Analog Thermal Sensor
E DP _ C OM P A 1 8
A1 7 e D P _ C OM P IO M 28
DP Compensation Signal
E DP _ H P D # B 1 6 e D P _ IC OM P O P E G _T X [ 0 ] M 33 C9 7
e D P _ H P D# P E G _T X [ 1 ] M 30
D
PQ 4 7 P E G _T X [ 2 ] L31 *0 .1 u_ 1 6 V _ Y 5 V _ 0 4
G D P _ A U X_ P C 1 5 P E G _T X [ 3 ] L28
[1 1] E MB _ H P D * MT N7 0 0 2 Z H S 3 [1 1] DP _ A U XP C3 2 5 *0 . 1 u _1 0 V _ X 7R _ 04 U 11
C3 2 4 *0 . 1 u _1 0 V _ X 7R _ 04 D P _ A U X_ N D 1 5 e DP_ AU X P E G _T X [ 4 ] K3 0 1 4 R1 2 2 *1 0 m i _l 0 4
[1 1] DP _ A U XN e DP_ AU X# P E G _T X [ 5 ] K2 7 D +_ C P U 2 VD D TH E R M 6 C RIT _ T E MP _ R E P # [1 8 ]
S
P E G _T X [ 6 ] D+ AL ERT TS # _ D IMM 0_ 1 [9 ,1 0 ]
C
R3 8 8 J29
C1 7 P E G _T X [ 7 ] J27 B
eDP
*1 0 0 K _ 04 C3 3 0 *0 . 1 u _1 0 V _ X 7R _ 04 D P _ T XP _0 Q1 8
[1 1] DP _ T X P 0 C3 2 9 *0 . 1 u _1 0 V _ X 7R _ 04 D P _ T XP _1 F16 e D P _ T X [0 ] P E G _T X [ 8 ] H 28
[1 1] DP _ T X P 1 C1 6 e D P _ T X [1 ] P E G _T X [ 9 ] G 28 3 7
C3 2 7 *0 . 1 u _1 0 V _ X 7R _ 04 D P _ T XP _2 * 2N 3 9 04 D -_C P U
[1 1] DP _ T X P 2 D P _ T XP _3 G1 5 e D P _ T X [2 ] P E G _ TX [1 0 ] E2 8 5 D- SD AT A 8 S M D _ C P U _ T HE R M [1 4 , 2 7 ]
E
[1 1] DP _ T X P 3 C5 4 0 *0 . 1 u _1 0 V _ X 7R _ 04 S M C _ C P U _ T HE R M [1 4 , 2 7 ]
e D P _ T X [3 ] P E G _ TX [1 1 ] F28 G ND S CL K
D P _ T XN _0 C1 8 P E G _ TX [1 2 ] D 27
C3 3 1 *0 . 1 u _1 0 V _ X 7R _ 04 * W 8 3L 7 7 1 A W G
[1 1] DP _ T X N0 C3 2 8 *0 . 1 u _1 0 V _ X 7R _ 04 D P _ T XN _1 E1 6 e D P _ T X # [0] P E G _ TX [1 3 ] E2 6
[1 1] DP _ T X N1 D P _ T XN _2 D1 6 e D P _ T X # [1] P E G _ TX [1 4 ] D 25
C3 2 6 *0 . 1 u _1 0 V _ X 7R _ 04
[1 1] DP _ T X N2 C5 4 1 *0 . 1 u _1 0 V _ X 7R _ 04 D P _ T XN _3 F15 e D P _ T X # [2] P E G _ TX [1 5 ]
[1 1] DP _ T X N3 e D P _ T X # [3]
11/03 P Z 98 8 2 7- 36 4 B -0 1 F
[3 ,8 , 11 ,1 3 , 1 4, 15 , 1 7 ,1 8, 1 9 ,2 0 ,22 ,2 3 ,2 6 ,28 ,3 0 ,3 1,3 3 ,3 4 ,3 5] 3.3 V

[3 ,5, 18 , 1 9 ,2 0, 3 4 ,3 6 ] 1 .05 V S _V T T
CPU 1/7 (DMI, PEG, FDI) B - 3
Schematic Diagrams
CPU 2/7 (CLK, MISC, JTAG)

Processor Pullups/Pull downs
1 . 05 V S _ V T T
PU/PD for JTAG signals

1. 0 5 V S _ V T T
Sandy Bridge Processor 2/7 H _P R O C H O T #
H _C P U P W R G D _ R
R 41 0 62 _ 0 4
R 41 2 10 K _ 0 4
R
R
R
41 6
10 8
10 9
5 1 _ 04
5 1 _ 04
* 51 _ 0 4
XD
XD
XD
P _ TM S
P _ TD I _ R
P _ P RE Q #
( CLK,MISC,JTAG ) C 58 5 * 0. 1 u _ 10 V _ X 7 R _ 0 4
R 41 5 5 1 _ 04 XD P _ TD O_ R
11/0 3
R 41 4 5 1 _ 04 XD P _ TC L K U3 4 B
R 95 5 1 _ 04 XD P _ TR S T # TRA CE W ID TH 1 0MI L, L EN GT H < 50 0M IL S
A 28
[ 18 ] H _S N B _ I V B #
H_ S N B _ IV B # C 26
P RO C_ S E L E CT #
B C LK
BC L K#
A 27
C L K _ E XP _P
C L K _ E XP _N
[ 14 ]
[ 1 4]
DDR3 Compensation Signals
MISC
CLOCKS
3 . 3V S
AN 3 4 S M _ R C OMP _0 R 41 3 1 4 0_ 1 % _ 04
R 40 7 1 K_ 0 4 XD P _ D B R _R S K T OC C # A 16
D P L L _R E F _ S S C LK A 15 CL K _ DP _ P [1 4 ] S M _ R C OMP _1 R 38 2 2 5 . 5 _1 % _ 04
DP L L _ RE F _ S S C L K # C L K _ D P _ N [ 14 ]
S M _ R C OMP _2 R 38 1 2 0 0_ 1 % _ 04
H _ C A TE R R # AL 3 3
CA T E RR #
THERMAL
R4 1 1 *1 0 mi l _ 04 H_ P E C I_ R AN 3 3 R8 C P U D R A MR S T #
[ 1 8 , 27 ] H _ P E C I P E CI S M_ D R A MR S T #
DDR3
MISC
R4 0 5 5 6 _1 % _ 04 H _ P R OC H O T# _ D A L 3 2 AK1 S M_ R C O MP _ 0
[ 3 6] H _ P R O C H OT # P R O C H OT # S M _ R C OMP [ 0] A5 S M_ R C O MP _ 1
S M _ R C OMP [ 1] A4 S M_ R C O MP _ 2
If P RO CH OT # i s no t us ed, t he n it m ust
Sheet 3 of 43 be t er mi na ted w it h a 68- O +- 5% p ul l-u p AN 3 2
TH E R M T R I P #
S M _ R C OMP [ 2] S3 circuit:- DRAM PWR GOOD logic
re si st or t o 1 .0 5V S_ VT T .
CPU 2/7 [ 1 8 ] H _ T H R MT R I P # R4 1 7 *1 0 mi l _ 04 H _ T H R MT R I P #_ R
AP2 9 X DP _ P R DY # 3 . 3V 1 .5 V _ CP U
(CLK, MISC, JTAG) P R DY #
PREQ #
AP2 7
AR2 6
X D P _ P R E Q#
X DP _ T CL K
10/28
T CK AR2 7 X D P _ T MS R7 3 R 57
AM 3 4 T MS AP3 0
PWR MANAGEMENT
R4 1 9 *1 0 mi l _ 04 P M_ S Y N C _R X DP _ T RS T #
JTAG & BPM

[ 1 5 ] H _ P M _S Y N C P M_ S Y N C TR S T # *2 0 0_ 1 % _0 4 1 0 K _ 04
AR2 8 X DP _ T DI_ R D2 0
T DI AP2 6 X D P _ T D O _R 1 A
[ 1 5] P M_ D R A M_ P W R GD
R4 1 8 *1 0 mi l _ 04 H _ C P U P W R GD _ R A P 3 3 T DO C 3 P MS Y S _P W R G D _ B U F
[ 1 8] H _ C P U P W R G D U N C OR E P W R GO OD 2 A
[ 1 5, 3 3 ] 1 . 8 V S _ P W R G D
A L3 5 X DP _ DB R_ R *B A T5 4 A W G H
P M S Y S _ P W R GD _ B U F R 60 1 3 0_ 1 % _0 4 V D D P W R GO OD _ R V8 DBR # R 58
S M_ D R A MP W R O K
A T2 8 XDP_ B PM 0_ R * 39 _ 0 4
BPM # [ 0] AR2 9 XDP_ B PM 1_ R
BPM # [ 1] AR3 0 XDP_ B PM 2_ R R5 9 0 _ 04
1 .0 5 VS_ VT T Buffered reset to CPU B U F _C P U _ R S T# A R 3 3 BPM # [ 2] A T3 0 XDP_ B PM 3_ R
D
Q 10
RESE T # BPM # [ 3] AP3 2 XDP_ B PM 4_ R
BPM # [ 4] AR3 1 XDP_ B PM 5_ R G
R1 0 5 7 5_ 1 % _0 4 R 1 04 43 _ 1 %_ 0 4 [ 6 , 3 1, 3 3 , 3 4 ] S U S B
BPM # [ 5] A T3 1 XDP_ B PM 6_ R * MT N 7 0 0 2Z H S 3
11/ 04 BPM # [ 6] AR3 2 XDP_ B PM 7_ R
S
6
3 .3 VS D BPM # [ 7]
Q3 6 A
R5 3 0 1 0K _ 0 4 2 G MT D N 7 0 02 Z H S 6 R
S
3 1 P Z 98 8 2 7-3 6 4 B -0 1F
D 10/29
5 G Q3 6 B
S MT D N 7 0 02 Z H S 6 R H _ P R OC H OT # S3 circuit:- DRAM_RST# to memory
4 should be high during S3
D
Q1 4
R 1 12 *1 . 5K _1 % _ 04 1 . 5V
[ 17 , 2 3 ] P L T_ R S T # G
[ 2 7 ] H _ P R OC H O T_ E C
MT N 70 0 2 Z H S 3 C 51 5
S
R5 3 1 C9 6 R 10 6 R4 7 *0 _0 4 R4 5
4 7 p_ 5 0 V _ N P O _0 4
1 00 K _ 0 4 *6 8 p _5 0 V _ N P O _ 04 *7 5 0_ 1 % _0 4 10/1 R9 1 1 0 0 K _ 04 1K _ 0 4
CAD Note: Capacitor Q8

need to be placed MT N 70 0 2 Z H S 3
R9 0 * 0 _0 4 C P UD RA M RS T # S D R 48 1K _0 4
close to buffer output pin D D R 3_ D R A M R S T # [ 9 , 10 ]
R4 6
D R A M R S T _ C N TR L [ 8 , 14 ]
G
4 . 9 9K _ 1 % _0 4
C2 2
0 . 0 47 u _ 10 V _ X 7R _ 04
[ 2 , 5 , 1 8, 1 9 , 2 0 , 34 , 3 6 ] 1 . 05 V S _ V T T
[6 ,3 1 ] 1 . 5V _C P U
[ 6 , 8 , 9, 1 0 , 2 0, 2 6 , 2 8 , 31 , 3 3 ] 1 . 5V
[ 2, 8 , 1 1 , 13 , 1 4 , 1 5, 1 7 , 1 8, 19 , 2 0 , 22 , 2 3 , 2 6, 2 8 , 3 0, 3 1 , 3 3 , 34 , 3 5 ] 3 . 3V
[ 9, 1 0 , 1 1 , 12 , 1 3 , 14 , 1 5 , 1 6, 1 7 , 1 8, 19 , 2 0 , 23 , 2 4 , 2 5, 2 7 , 2 8, 2 9 , 3 0 , 31 , 3 6 ] 3 . 3V S
B - 4 CPU 2/7 (CLK, MISC, JTAG)
Schematic Diagrams
CPU 3/7 (DDR3)

Sandy Bridge Processor 3/7 ( DDR3 )
U34C U34D
AB6 AE2
[ 9] M_A_DQ[63:0] SA_CLK[0] M_A_CLK_DDR0 [9] [10] M_B_DQ[63:0] SB_CLK[0] M_B_CLK_DDR0 [10]
AA6 AD2
C5 SA_CLK#[0] V9 M_A_CLK_DDR#0 [9] C9 SB_CLK#[0] R9 M_B_CLK_DDR#0 [ 10]
M_A_DQ0 M_B_DQ0
D5 SA_DQ[0] SA_CKE[0] M_A_CKE0 [9] A7 SB_DQ[0] SB_CKE[0] M_B_CKE0 [10]
M_A_DQ1 M_B_DQ1
M_A_DQ2 D3 SA_DQ[1] M_B_DQ2 D10 SB_DQ[1]
M_A_DQ3 D2 SA_DQ[2] M_B_DQ3 C8 SB_DQ[2]
M_A_DQ4 D6 SA_DQ[3] AA5 M_B_DQ4 A9 SB_DQ[3] AE1
SA_DQ[4] SA_CLK[1] M_A_CLK_DDR1 [9] SB_DQ[4] SB_CLK[1] M_B_CLK_DDR1 [10]
M_A_DQ5 C6 AB5 M_B_DQ5 A8 AD1
C2 SA_DQ[5] SA_CLK#[1] V10 M_A_CLK_DDR#1 [9] D9 SB_DQ[5] SB_CLK#[1] R10 M_B_CLK_DDR#1 [ 10]
M_A_DQ6 M_B_DQ6
C3 SA_DQ[6] SA_CKE[1] M_A_CKE1 [9] D8 SB_DQ[6] SB_CKE[1] M_B_CKE1 [10]
M_A_DQ7 M_B_DQ7
M_A_DQ8 F10 SA_DQ[7] M_B_DQ8 G4 SB_DQ[7]
M_A_DQ9 F8 SA_DQ[8] M_B_DQ9 F4 SB_DQ[8]
M_A_DQ10 G10 SA_DQ[9] AB4 M_B_DQ10 F1 SB_DQ[9] AB2
M_A_DQ11 G9 SA_DQ[10] SA_CLK[2] AA4 M_B_DQ11 G1 SB_DQ[10] SB_CLK[2] AA2
M_A_DQ12 F9 SA_DQ[11] SA_CLK#[2] W9 M_B_DQ12 G5 SB_DQ[11] SB_CLK#[2] T
9
M_A_DQ13 F7 SA_DQ[12] SA_CKE[2] M_B_DQ13 F5 SB_DQ[12] SB_CKE[2]
M_A_DQ14 G8 SA_DQ[13] M_B_DQ14 F2 SB_DQ[13]
M_A_DQ15 G7 SA_DQ[14] M_B_DQ15 G2 SB_DQ[14]
M_A_DQ16 K4 SA_DQ[15] AB3 M_B_DQ16 J7 SB_DQ[15] AA1
M_A_DQ17 K5 SA_DQ[16] SA_CLK[3] AA3 M_B_DQ17 J8 SB_DQ[16] SB_CLK[3] AB1
K1 SA_DQ[17] SA_CLK#[3] W10 K10 SB_DQ[17] SB_CLK#[3] T
10
M_A_DQ18 M_B_DQ18
M_A_DQ19 J1 SA_DQ[18] SA_CKE[3] M_B_DQ19 K9 SB_DQ[18] SB_CKE[3]
M_A_DQ20 J5 SA_DQ[19] M_B_DQ20 J9 SB_DQ[19]
SA_DQ[20] SB_DQ[20]
M
M
M
_A_DQ21
_A_DQ22
_A_DQ23
J4
J2
K2
SA_DQ[21]
SA_DQ[22] SA_CS#[0]
AK3
AL3 M_A_CS#0 [9]
M_B_DQ21
M_B_DQ22
M_B_DQ23
J10
K8
K7
SB_DQ[21]
SB_DQ[22] SB_CS#[0]
AD3
AE3 M_B_CS#0 [10]
Sheet 4 of 43
M8 SA_DQ[23] SA_CS#[1] AG1 M_A_CS#1 [9] M 5 SB_DQ[23] SB_CS#[1] AD6 M_B_CS#1 [10]
M
M
M
_A_DQ24
_A_DQ25
_A_DQ26
N10
N8
SA_DQ[24]
SA_DQ[25]
SA_CS#[2]
SA_CS#[3]
AH1
M_B_DQ24
M_B_DQ25
M_B_DQ26
N4
N2
SB_DQ[24]
SB_DQ[25]
SB_CS#[2]
SB_CS#[3]
AE6 CPU 3/7
SA_DQ[26] SB_DQ[26]
M
M
M
_A_DQ27
_A_DQ28
_A_DQ29
N7
M10
M9
SA_DQ[27]
SA_DQ[28] AH3
M_B_DQ27
M_B_DQ28
M_B_DQ29
N1
M
N5
4 SB_DQ[27]
SB_DQ[28] AE4
(DDR3)
M_A_DQ30 N9 SA_DQ[29] SA_ODT[0] AG3 M_A_ODT0 [9] M_B_DQ30 M 2 SB_DQ[29] SB_ODT[0] AD4 M_B_ODT0 [10]
M_A_DQ31 M7 SA_DQ[30] SA_ODT[1] AG2 M_A_ODT1 [9] M_B_DQ31 M 1 SB_DQ[30] SB_ODT[1] AD5 M_B_ODT1 [10]
SA_DQ[31] SA_ODT[2] SB_DQ[31] SB_ODT[2]
DDR SYSTEM MEMORY B

M_A_DQ32 AG6 AH2 M_B_DQ32 AM 5 AE5
DDR SYSTEM MEMORY A
M_A_DQ33 AG5 SA_DQ[32] SA_ODT[3] M_B_DQ33 AM 6 SB_DQ[32] SB_ODT[3]

M_A_DQ34 AK6 SA_DQ[33] M_B_DQ34 AR3 SB_DQ[33]
AK5 SA_DQ[34] AP3 SB_DQ[34]
M_A_DQ35 M_B_DQ35
M_A_DQ36 AH5 SA_DQ[35] M_B_DQ36 AN3 SB_DQ[35]
M_A_DQ37 AH6 SA_DQ[36] C4 M_A_DQS#0 M_A_DQS#[7:0] [ 9] M_B_DQ37 AN2 SB_DQ[36] D7 M_B_DQS#0 M_B_DQS#[7:0] [10]
M_A_DQ38 AJ5 SA_DQ[37] SA_DQS#[0] G6 M_A_DQS#1 M_B_DQ38 AN1 SB_DQ[37] SB_DQS#[0] F3 M_B_DQS#1
M_A_DQ39 AJ6 SA_DQ[38] SA_DQS#[1] J3 M_A_DQS#2 M_B_DQ39 AP2 SB_DQ[38] SB_DQS#[1] K6 M_B_DQS#2
M_A_DQ40 AJ8 SA_DQ[39] SA_DQS#[2] M6 M_A_DQS#3 M_B_DQ40 AP5 SB_DQ[39] SB_DQS#[2] N3 M_B_DQS#3
AK8 SA_DQ[40] SA_DQS#[3] AL6 AN9 SB_DQ[40] SB_DQS#[3] AN5
M_A_DQ41 M_A_DQS#4 M_B_DQ41 M_B_DQS#4
M_A_DQ42 AJ9 SA_DQ[41] SA_DQS#[4] AM8 M_A_DQS#5 M_B_DQ42 AT 5 SB_DQ[41] SB_DQS#[4] AP9 M_B_DQS#5
M_A_DQ43 AK9 SA_DQ[42] SA_DQS#[5] AR12 M_A_DQS#6 M_B_DQ43 AT 6 SB_DQ[42] SB_DQS#[5] AK12 M_B_DQS#6
M_A_DQ44 AH8 SA_DQ[43] SA_DQS#[6] AM15 M_A_DQS#7 M_B_DQ44 AP6 SB_DQ[43] SB_DQS#[6] AP15 M_B_DQS#7
M_A_DQ45 AH9 SA_DQ[44] SA_DQS#[7] M_B_DQ45 AN8 SB_DQ[44] SB_DQS#[7]
M_A_DQ46 AL9 SA_DQ[45] M_B_DQ46 AR6 SB_DQ[45]
M_A_DQ47 AL8 SA_DQ[46] M_B_DQ47 AR5 SB_DQ[46]
M_A_DQ48 AP11 SA_DQ[47] M_B_DQ48 AR9 SB_DQ[47]
M_A_DQ49 AN11 SA_DQ[48] D4 M_A_DQS0 M_A_DQS[7:0] [ 9] M_B_DQ49 AJ11 SB_DQ[48] C7 M_B_DQS0 M_B_DQS[7:0] [10]
M_A_DQ50 AL12 SA_DQ[49] SA_DQS[0] F6 M_A_DQS1 M_B_DQ50 AT 8 SB_DQ[49] SB_DQS[0] G3 M_B_DQS1
M_A_DQ51 AM12 SA_DQ[50] SA_DQS[1] K3 M_A_DQS2 M_B_DQ51 AT 9 SB_DQ[50] SB_DQS[1] J6 M_B_DQS2
AM11 SA_DQ[51] SA_DQS[2] N6 AH11 SB_DQ[51] SB_DQS[2] M3
M_A_DQ52 M_A_DQS3 M_B_DQ52 M_B_DQS3
M_A_DQ53 AL11 SA_DQ[52] SA_DQS[3] AL5 M_A_DQS4 M_B_DQ53 AR8 SB_DQ[52] SB_DQS[3] AN6 M_B_DQS4
M_A_DQ54 AP12 SA_DQ[53] SA_DQS[4] AM9 M_A_DQS5 M_B_DQ54 AJ12 SB_DQ[53] SB_DQS[4] AP8 M_B_DQS5
M_A_DQ55 AN12 SA_DQ[54] SA_DQS[5] AR11 M_A_DQS6 M_B_DQ55 AH12 SB_DQ[54] SB_DQS[5] AK11 M_B_DQS6
M_A_DQ56 AJ14 SA_DQ[55] SA_DQS[6] AM14 M_A_DQS7 M_B_DQ56 AT11 SB_DQ[55] SB_DQS[6] AP14 M_B_DQS7
M_A_DQ57 AH14 SA_DQ[56] SA_DQS[7] M_B_DQ57 AN14 SB_DQ[56] SB_DQS[7]
AL15 SA_DQ[57] AR14 SB_DQ[57]
M_A_DQ58 M_B_DQ58
M_A_DQ59 AK15 SA_DQ[58] M_B_DQ59 AT14 SB_DQ[58]
M_A_DQ60 AL14 SA_DQ[59] M_B_DQ60 AT12 SB_DQ[59]
SA_DQ[60] M_A_A[15:0] [9] SB_DQ[60] M_B_B[ 15:0] [10]
M_A_DQ61 AK14 AD10 M_A_A0 M_B_DQ61 AN15 AA8 M_B_B0
M_A_DQ62 AJ15 SA_DQ[61] SA_MA[0] W1 M_A_A1 M_B_DQ62 AR15 SB_DQ[61] SB_MA[0] T
7 M_B_B1
M_A_DQ63 AH15 SA_DQ[62] SA_MA[1] W2 M_A_A2 M_B_DQ63 AT15 SB_DQ[62] SB_MA[1] R7 M_B_B2
SA_DQ[63] SA_MA[2] W7 M_A_A3 SB_DQ[63] SB_MA[2] T
6 M_B_B3
SA_MA[3] V3 M_A_A4 SB_MA[3] T
2 M_B_B4
SA_MA[4] V2 M_A_A5 SB_MA[4] T
4 M_B_B5
SA_MA[5] W3 M_A_A6 SB_MA[5] T
3 M_B_B6
AE10 SA_MA[6] W6 M_A_A7 AA9 SB_MA[6] R2 M_B_B7
[9] M_A_BS0 AF10 SA_BS[0] SA_MA[7] V1 [10] M_B_BS0 AA7 SB_BS[0] SB_MA[7] T
5
M_A_A8 M_B_B8
[9] M_A_BS1 V6 SA_BS[1] SA_MA[8] W5 M_A_A9 [10] M_B_BS1 R6 SB_BS[1] SB_MA[8] R3 M_B_B9
[9] M_A_BS2 SA_BS[2] SA_MA[9] AD8 M_A_A10 [10] M_B_BS2 SB_BS[2] SB_MA[9] AB7 M_B_B10
SA_MA[10] V4 M_A_A11 SB_MA[10] R1 M_B_B11
SA_MA[11] W4 M_A_A12 SB_MA[11] T
1 M_B_B12
AE8 SA_MA[12] AF8 M_A_A13 AA10 SB_MA[12] AB10 M_B_B13
[9] M_A_CAS# AD9 SA_CAS# SA_MA[13] V5 [ 10] M_B_CAS# AB8 SB_CAS# SB_MA[13] R5
M_A_A14 M_B_B14
[9] M_A_RAS# AF9 SA_RAS# SA_MA[14] V7 M_A_A15 [ 10] M_B_RAS# AB9 SB_RAS# SB_MA[14] R4 M_B_B15
[ 9] M_A_WE# SA_WE# SA_MA[15] [10] M_B_WE# SB_WE# SB_MA[15]
PZ98827-364B- 01F PZ98827-364B-01F
CPU 3/7 (DDR3) B - 5
Schematic Diagrams
CPU 4/7 (Power)

U 34F POWER
V CO RE
48A PROCESSOR UNCORE POWER 1 .0 5 V S _ V T T
A G3 5
PROCES SOR CORE POWER A G3 4 V CC 1 A H 13
8.5A
A G3 3 V CC 2 V CC IO 1 A H 10
A G3 2 V CC 3 V CC IO 2 A G 10 C3 6 1 C3 5 7 C 365 C 398 C 350 C4 0 2
ICCMAX Maximum Proces sor SV 48 A G3 1
A G3 0
V
V
CC
CC
4
5
V CC IO 3
V CC IO 4
A C 10
Y1 0
+
22 u _ 6 . 3 V _ X 5 R _ 0 8 22 u _ 6 . 3 V _ X 5R _ 0 8 2 2 u _ 6 . 3 V _ X 5R _ 0 8 * 2 2 u_ 6 . 3 V _ X 5 R _ 0 8 * 2 2 u_ 6 . 3 V _ X 5 R _ 0 8
V C OR E A G2 9 V CC 6 V CC IO 5 U1 0 22 0 u _ 6 . 3 V _ 6 . 3 *6 . 3 *4 . 2
A G2 8 V CC 7 V CC IO 6 P1 0
C 353 2 2u _ 6 . 3 V _ X 5 R _ 0 8 A G2 7 V CC 8 V CC IO 7 L10
A G2 6 V CC 9 V CC IO 8 J14
AF3 5 V CC 10 V CC IO 9 J13
C 371 2 2u _ 6 . 3 V _ X 5 R _ 0 8 C3 5 5 C3 4 4 C 364 C 358 C 346 C4 1 7
AF3 4 V CC 11 V CC IO 1 0 J12
V CC 12 V CC IO 1 1 +
C 366 2 2u _ 6 . 3 V _ X 5 R _ 0 8 AF3 3 J11 *2 2 u _6 . 3 V _ X 5 R _0 8 *2 2 u _6 . 3 V _ X 5 R _0 8 * 2 2 u_ 6 . 3 V _ X 5 R _ 0 8 * 2 2 u_ 6 . 3 V _ X 5 R _ 0 8 2 2 u _ 6 . 3 V _ X5 R _ 0 8
AF3 2 V CC 13 V CC IO 1 2 H1 4 22 0 u _ 6 . 3 V _ 6 . 3 *6 . 3 *4 . 2
C 354 2 2u _ 6 . 3 V _ X 5 R _ 0 8 AF3 1 V CC 14 V CC IO 1 3 H1 2
AF3 0 V CC 15 V CC IO 1 4 H1 1
AF2 9 V CC 16 V CC IO 1 5 G1 4
C 359 2 2u _ 6 . 3 V _ X 5 R _ 0 8
AF2 8 V CC 17 V CC IO 1 6 G1 3 C3 9 6 C4 1 9 C 406 C 397 C 384
C 363 2 2u _ 6 . 3 V _ X 5 R _ 0 8 AF2 7 V CC 18 V CC IO 1 7 G1 2
PEG AND DDR

AF2 6 V CC 19 V CC IO 1 8 F1 4 *2 2 u _6 . 3 V _ X 5 R _0 8 *2 2 u _6 . 3 V _ X 5 R _0 8 * 2 2 u_ 6 . 3 V _ X 5 R _ 0 8 * 2 2 u_ 6 . 3 V _ X 5 R _ 0 8 2 2 u _ 6 . 3 V _ X5 R _ 0 8
A D3 5 V CC 20 V CC IO 1 9 F1 3
C 337 2 2u _ 6 . 3 V _ X 5 R _ 0 8
A D3 4 V CC 21 V CC IO 2 0 F1 2
C 332 2 2u _ 6 . 3 V _ X 5 R _ 0 8 A D3 3 V CC 22 V CC IO 2 1 F1 1
A D3 2 V CC 23 V CC IO 2 2 E1 4
C 351 2 2u _ 6 . 3 V _ X 5 R _ 0 8 A D3 1 V CC 24 V CC IO 2 3 E1 2 C3 2 1 C4 1 8 C 375 C 383 C 382
A D3 0 V CC 25 V CC IO 2 4
A D2 9 V CC 26 E1 1
C 336 2 2u _ 6 . 3 V _ X 5 R _ 0 8 *2 2 u _6 . 3 V _ X 5 R _0 8 *2 2 u _6 . 3 V _ X 5 R _0 8 2 2 u _ 6 . 3 V _ X 5R _ 0 8 2 2 u _ 6 . 3 V _ X 5R _ 0 8 * 2 2 u_ 6 . 3 V _ X 5 R _ 0 8
A D2 8 V CC 27 V CC IO 25 D1 4
Sheet 5 of 43 A D2 7
A D2 6
A C3 5
V
V
V
CC
CC
CC
28
29
30
V CC
V CC
V CC
IO
IO
IO
26
27
28
D1 3
D1 2
D1 1
V CC 31 V CC IO 29
CPU 4/7 V C OR E
C 69 1 0u _ 6 . 3 V _ X 5 R _ 0 6
A C3 4
A C3 3
A C3 2
A C3 1
V
V
V
CC
CC
CC
32
33
34
V CC
V CC
V CC
IO
IO
IO
30
31
32
C1 4
C1 3
C1 2
C1 1
C4 0 7
*2 2 u _6 . 3 V _ X 5 R _0 8
C3 7 2
22 u _ 6 . 3 V _ X 5R _ 0 8
C 352
2 2 u _ 6 . 3 V _ X 5R _ 0 8
C 367
2 2 u _ 6 . 3 V _ X 5R _ 0 8
C 385
2 2 u _ 6 . 3 V _ X5 R _ 0 8
(Power) C 33 1 0u _ 6 . 3 V _ X 5 R _ 0 6 A C3 0 V CC 35 V CC IO 33 B1 4
A C2 9 V CC 36 V CC IO 34 B1 2
A C2 8 V CC 37 V CC IO 35 A1 4
C 74 1 0u _ 6 . 3 V _ X 5 R _ 0 6
A C2 7 V CC 38 V CC IO 36 A1 3 C3 8 1 C3 9 4 C 420 C 368
A C2 6 V CC 39 V CC IO 37 A1 2
C 56 1 0u _ 6 . 3 V _ X 5 R _ 0 6
AA3 5 V CC 40 V CC IO 38 A1 1 *2 2 u _6 . 3 V _ X 5 R _0 8 *2 2 u _6 . 3 V _ X 5 R _0 8 * 2 2 u_ 6 . 3 V _ X 5 R _ 0 8 * 2 2 u_ 6 . 3 V _ X 5 R _ 0 8
C 34 1 0u _ 6 . 3 V _ X 5 R _ 0 6 AA3 4 V CC 41 V CC IO 39
AA3 3 V CC 42 J23 + V 1 .0 5 S _ V C CP _ F R 62 * 2 0m i l _ 0 4
AA3 2 V CC 43 V CC IO 4 0 1 .0 5 V S _ V T T
C 53 1 0u _ 6 . 3 V _ X 5 R _ 0 6
AA3 1 V CC 44
AA3 0 V CC 45
AA2 9 V CC 46
V C OR E AA2 8 V CC 47
AA2 7 V CC 48
AA2 6 V CC 49
C 362 *2 2 u _ 6. 3V _X 5 R _ 08
Y3 5 V CC 50
CORE SUPPLY
C 360 *2 2 u _ 6. 3V _X 5 R _ 08 Y3 4 V CC 51 CAD Note: H_CPU_SVIDALRT#_R,H_CPU_SVIDDAT_R
Y3 3 V CC 52 Place the PU resistors close to CPU
Y3 2 V CC 53
C 334 *2 2 u _ 6. 3V _X 5 R _ 08
Y3 1 V CC 54
C 333 *2 2 u _ 6. 3V _X 5 R _ 08 Y3 0 V CC 55
Y2 9 V CC 56 SVID Signals
Y2 8 V CC 57
C 356 *2 2 u _ 6. 3V _X 5 R _ 08
Y2 7 V CC 58
C 62 *1 0 u _ 6. 3V _X 5 R _ 06 Y2 6 V CC 59 1 .0 5 V S_ VT T
V3 5 V CC 60
C 72 *1 0 u _ 6. 3V _X 5 R _ 06 V3 4 V CC 61 AJ 2 9 H _ C P U _ S V I D A L R T # _R R 40 6 4 3 _ 1 % _0 4 H _ C P U _S V I D A L R T # R4 0 8 7 5_ 1 % _ 0 4
SVID
V3 3 V CC 62 VID AL ER T # AJ 3 0 H _C P U _ S V I D A L R T # [ 3 6 ]
H _ CP U_ S V IDC L K _ R R 88 0_04 H _ C P U _S V I D C L K R8 9 *5 4 . 9 _ 1 % _0 4
V3 2 V CC 63 V ID S CL K AJ 2 8 H _ CP U_ S V IDD A T _ R H _C P U _ S V I D C L K [ 3 6] H _ C P U _S V I D D A T _ R
C 59 *1 0 u _ 6. 3V _X 5 R _ 06 R 85 0_04 R8 6 1 30 _ 1 % _ 0 4
V3 1 V CC 64 VI DSO U T H _C P U _ S V I D D A T [ 3 6]
C 66 *1 0 u _ 6. 3V _X 5 R _ 06 V3 0 V CC 65
V2 9 V CC 66
V2 8 V CC 67
V2 7 V CC 68
V2 6 V CC 69
CAD Note: H_CPU_SVIDCLK_R
U3 5 V CC 70 Place the PU
U3 4 V CC 71
U3 3 V CC 72 resistors close to VR
U3 2 V CC 73
U3 1 V CC 74
U3 0 V CC 75
U2 9 V CC 76
U2 8 V CC 77 V C OR E _ V C C _ S E N S E [ 3 6 ]
U2 7 V CC 78 V C OR E _ V S S _ S E N S E [ 3 6 ]
U2 6 V CC 79
R3 5 V CC 80
R3 4 V CC 81
R3 3 V CC 82
R3 2 V CC 83
R3 1 V CC 84
R3 0 V CC 85 1 .0 5 V S _ V T T
R2 9 V CC 86
R2 8 V CC 87
SENSE LINES
R2 7 V CC 88 AJ 3 5
R2 6 V CC 89 V C C_ S E N S E AJ 3 4 R 3 79
P3 5 V CC 90 V SS_ SEN SE
P3 4 V CC 91 10_04
P3 3 V CC 92
P3 2 V CC 93 B1 0 V C CIO _ S E N S E _ R R 3 84 *0 _ 0 4 V C CIO _ S E N S E [ 34 ]
P3 1 V CC 94 V C C I O_ S E N S E A1 0 V S S I O_ S E N S E
P3 0 V CC 95 V S S I O_ S E N S E
P2 9 V CC 96
P2 8 V CC 97 [ 3 6 , 37 ] V CO R E
P2 7 V CC 98 [ 2, 3 , 1 8 , 1 9 , 2 0 , 3 4 , 36 ] 1. 05 V S _ V T T
P2 6 V CC 99 R 3 83
V CC 1 00
10_04
P Z 9 88 2 7 -3 6 4 B -0 1 F
B - 6 CPU 4/7 (Power)
Schematic Diagrams
CPU 5/7 (Graphics Power)
Sandy Bridge Processor 5/7 ( GRAPHICS POWER )
U 3 4G
POWER 1 .5 V
V G F X _ CO RE
All VAXG = 33A R 11 9

AT2 4 AK3 5
SENSE
LINES
AT2 3 VAXG 1 VA XG _ SENSE AK3 4 V C C _ GT _ S E N S E [ 3 6]
Q1 5 1 K _ 1 % _0 4
C 3 91 C 39 2 C3 6 9 C 3 88 C3 8 7 AT2 1 VAXG 2 V SSA XG _ SENSE V S S _ GT _ S E N S E [ 3 6 ] *A O3 4 02 L
AT2 0 VAXG 3 V _ S M _V R E F S D V _ S M _ V RE F _ C NT
AT1 8 VAXG 4
2 2 u _ 6. 3 V _ X 5 R _ 0 8 2 2 u_ 6 . 3 V _ X5 R _ 08 *2 2 u_ 6 . 3 V _ X 5R _ 08 2 2 u _6 . 3 V _ X 5R _ 0 8 2 2u _ 6 . 3 V _X 5 R _0 8
AT1 7 VAXG 5 R1 1 4
A R2 4 VAXG 6
*1 0 0K _1 % _ 04 R 11 7
VAXG 7
G
A R2 3 11/03
A R2 1 VAXG 8
1 1/03 1 K _ 1 % _0 4
A R2 0 VAXG 9 C5 8 6 *0 . 1 u _1 0 V _ X 7R _ 04
A R1 8 VAXG 10 S U S B # [ 3, 3 1 , 3 3 , 34 ]
VREF
A R1 7 VAXG 11
C 3 86 C 37 6 C3 7 4 C 3 17 C3 7 7
AP2 4 VAXG 12 AL 1 V_ SM _ VREF R1 1 6 0 _0 4 V _ S M _V R E F _ C N T
AP2 3 VAXG 13 SM _ VREF
2 2 u _ 6. 3 V _ X 5 R _ 0 8 2 2 u_ 6 . 3 V _ X5 R _ 08 22 u _ 6 . 3V _X 5 R _ 0 8 2 2 u _6 . 3 V _ X 5R _ 0 8 2 2u _ 6 . 3 V _X 5 R _0 8
AP2 1 VAXG 14
AP2 0 VAXG 15
AP1 8 VAXG 16 CAD Note: +V_SM_VREF should
AP1 7 VAXG 17 have 10 mil trace width
A N2 4 VAXG 18
A N2 3 VAXG 19
A N2 1 VAXG 20
C 3 89 C 39 0 C3 2 2 C 3 18 C3 7 3
A N2 0 VAXG 21
A N1 8 VAXG 22 1. 5 V _ C P U
2 2 u _ 6. 3 V _ X 5 R _ 0 8 2 2 u_ 6 . 3 V _ X5 R _ 08 22 u _ 6 . 3V _X 5 R _ 0 8 * 22 u _ 6 . 3V _X 5 R _ 0 8 2 2u _ 6 . 3 V _X 5 R _0 8
DDR3 -1.5V RAILS

VAXG 23
A N1 7
A M2 4 VAXG 24 AF7
All VDDQ = 12A
Sheet 6 of 43
GRAPHICS
A M2 3 VAXG 25 VD DQ 1 AF4
A M2 1 VAXG 26 VD DQ 2 AF1 +C 4 00
A M2 0
A M1 8
VAXG
VAXG
VAXG
27
28
29
VD DQ 3
VD DQ 4
VD DQ 5
A C7
A C4
C6 3
10 u _ 6 . 3V _X 5 R _ 0 6
C 65
1 0 u _6 . 3 V _ X 5R _ 0 6
C5 8
1 0u _ 6 . 3 V _X 5 R _0 6 2 2 0 u _6 . 3 V _ 6 . 3* 6 . 3 *4 . 2
CPU 5/7
C 3 15 C 31 4 A M1 7 A C1
+
* 3 30 U _2 . 5 V _ D 2_ D
+
5 6 0u _ 2 . 5 V _6 . 6 * 6. 6 * 5. 9
AL 2 4
AL 2 3
AL 2 1
VAXG
VAXG
VAXG
30
31
32
VD DQ 6
VD DQ 7
VD DQ 8
Y7
Y4
Y1
11/29
(Graphics Power)
AL 2 0 VAXG 33 VD DQ 9 U7 C7 1 C 60 C6 7
AL 1 8 VAXG 34 V D D Q1 0 U4
AL 1 7 VAXG 35 V D D Q1 1 U1 10 u _ 6 . 3V _X 5 R _ 0 6 1 0 u _6 . 3 V _ X 5R _ 0 6 1 0u _ 6 . 3 V _X 5 R _0 6
AK2 4 VAXG 36 V D D Q1 2 P7
AK2 0 VAXG 39 V D D Q1 5
AK1 8 VAXG 40
AK1 7 VAXG 41
AJ 2 4 VAXG 42
AJ 2 3 VAXG 43
AJ 2 1 VAXG 44
AJ 2 0 VAXG 45
AJ 1 8 VAXG 46
AJ 1 7 VAXG 47
A H2 4 VAXG 48 0. 8 5 V S
A H2 3 VAXG 49
SA RAIL
A H2 1 VAXG 50 M2 7
All VDDQ = 6A
A H2 0 VAXG 51 V CC SA1 M2 6
A H1 8 VAXG 52 V CC SA2 L 26 C3 2 3 C 3 45 C2 8 P C1 6 7
A H1 7 VAXG 53 V CC SA3 J 26 +
VAXG 54 V CC SA4 J 25 10 u _ 6 . 3V _X 5 R _ 0 8 1 0 u _6 . 3 V _ X 5R _ 0 8 1 0u _ 6 . 3 V _X 5 R _0 6 * 3 30 u _ 2 . 5V _9 m _ 6. 3* 6
V CC SA5 J 24
V CC SA6 H2 6
V CC SA7 H2 5
V CC SA8
1.8V RAIL
1 .5 V _ CP U
1 .8 V S
All VCCPLL = 1.2A B6 H2 3 V C C S A _S E N S E V CC S A _ S E NS E [3 5 ]
A6 V C CP L L 1 V CCS A _ S E NS E R3 9 3
MISC
C 4 58 C3 1 6 C3 1 9 C 32 0 A2 V C CP L L 2 R5 3 2 * 0 _0 4
V C CP L L 3 V CC S A _ V ID0 [3 5 ]
+ *1 0 K _ 0 4
3 3 0 uF _2 . 5 V _ 9 m_ 6 . 3 *6 1 0 u_ 6 . 3 V _ X5 R _0 6 1u _ 6 . 3 V _X 5 R _0 4 1 u _ 6. 3 V _ X 5 R _ 0 4 C2 2 R 56 1 0K _0 4
F C _ C2 2 C2 4
V C CS A _ V ID 1 V C C S A _ V I D 1 [ 35 ]
P Z 98 8 2 7-3 6 4 B -0 1 F R3 8 6
1 0 K _0 4
[ 3 5] 0. 8 5 V S
[ 19 , 2 9 , 3 1] 1. 5 V S
[ 18 , 1 9 , 3 3] 1. 8 V S
[ 3 , 8 , 9 , 10 , 2 0 , 2 6, 28 , 3 1 , 3 3] 1. 5 V
[ 3 , 3 1] 1. 5 V _ C P U
[ 3 7] V GF X _ C O R E
[ 3 , 9 , 1 0, 1 1 , 1 2 , 1 3, 1 4 , 1 5 , 16 , 1 7 , 1 8, 1 9 , 2 0 , 2 3, 2 4 , 2 5 , 27 , 2 8 , 2 9, 30 , 3 1 , 3 6] 3. 3 V S
CPU 5/7 (Graphics Power) B - 7
Schematic Diagrams
CPU 6/7 (GND)
Sandy Bridge Processor 6/7 ( GND )

U34H U3 4I
AT35 AJ22
AT32 VSS1 VSS81 AJ19
AT29 VSS2 VSS82 AJ16 T35 F22
AT27 VSS3 VSS83 AJ13 T34 VSS1 61 VSS234 F19
AT25 VSS4 VSS84 AJ10 T33 VSS1 62 VSS235 E30
CAD Note: 0 ohm resistor AT10 VSS9 VSS89 AJ1 T28 VSS1 67 VSS240 E15
should be placed close AT7 VSS10 VSS90 AH35 T27 VSS1 68 VSS241 E13
AT4 VSS11 VSS91 AH34 T26 VSS1 69 VSS242 E10
to CPU AT3 VSS12 VSS92 AH32 P9 VSS1 70 VSS243 E9
AR25 VSS13 VSS93 AH30 P8 VSS1 71 VSS244 E8
VSS14 VSS94 VSS1 72 VSS245
AR22 AH29 P6 E7
AR10 VSS18 VSS98 AH22 N35 VSS1 76 VSS249 E3
AR7 VSS19 VSS99 AH19 N34 VSS1 77 VSS250 E2
AR4 VSS20 VSS1 00 AH16 N33 VSS1 78 VSS251 E1
AR2 VSS21 VSS1 01 AH7 N32 VSS1 79 VSS252 D35
AP34 VSS22 VSS1 02 AH4 N31 VSS1 80 VSS253 D32
AP31 VSS23 VSS1 03 AG9 N30 VSS1 81 VSS254 D29
VSS24 VSS1 04 VSS1 82 VSS255
Sheet 7 of 43 AP28
AP25
AP22
VSS25
VSS26
VSS1 05
VSS1 06
AG8
AG4
AF6
N29
N28
N27
VSS1 83
VSS1 84
VSS256
VSS257
D26
D20
D17
AP19 VSS27 VSS1 07 AF5 N26 VSS1 85 VSS258 C34
CPU 6/7 (GND) AP16
AP13
VSS28
VSS29
VSS1 08
VSS1 09
AF3
AF2
M34
L33
VSS1 86
VSS1 87
VSS259
VSS260
C31
C28
AP10 VSS30 VSS1 10 AE3 5 L30 VSS1 88 VSS261 C27
AN30 VSS34 VSS1 14 AE3 1 L6 VSS1 92 VSS265 C1
AN27 VSS35 VSS1 15 AE3 0 L5 VSS1 93 VSS266 B22
AN25 VSS36 VSS1 16 AE2 9 L4 VSS1 94 VSS267 B19
AN22
AN19
VSS37
VSS38
VSS39
VSS VSS1 17
VSS1 18
VSS1 19
AE2 8
AE2 7
L3
L2
VSS1 95
VSS1 96
VSS1 97
VSS VSS268
VSS269
VSS270
B17
B15
AN16 AE2 6 L1 B13
AN13 VSS40 VSS1 20 AE9 K35 VSS1 98 VSS271 B11
AN10 VSS41 VSS1 21 AD7 K32 VSS1 99 VSS272 B9
AN7 VSS42 VSS1 22 AC9 K29 VSS2 00 VSS273 B8
AN4 VSS43 VSS1 23 AC8 K26 VSS2 01 VSS274 B7
AM29 VSS44 VSS1 24 AC6 J34 VSS2 02 VSS275 B5
AM25 VSS45 VSS1 25 AC5 J31 VSS2 03 VSS276 B3
AM22 VSS46 VSS1 26 AC3 H33 VSS2 04 VSS277 B2
AM19 VSS47 VSS1 27 AC2 H30 VSS2 05 VSS278 A35
AM16 VSS48 VSS1 28 AB3 5 H27 VSS2 06 VSS279 A32
AM2 VSS54 VSS1 34 AB2 9 H10 VSS2 12 VSS285
AM1 VSS55 VSS1 35 AB2 8 H9 VSS2 13
AL34 VSS56 VSS1 36 AB2 7 H8 VSS2 14
AL31 VSS57 VSS1 37 AB2 6 H7 VSS2 15
AL28 VSS58 VSS1 38 Y9 H6 VSS2 16
AL10 VSS64 VSS1 44 W35 G35 VSS2 22
AL7 VSS65 VSS1 45 W34 G32 VSS2 23
AL4 VSS66 VSS1 46 W33 G29 VSS2 24
AL2 VSS67 VSS1 47 W32 G26 VSS2 25
AK33 VSS68 VSS1 48 W31 G23 VSS2 26
AK30 VSS69 VSS1 49 W30 G20 VSS2 27
AK27 VSS70 VSS1 50 W29 G17 VSS2 28
AK25 VSS71 VSS1 51 W28 G11 VSS2 29
AK22 VSS72 VSS1 52 W27 F34 VSS2 30
AK19 VSS73 VSS1 53 W26 F31 VSS2 31
AK16 VSS74 VSS1 54 U9 F29 VSS2 32
AK13 VSS75 VSS1 55 U8 VSS2 33
AK10 VSS76 VSS1 56 U6
AJ25 VSS79 VSS1 59 U2
VSS80 VSS1 60
PZ9882 7-364 B- 01F PZ98827- 364B-01 F
B - 8 CPU 6/7 (GND)
Schematic Diagrams
CPU 7/7 (RESERVED)

CFG Straps for Processor
( RESERVED )
PEG Static Lane Reversal - CFG2 is for the 16x U 34 E
L7
CFG2 1:(Default) Normal Operation; Lane # R SVD 28 AG 7
definition matches socket pin map definition CF G 0 AK2 8 R SVD 29 AE7
AK2 9 CF G [0 ] R SVD 30 AK2
0:Lane Reversed CF G 2 AL 2 6 CF G [1 ] R SVD 31 W8
AL 2 7 CF G [2 ] R SVD 32
CF G 4 AK2 6 CF G [3 ]
CF G 5 AL 2 9 CF G [4 ] AT2 6
CF G 2 R 11 1 *1 K _ 0 4 CF G 6 AL 3 0 CF G [5 ] R S V D 33 AM 3 3
CF G 7 A M3 1 CF G [6 ] R S V D 34 AJ 2 7
A M3 2 CF G [7 ] R S V D 35
A M3 0 CF G [8 ]
A M2 8 CF G [9 ]
A M2 6 CF G [ 1 0]
AN2 8 CF G [ 1 1]
AN3 1 CF G [ 1 2] T8
Display Port Presence Strap AN2 6 CF G [ 1 3] R SVD 37 J16
A M2 7 CF G [ 1 4] R SVD 38 H 16
1:(Default) Disabled; No Physical Display Port AK3 1 CF G [ 1 5] R SVD 39 G 16
CFG4 attached to Embedded Display Port AN2 9 CF G [ 1 6] R SVD 40
0:Enabled; An external Display Port device is

CF G [ 1 7]
Sheet 8 of 43
connected to the Embedded Display Port
H_ CPU
H_ CPU
_ RSV D
_ RSV D
1 AJ 3 1
2 AH3 1 V A X G_ V A L _ S E N S E
R
R
SVD
SVD
41
42
AR 3 5
AT3 4
AT3 3
CPU 7/7
V S S A X G_ V A L _ S E N S E R SVD 43
CF G 4 R 11 0 *1 K _ 0 4
H_ CPU
H_ CPU
_ RSV D
_ RSV D
3 AJ 3 3
4 AH3 3
V C C _ V A L _S E N S E
VS S _ V AL _ S ENSE
R
R
SVD
SVD
44
45
AP3 5
AR 3 4
(RESERVED)
AJ 2 6
RS V D 5
RESERVED
B3 4
V R E F _ C H _A _ D IMM B 4 R SVD 46 A3 3
PCIE Port Bifurcation Straps
V R E F _ C H _B _ D IMM D 1 RS V D 6 R SVD 47 A3 4
RS V D 7 R SVD 48 B3 5
R SVD 49 C 35
11: (Default) x16 - Device 1 functions 1 and 2 disabled R SVD 50
10: x8, x8 - Device 1 function 1 enabled ; function 2 disabled F25 1 .5 V
F24 RS V D 8
CFG[6:5] 01: Reserved - (Device 1 function 1 disabled ; function 2 enabled) F23 RS V D 9 R 40 * 0 _0 4
D2 4 RS V D 10 AJ 3 2
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled G2 5 RS V D 11 R S V D 51 AK3 2 R3 8
G2 4 RS V D 12 R S V D 52
E2 3 RS V D 13 Q7 1K _ 1 % _ 04
CF G 5 D2 3 RS V D 14
R 99 *1 K _ 0 4 * A O3 4 0 2L
C3 0 RS V D 15 AH 2 7 V R E F _ C H _ A _ D I MM S D MV R E F _ D Q _ D I M 0
A3 1 RS V D 16 V C C_ DIE_ SE N S E M V R E F _D Q_ D I MMA [ 9]
CF G 6 R 92 *1 K _ 0 4 B3 0 RS V D 17
B2 9 RS V D 18
R3 9 R3 1 10/29
RS V D 19
G
D3 0 AN 3 5
B3 1 RS V D 20 R S V D 54 AM 3 5 *1 K _ 0 4 1K _ 1 % _ 04
A3 0 RS V D 21 R S V D 55
C2 9 RS V D 22
RS V D 23
PEG DEFER TRAINING J20 D R A M R S T _ C N TR L

B1 8 RS V D 2 4 AT2 D R A M R S T _ C N TR L [ 3, 14 ]
1: (Default) PEG Train immediately following xxRESETB de assertion A1 9 RS V D 2 5 R S V D 56 AT1
CFG7 0: PEG Wait for BIOS for training V C C I O_ S E L R S V D 57
R S V D 58
AR 1 1 .5 V
J15 R 44 * 0 _0 4
RS V D 2 7
CF G 7 R 93 *1 K _ 0 4 B1 R 28
KE Y Q6
* A O3 4 0 2L 1 K _ 1% _ 0 4
V R E F _ C H _ B _ D I MM S D M V R E F _ D Q_ D I M 1
M V R E F _D Q_ D I MMB [ 10 ]
10/29
R4 9 R 29
G
10/29 P Z 9 8 8 27 -3 6 4B - 01 F
3 .3 V R 39 2 10 K _ 0 4 *1 K _ 0 4 1 K _ 1% _ 0 4
R3 9 1 * 10 m i _l 0 4 H _S N B _ I V B # _P W R C TR L
D R A M R S T _ C N TR L
On CRB
H_SNB_IVB#_PWRCTRL = low, 1.0V
H_SNB_IVB#_PWRCTRL = high/NC, 1.05V
[ 3 , 6 , 9, 1 0 , 2 0, 2 6 ,2 8 ,31 ,3 3 ] 1 . 5V
[ 2, 3 ,1 1 , 13 , 1 4 , 1 5, 1 7 , 1 8, 19 , 2 0 , 22 , 2 3 , 2 6, 2 8 , 3 0, 3 1 ,3 3 ,34 ,3 5 ] 3 . 3V
CPU 7/7 (RESERVED) B - 9
Schematic Diagrams
DDR3 SO-DIMM_0
SO-DIMM A CHANGE TO STANDARD
J D I M M2 A
[ 4] M_ A _ A [ 1 5 : 0] 98 5 M _ A _ D Q [ 63 : 0 ] [ 4 ]
M _ A_ A0 M _ A_ DQ 0 J D I MM 2B
M _ A_ A1 97 A0 DQ 0 7 M _ A_ DQ 1
M _ A_ A2 96 A1 DQ 1 15 M _ A_ DQ 2
M _ A_ A3 95 A2 DQ 2 17 M _ A_ DQ 3 1. 5V
M _ A_ A4 92 A3 DQ 3 4 M _ A_ DQ 4
M _ A_ A5 91 A4 DQ 4 6 M _ A_ DQ 5 75 44
M _ A_ A6 90 A5 DQ 5 16 M _ A_ DQ 6 76 VD D1 V SS1 6 48
85 A8 DQ 8 23 87 VD D4 V SS1 9 55
M _ A_ A9 M _ A_ DQ 9
M _ A _ A 10 107 A9 DQ 9 33 M _ A_ DQ 10 88 VD D5 V SS2 0 60
M _ A _ A 11 84 A1 0 /AP DQ 1 0 35 M _ A_ DQ 11 93 VD D6 V SS2 1 61
M _ A _ A 12 83 A1 1 DQ 1 1 22 M _ A_ DQ 12 94 VD D7 V SS2 2 65
M _ A _ A 13 119 A 1 2 /B C# DQ 1 2 24 M _ A_ DQ 13 3 .3 VS 99 VD D8 V SS2 3 66
M _ A _ A 14 80 A1 3 DQ 1 3 34 M _ A_ DQ 14 100 VD D9 V SS2 4 71
M _ A _ A 15 78 A1 4 DQ 1 4 36 M _ A_ DQ 15 20 mi ls 105 VD D1 0 V SS2 5 72
A1 5 DQ 1 5 39 M _ A_ DQ 16 106 VD D1 1 V SS2 6 12 7
109 DQ 1 6 41 M _ A_ DQ 17 C 10 1 C1 0 2 111 VD D1 2 V SS2 7 12 8
[4 ] M _ A_ BS0 108 BA0 DQ 1 7 51 M _ A_ DQ 18 112 VD D1 3 V SS2 8 13 3
[4 ] M _ A_ BS1 79 BA1 DQ 1 8 53 M _ A_ DQ 19 1 u _6 . 3 V _ Y 5 V _ 0 4 0 . 1 u_ 1 6 V _ Y 5 V _ 04 117 VD D1 4 V SS2 9 13 4
[4 ] M _ A_ BS2 114 BA2 DQ 1 9 40 118 VD D1 5 V SS3 0 13 8
M _ A_ DQ 20
[4 ] M _ A_ CS # 0 121 S0 # DQ 2 0 42 M _ A_ DQ 21 123 VD D1 6 V SS3 1 13 9
[4 ] M _ A_ CS # 1 101 S1 # DQ 2 1 50 124 VD D1 7 V SS3 2 14 4
M _ A_ DQ 22
[ 4 ] M_ A _ C L K _ D D R 0 103 CK 0 DQ 2 2 52 M _ A_ DQ 23 VD D1 8 V SS3 3 14 5
[ 4 ] M_ A _ C L K _ D D R #0
Sheet 9 of 43
102 CK 0 # DQ 2 3 57 M _ A_ DQ 24 199 V SS3 4 15 0
[ 4 ] M_ A _ C L K _ D D R 1 104 CK 1 DQ 2 4 59 M _ A_ DQ 25 V D DS PD V SS3 5 15 1
[ 4 ] M_ A _ C L K _ D D R #1 CK 1 # DQ 2 5 V SS3 6
73 67 M _ A_ DQ 26 3 .3 V S 77 15 5
[4 ] M _ A_ CK E0 74 CK E 0 DQ 2 6 69 M _ A_ DQ 27 122 N C1 V SS3 7 15 6
DDR3 SO-DIMM_0 [4 ] M _ A_ CK E1
[ 4 ] M_ A _ C A S #
[ 4 ] M_ A _ R A S #
115
110
113
CK E 1
CA S #
RA S #
DQ 2 7
DQ 2 8
DQ 2 9
56
58
68
M
M
M
_ A_ DQ
_ A_ DQ
_ A_ DQ
28
29
30
R1 2 4 *1 0K _0 4 125
198
N C2
N CT E ST
V
V
V
SS3 8
SS3 9
SS4 0
16 1
16 2
16 7
[ 4 ] M_ A _ W E # 197 W E# DQ 3 0 70 [ 2 , 1 0 ] T S # _D I MM 0 _1 30 EVEN T# V SS4 1 16 8
S A 0_ D I M0 M _ A_ DQ 31
S A 1_ D I M0 201 SA0 DQ 3 1 12 9 M _ A_ DQ 32 [ 3 , 1 0 ] D D R 3 _ D R A MR S T # R ESET# V SS4 2 17 2
202 SA1 DQ 3 2 13 1 M _ A_ DQ 33 C 24 1 u _6 . 3 V _ X 5R _ 04 V SS4 3 17 3
[ 10 , 1 4 ] S MB _C L K 200 S CL DQ 3 3 14 1 M _ A_ DQ 34 1 V SS4 4 17 8
[ 1 0 , 1 4 ] S MB _ D A T A C 23 0 . 1 u_ 1 0 V _ X5 R _0 4
3 .3 V S S DA DQ 3 4 14 3 M _ A_ DQ 35 126 V R E F _ DQ V SS4 5 17 9
116 DQ 3 5 13 0 M _ A_ DQ 36 [ 8 ] M V R E F _D Q_ D I MM A V R E F _ CA V SS4 6 18 4
[ 4 ] M _ A _ OD T 0 120 OD T 0 DQ 3 6 13 2 M _ A_ DQ 37 R4 1 * 0_ 0 4 V SS4 7 18 5
[ 4 ] M _ A _ OD T 1 OD T 1 DQ 3 7 14 0 2 V SS4 8 18 9
R N2 M _ A_ DQ 38
1 0 K _ 8P 4 R _0 4 11 DQ 3 8 14 2 M _ A_ DQ 39 MV R E F _ D I M 0 3 VSS1 V SS4 9 19 0
1 8 S A 1 _D I M1 28 DM 0 DQ 3 9 14 7 M _ A_ DQ 40 C 92 1 u _6 . 3 V _ X 5R _ 04 8 VSS2 V SS5 0 19 5
2 7 S A 0 _D I M1 S A 1 _ D I M 1 [ 10 ] 46 DM 1 DQ 4 0 14 9 M _ A_ DQ 41 9 VSS3 V SS5 1 19 6
S A 0 _ D I M 1 [ 10 ] C 91 0 . 1 u_ 1 0 V _ X5 R _0 4
3 6 S A 1 _D I M0 63 DM 2 DQ 4 1 15 7 M _ A_ DQ 42 13 VSS4 V SS5 2
4 5 S A 0 _D I M0 136 DM 3 DQ 4 2 15 9 M _ A_ DQ 43 14 VSS5
153 DM 4 DQ 4 3 14 6 M _ A_ DQ 44 19 VSS6
170 DM 5 DQ 4 4 14 8 M _ A_ DQ 45 20 VSS7 V T T _ ME M
187 DM 6 DQ 4 5 15 8 M _ A_ DQ 46 25 VSS8
DM 7 DQ 4 6 16 0 M _ A_ DQ 47 CLOSE TO S O- DIMM _0 26 VSS9 20 3
[ 4 ] M_ A _ D Q S [ 7 : 0 ] M _ A _ DQ S0 12 DQ 4 7 16 3 M _ A_ DQ 48 31 VSS1 0 VTT1 20 4
M _ A _ DQ S1 29 DQ S0 DQ 4 8 16 5 M _ A_ DQ 49 32 VSS1 1 VTT2
M _ A _ DQ S2 47 DQ S1 DQ 4 9 17 5 M _ A_ DQ 50 37 VSS1 2 GN D 1
M _ A _ DQ S3 64 DQ S2 DQ 5 0 17 7 M _ A_ DQ 51 R 94 1 K _ 1 %_ 0 4 MV R E F _ D I M 0 38 VSS1 3 G1 GN D 2
M _ A _ DQ S4 137 DQ S3 DQ 5 1 16 4 M _ A_ DQ 52 1. 5 V 43 VSS1 4 G2
M _ A _ DQ S5 154 DQ S4 DQ 5 2 16 6 M _ A_ DQ 53 VSS1 5
M _ A _ DQ S6 171 DQ S5 DQ 5 3 17 4 M _ A_ DQ 54 R1 0 3 D D R S K -2 0 40 1 -T R 5 B
M _ A _ DQ S7 188 DQ S6 DQ 5 4 17 6 M _ A_ DQ 55
DQ S7 DQ 5 5 18 1 M _ A_ DQ 56 1K _ 1 % _ 04
[ 4 ] M _A _ D QS # [ 7 : 0 ] M _ A _ DQ S #0 10 DQ 5 6 18 3 M _ A_ DQ 57
27 DQ S0 # DQ 5 7 19 1
M _ A _ DQ S #1 M _ A_ DQ 58
M _ A _ DQ S #2 45 DQ S1 # DQ 5 8 19 3 M _ A_ DQ 59
M _ A _ DQ S #3 62 DQ S2 # DQ 5 9 18 0 M _ A_ DQ 60
M _ A _ DQ S #4 135 DQ S3 # DQ 6 0 18 2 M _ A_ DQ 61
M _ A _ DQ S #5 152 DQ S4 # DQ 6 1 19 2 M _ A_ DQ 62
M _ A _ DQ S #6 169 DQ S5 # DQ 6 2 19 4 M _ A_ DQ 63
M _ A _ DQ S #7 186 DQ S6 # DQ 6 3
DQ S7 #
D D R S K -2 04 0 1 -T R 5 B
V T T _ ME M
C1 0 3 C1 0 5 C1 0 4 C 1 06 C 1 11
1 u_ 6 . 3 V _ X 5R _ 04 1 u_ 6 . 3 V _ X5 R _0 4 1u _ 6 . 3 V _X 5 R _ 0 4 1 u _ 6 . 3V _ X 5 R _ 0 4 1 0 u _6 . 3 V _ X 5R _ 06
1 .5 V
C3 7 0 C 64 C5 7 C5 5 C6 1 C 40 C 70 C 84 C4 6
+
+ C3 4 7
*2 2 0 u_ 4 V _ V _ A 1 0 u_ 1 0 V _ Y 5 V _ 08 1 0u _ 1 0 V _Y 5 V _ 08 1 0u _ 6 . 3V _X 5 R _ 0 6 1u _ 6 . 3V _X 5 R _ 0 4 1 u _ 6 . 3V _ X 5 R _ 0 4 1 u _ 6. 3 V _ X 5 R _ 0 4 1 u _6 . 3 V _ X 5R _ 04 1 u_ 6 . 3 V _ X5 R _ 04
5 6 0 u_ 2 . 5 V _ 6 . 6* 6 . 6* 5 . 9 [ 3 , 6, 8 , 1 0 , 2 0, 26 , 2 8 , 31 , 3 3 ] 1 . 5 V
[ 10 , 3 3 ] V T T _M E M
[ 3 , 1 0, 11 , 1 2 , 13 , 1 4 , 1 5, 16 , 1 7 , 18 , 1 9 , 2 0, 23 , 2 4 , 25 , 2 7 , 2 8, 29 , 3 0 , 31 , 3 6 ] 3 . 3 V S
[ 1 9 , 29 , 3 1 ] 1 . 5 V S
1 . 5V
C3 7 C8 6 C6 8 C 82 C 48 C 49 C5 1 C5 0 C5 2 C 47
0 . 1 u_ 1 0 V _ X5 R _0 4 0 . 1u _ 1 0V _X 5 R _ 0 4 0. 1 u _ 1 0V _ X 5 R _ 0 4 0 . 1 u _ 10 V _ X 5 R _ 0 4 0 . 1 u _1 0 V _ X 5R _ 04 0 . 1 u_ 1 0 V _ X5 R _0 4 0 . 1 u_ 1 0 V _ X5 R _0 4 0 . 1u _ 1 0V _X 5 R _ 0 4 0. 1 u _ 1 0V _ X 5 R _ 0 4 0 . 1 u _ 10 V _ X 5 R _ 0 4
B - 10 DDR3 SO-DIMM_0
Schematic Diagrams
DDR3 SO-DIMM_1
SO-DIMM B CHANGE TO STANDARD
J D I M M1 A
[ 4 ] M _ B _B [ 15 : 0 ] M _ B_ B0 98 5 M_ B _ D Q0 M_ B _ D Q [ 6 3: 0 ] [ 4 ]
J D I M M1 B
M _ B_ B1 97 A0 D Q0 7 M_ B _ D Q1
96 A1 D Q1 15 1 . 5V
M _ B_ B2 M_ B _ D Q2
M _ B_ B3 95 A2 D Q2 17 M_ B _ D Q3
M _ B_ B4 92 A3 D Q3 4 M_ B _ D Q4
M _ B_ B5 91 A4 D Q4 6 M_ B _ D Q5 75 44
M _ B_ B6 90 A5 D Q5 16 M_ B _ D Q6 76 V DD 1 VSS1 6 48
M _ B _ B 10 107 A9 D Q9 33 M_ B _ D Q1 0 88 V DD 5 VSS2 0 60
M _ B _ B 11 84 A 1 0/ A P D Q1 0 35 M_ B _ D Q1 1 93 V DD 6 VSS2 1 61
M _ B _ B 12 83 A1 1 D Q1 1 22 M_ B _ D Q1 2 94 V DD 7 VSS2 2 65
M _ B _ B 13 119 A 1 2/ B C # D Q1 2 24 M_ B _ D Q1 3 99 V DD 8 VSS2 3 66
A1 5 D Q1 5 39 M_ B _ D Q1 6 106 V DD 11 VSS2 6 1 27
109 D Q1 6 41 M_ B _ D Q1 7 111 V DD 12 VSS2 7 1 28
[ 4 ] M _B _ B S 0 108 BA0 D Q1 7 51 M_ B _ D Q1 8 112 V DD 13 VSS2 8 1 33
[ 4 ] M _B _ B S 1 79 BA1 D Q1 8 53 117 V DD 14 VSS2 9 1 34
M_ B _ D Q1 9
[ 4 ] M _B _ B S 2 114 BA2 D Q1 9 40 M_ B _ D Q2 0 118 V DD 15 VSS3 0 1 38
[ 4 ] M _B _ C S # 0 121 S0 # D Q2 0 42 123 V DD 16 VSS3 1 1 39
M_ B _ D Q2 1
[ 4 ] M _B _ C S # 1 101 S1 # D Q2 1 50 M_ B _ D Q2 2 3. 3 V S 124 V DD 17 VSS3 2 1 44
[ 4] M_ B _ C L K _ D D R0 103 CK0 D Q2 2 52 V DD 18 VSS3 3 1 45
M_ B _ D Q2 3
[ 4] M_ B _ C L K _ D D R# 0 102 CK0 # D Q2 3 57 M_ B _ D Q2 4 2 0 mil s 199 VSS3 4 1 50
[ 4] M_ B _ C L K _ D D R1 104 CK1 D Q2 4 59 V DD S P D VSS3 5 1 51
M_ B _ D Q2 5
[ 4] M_ B _ C L K _ D D R# 1 73 CK1 # D Q2 5 67 M_ B _ D Q2 6 77 VSS3 6 1 55
[ 4 ] M _B _ C K E 0 C4 1 6 C4 1 5
74 CKE 0 D Q2 6 69 M_ B _ D Q2 7 122 NC1 VSS3 7 1 56
[ 4 ] M _B _ C K E 1 115 CKE 1 D Q2 7 56 M_ B _ D Q2 8 125 NC2 VSS3 8 1 61
[ 4 ] M _ B _C A S # 1u _ 6 . 3V _Y 5 V _0 4 0 . 1u _ 1 6V _Y 5 V _0 4
110 CAS # D Q2 8 58 M_ B _ D Q2 9 NCT E S T VSS3 9 1 62
[ 4 ] M _ B _R A S #
[ 4 ] M _ B _W E #
[ 9 ] S A 0_ D I M1
SA 0 _ DIM 1
SA 1 _ DIM 1
113
197
201
RAS #
W E#
SA0
D Q2 9
D Q3 0
D Q3 1
68
70
129
M_ B _ D
M_ B _ D
M_ B _ D
Q3 0
Q3 1
Q3 2
[ 2 , 9 ] T S # _D I MM 0 _1
[ 3 , 9 ] D D R 3 _ D R A MR S T #
198
30 E V E NT #
RES ET #
VSS4 0
VSS4 1
VSS4 2
1 67
1 68
1 72
Sheet 10 of 43
[ 9 ] S A 1_ D I M1
[ 9 , 1 4] S MB _ C L K
[ 9 , 14 ] S MB _ D A T A
202
200
SA1
S CL
S DA
D Q3 2
D Q3 3
D Q3 4
131
141
143
M_ B _ D
M_ B _ D
M_ B _ D
Q3 3
Q3 4
Q3 5
C2 6
C2 5
1 u _ 6. 3 V _ X 5 R _ 0 4
0 . 1 u _1 0 V _ X 5R _ 04 1
126 V RE F _ D Q
VSS4 3
VSS4 4
VSS4 5
1 73
1 78
1 79
DDR3 SO-DIMM_1
116 D Q3 5 130 [ 8] MV R E F _ D Q_ D I MM B V RE F _ C A VSS4 6 1 84
M_ B _ D Q3 6
[ 4 ] M _B _ O D T 0 120 OD T0 D Q3 6 132 M_ B _ D Q3 7 R 42 * 0 _0 4 VSS4 7 1 85
[ 4 ] M _B _ O D T 1 OD T1 D Q3 7 140 2 VSS4 8 1 89
M_ B _ D Q3 8
11 D Q3 8 142 M_ B _ D Q3 9 MV R E F _ D I M 1 3 VSS1 VSS4 9 1 90
28 DM 0 D Q3 9 147 M_ B _ D Q4 0 C 89 1 u_ 6 . 3 V _ X5 R _0 4 8 VSS2 VSS5 0 1 95
46 DM 1 D Q4 0 149 M_ B _ D Q4 1 9 VSS3 VSS5 1 1 96
C 88 0 . 1u _ 1 0V _X 5 R _ 0 4
63 DM 2 D Q4 1 157 M_ B _ D Q4 2 13 VSS4 VSS5 2
136 DM 3 D Q4 2 159 M_ B _ D Q4 3 14 VSS5
153 DM 4 D Q4 3 146 M_ B _ D Q4 4 19 VSS6
170 DM 5 D Q4 4 148 M_ B _ D Q4 5 20 VSS7 V TT _ ME M
187 DM 6 D Q4 5 158 M_ B _ D Q4 6 25 VSS8
DM 7 D Q4 6 160 M_ B _ D Q4 7 26 VSS9 2 03
[ 4 ] M_ B _ D QS [ 7 : 0 ] M _ B _ D QS 0 12 D Q4 7 163 M_ B _ D Q4 8 C LO SE TO SO -DI MM_ 1 31 VSS1 0 VTT1 2 04
29 DQ S0 D Q4 8 165 32 VSS1 1 VTT2
M _ B _ D QS 1 M_ B _ D Q4 9
M _ B _ D QS 2 47 DQ S1 D Q4 9 175 M_ B _ D Q5 0 37 VSS1 2 GN D 1
M _ B _ D QS 3 64 DQ S2 D Q5 0 177 M_ B _ D Q5 1 38 VSS1 3 G1 GN D 2
M _ B _ D QS 4 137 DQ S3 D Q5 1 164 M_ B _ D Q5 2 R 97 1 K _ 1% _ 0 4 MV R E F _ D I M 1 43 VSS1 4 G2
154 DQ S4 D Q5 2 166 1 .5 V VSS1 5
M _ B _ D QS 5 M_ B _ D Q5 3
M _ B _ D QS 6 171 DQ S5 D Q5 3 174 M_ B _ D Q5 4 D D R S K -2 0 4 01 -T R 9D
M _ B _ D QS 7 188 DQ S6 D Q5 4 176 M_ B _ D Q5 5 R 98
DQ S7 D Q5 5 181 M_ B _ D Q5 6
[ 4 ] M _B _D QS # [ 7 : 0 ] 10 D Q5 6 183
M _ B _ D QS #0 M_ B _ D Q5 7 1 K _ 1% _ 0 4
M _ B _ D QS #1 27 DQ S 0# D Q5 7 191 M_ B _ D Q5 8
M _ B _ D QS #2 45 DQ S 1# D Q5 8 193 M_ B _ D Q5 9
M _ B _ D QS #3 62 DQ S 2# D Q5 9 180 M_ B _ D Q6 0
M _ B _ D QS #4 135 DQ S 3# D Q6 0 182 M_ B _ D Q6 1
M _ B _ D QS #5 152 DQ S 4# D Q6 1 192 M_ B _ D Q6 2
M _ B _ D QS #6 169 DQ S 5# D Q6 2 194 M_ B _ D Q6 3
M _ B _ D QS #7 186 DQ S 6# D Q6 3
DQ S 7#
D D R S K -20 4 0 1-T R 9D
La y out Note :
S O- DIMM_1 i s pla c ed fa rthe r from the G MC H t ha n S O- DIMM_0
V T T _ ME M
C1 1 0 C1 0 9 C 1 07 C1 0 8 C1 1 2
1 u_ 6 . 3 V _ X5 R _0 4 1u _ 6 . 3V _X 5 R _ 0 4 1 u _ 6. 3 V _ X 5 R _ 0 4 1 u _6 . 3 V _ X 5R _0 4 10 u _ 6 . 3V _ X 5 R _ 0 6
1 .5 V
C3 7 9 C7 8 C 3 80 C4 4 C8 3 C 76 C 39 C7 3
[ 1 9 , 29 , 3 1 ] 1 . 5V S
1 0u _ 1 0V _Y 5 V _0 8 10 u _ 10 V _ Y 5V _ 0 8 1 0 u _1 0 V _ Y 5 V _ 0 8 1 u _6 . 3 V _ X 5R _0 4 1u _ 6 . 3 V _X 5 R _ 0 4 1 u _ 6. 3V _ X 5 R _ 0 4 1 u _6 . 3 V _ X 5R _ 04 1 u_ 6 . 3 V _ X5 R _0 4
[ 3, 6 , 8 , 9 , 2 0, 2 6 , 2 8 , 31 , 3 3 ] 1 . 5V
[9 ,3 3 ] V T T_ M E M
[ 3 , 9 , 1 1, 1 2 , 1 3, 1 4 , 1 5 , 16 , 1 7 , 1 8, 1 9 , 2 0, 23 , 2 4 , 25 , 2 7 , 2 8, 2 9 , 3 0 , 31 , 3 6 ] 3 . 3V S
1 . 5V
C4 5 C4 2 C 41 C8 1 C3 6 C 85 C 35 C3 8 C7 5 C 43
0 . 1u _ 1 0 V _X 5 R _ 0 4 0. 1 u _ 10 V _ X 5 R _ 0 4 0 . 1 u _1 0 V _ X 5R _ 04 0 . 1 u_ 1 0 V _ X5 R _ 0 4 0. 1u _ 1 0V _ X 5 R _ 0 4 0 . 1 u _ 10 V _ X 5R _ 04 0 . 1 u_ 1 0 V _ X5 R _0 4 0 . 1u _ 1 0V _X 5 R _ 0 4 0. 1 u _ 10 V _ X 5 R _ 0 4 0 . 1 u _1 0 V _ X5 R _0 4
DDR3 SO-DIMM_1 B - 11
Schematic Diagrams
LVDS, Inverter
3 .3 V S
PANEL CONNECTOR 30Pin & 40 Pin Co-layout--LED

30Pin R1 0 R9
V IN V IN
L2
VL ED
2 . 2 K _0 4 2 . 2K _ 0 4
PANEL.
* H C B 16 0 8 K F -1 21 T 25 J _L C D 2
2A 2A
. 1
3 1 2
2
4
P _ DD C_ DA T A
P _ DD C_ CL K
PLVDD
3 4 HI LVDS:3.3V 3A PLVDD_SEL
PL VD D_ S EL 5 6
8 7 5 6 8 B R I GH T N E S S HI ? 5V 3A
3 7 9 7 8 10 HI eDP:3.3V 3A
Q4 7 LOW ? 3.3V 3A
2 6 C5 1 7 11 9 10 12 I N V _B L O N LOW eDP;5V 3A
1 5 13 11 12 14
R 60 7 P 20 0 3 E V G
L V D S -LC LK N 15 13 14 16 L V D S -L 2 N
0. 1 u _ 50 V _ Y 5 V _ 06
L V D S -LC LK P 17 15 16 18 L V D S -L 2 P
1 M_ 0 4
19 17 18 20
4
L V D S -L1 N 21 19 20 22 E M B _H P D
23 21 22 24
L V D S -L1 P 1A
Q4 8 25 23 24 26 3. 3 V S R5 7 9 0 _ 06
25 26 3 .3 VS
D
C 58 7 MT N 7 0 02 Z H S 3 L V D S -L0 N 27 28 5 VS
27 28 3A
L V D S -L0 P 29 30
G N B _E N A V D D 29 30 PL VDD P L V DD
* 0. 1 u _ 50 V _ Y 5 V _ 0 6 3 .3 VS Q 43 3A Q 41 3A
R5 8 0 *A O 34 1 5 >100 mil A O 34 1 5 >100mil
8 7 21 6 -3 00 6 S D S D
S
C5 1 8 C 5 19 C 52 0
R5 8 1 *1 0 0 K _0 4 >100 mil
11/3 4 . 7 u _1 0 V _ Y 5 V _ 08 C 54 2 C5 4 3 C5 4 5
0. 1 u _ 16 V _ Y 5 V _ 0 4 0 . 1 u_ 1 6 V _Y 5V _0 4 *1 0 0K _0 4 R 5 77 R 6 08
G
C5 4 4 0 . 1 u _1 6 V _ Y 5 V _ 04
0 . 1 u_ 1 6 V _Y 5 V _ 0 4
0 . 1u _ 1 6V _ Y 5 V _ 0 4
1 0u _ 10 V _ Y 5 V _ 08
* 2 00 _ 1% _ 0 4
Q4 4 5V S Q 45 R2 4 4
*1 00 K _ 0 4
P L V D D _S E L G *M T N 7 00 2 Z H S 3 *A O 34 1 5
S D 1 00 K _ 0 4
Sheet 11 of 43 40Pin
S
>100 mil R5 7 8 3 3 0 K _0 4
Q 42
D
M T N 7 00 2 Z H S 3
G
LVDS, Inverter VL ED
2A
J _ L CD1
* 8 72 1 6-4 0 0 6
[ 1 6 , 2 7] N B _ E N A V D D
G
S
P _ DD C_ DA T A
1 2 P _ D D C _ D A TA [ 16 ]
P _ DD C_ CL K R 37 0 Q4 9
D
P L V D D _S E L 3 4 P _ D D C _ C LK [ 1 6 ] *M TN 7 00 2 Z H S 3
5 6 B R I GH TN E S S 1 0 0K _ 0 4
7 8 B R I G H T N E S S [ 27 ] G
9 10 I N V _B L O N
11 12
S
L V D S -L C L K N 13 14 L V D S -L 2 N
[ 1 6] L V D S -L C L K N 15 16 L V D S -L2 N [ 16 ]
L V D S -L C L K P L V D S -L 2 P 11/0 3
[ 1 6] L V D S -L C L K P 17 18 L V D S -L2 P [ 1 6 ]
L V D S -L 1 N 19 20 E M B _H P D
[ 1 6 ] L V D S -L 1 N L V D S -L 1 P 21 22 E MB _ H P D [ 2]
[ 1 6 ] L V D S -L 1 P 1A
23 24 RN1 2 8 1 0 _ 8P 4 R _0 4 M U X _ 2N
25 26 3 .3 VS [ 16 ] L V D S -U 2 N
L V D S -L 0 N 3A 7 2 M U X _ 2P
[ 1 6] LV D S -L 0N L V D S -L 0 P 27 28 [1 6 ] LV D S -U 2 P 6 3 M U X _ 1N
[ 1 6 ] L V D S -L 0 P 29 30 PL VD D [1 6 ] LV D S -U 1 N 5 4 M U X _ 1P
31 32 MU X _2 N [1 6 ] LV D S -U 1 P
[ 1 6 ] L V D S -U C L K N [ 16 ] L V D S -U 0 N RN1 3 8 1 0 _ 8P 4 R _0 4 M U X _ 0N
33 34 MU X _2 P 7 2 M U X _ 0P
[ 1 6 ] L V D S -U C L K P M U X _ 1N 35 36 MU X _0 N [1 6 ] LV D S -U 0 P 6 3
M U X _ 1P 37 38 MU X _0 P 5 4
G1
G2
39 40
[2 ] D P _ T XN 1 RN1 4 8 1 * 0_ 8 P 4 R _ 04
7 2
[2 ] D P _ TX P 1 D P _ TX P 2 [ 2 ]
G 1
6 3
G2
[2 ] D P _ T XN 0 5 4 D P _ T XN 2 [ 2]
[2 ] D P _ TX P 0 RN1 5 8 1 * 0_ 8 P 4 R _ 04
[2 ] DP _ A UX N 7 2 D P _ TX P 3 [ 2 ]
[2 ] D P _ A UXP 6 3 D P _ T XN 3 [ 2]
5 4
INVERTER CONNECTOR
3 .3 V
3. 3 V 3. 3 V
R2 6 8 * 10 0 K _ 04
U1 6 A
14
7 4L V C 08 P W U1 6 B C 2 14
14
B K L _E N 1 7 4L V C 08 P W
[ 2 7 ] B K L_ E N 3 4 * 0 . 1u _ 10 V _ Y 5 V _ 0 4
B LO N 2 6
[ 1 6 ] B L ON
5
7
R2 6 7 1 0 0K _0 4
7
U 1 6C
14
74 L V C 0 8 P W
9
[ 1 8] S B _B L O N 8 [ 1 2, 1 9 , 2 0, 2 5 , 2 9, 3 0 , 3 1, 3 6 , 3 7] 5 VS
I N V _ B LO N
3. 3 V 10 [ 3 0, 3 1 , 3 2, 3 3 , 3 4, 3 5 , 3 6, 3 7 , 3 8] VI N
[ 2 , 3 , 8 , 13 , 1 4, 15 , 1 7, 1 8 , 1 9, 2 0 , 2 2, 2 3 , 2 6, 2 8 , 3 0, 3 1 , 3 3, 3 4 , 3 5] 3 .3 V
R 2 66 *1 0 0K _0 4
U1 6 D R2 8 0 C2 1 3 [ 3, 9 , 1 0 , 12 , 1 3 , 14 , 1 5, 16 , 1 7, 1 8 , 1 9, 2 0 , 2 3, 2 4 , 2 5, 2 7 , 2 8, 2 9 , 3 0, 3 1 , 3 6] 3 .3 VS
14 [ 3 1, 3 2 , 3 4] S Y S 1 5V
7
7 4L V C 08 P W
12 *1 M_ 0 4 0 . 1 u_ 1 6V _Y 5V _ 0 4
[ 2 7, 3 0 ] L I D _ S W # 11
13
[ 1 5, 2 7 , 3 6] A L L _ S Y S _ P W R GD
7
B - 12 LVDS, Inverter
Schematic Diagrams
HDMI, CRT
HDMI PORT 5 VS _ H D MI
For ESD
FOR INTEL GRAPHIC
C
A
A
R 4 03 R 404
U5
2. 2K _ 04
2. 2 K _04
RD3 RD2 RD1
AC
AC
AC
[ 1 6] H D MI B_ D 2B P 39 22 H D MI B _D A T A2 P 5V S 5V S _H D MI *B A V9 9 R E C TI F I E R *B AV 9 9 R E C TI F I ER
38 NI _ D 1+ OU T_D 1+ 23 H D MI B _D A T A2 N *B A V 99 R EC T I FI E R
[ 1 6] H D MI B_ D 2B N IN _ D 1- OU T _D 1 - R 4 00 1_ 04 5 VS _ H D MI _I N R 40 1 1 _0 4 H D MI B _E X T1_ S C L
42 19 H D MI B _D A T A1 P
[ 1 6] H D MI B_ D 1B P 41 NI _ D 2+ OU T_D 2+ 20
[ 1 6] H D MI B_ D 1B N H D MI B _D A T A1 N H D MI B _E X T1_ S D A
IN _ D 2- OU T _D 2 -
45 16 H D MI B _D A T A0 P J_H D MI1 H D MI _ H PD-C
[ 1 6] H D MI B_ D 0B P 44 NI _ D 3+ OU T_D 3+ 17 H D MI B _D A T A0 N
[ 1 6] H D MI B_ D 0B N IN _ D 3- OU T _D 3 -
C 3 48 C 349
48 13 H D MI B _C L OC K P
[ 1 6] H D MI B_ C LK B P 47 IN _ D 4+ OU T_D 4+ 14 H D MI B _C L OC K N 1 0u _1 0V _Y 5 V_ 08 10u _1 0V _Y 5 V _0 8
[ 1 6] H D MI B_ C LK B N IN _ D 4- OU T _D 4 - 19 HD MI _H PD -C
H D MI _C T RLC L K 9 28 H D MI B _E X T1_ S C L 18 HOT P LU G D E TE C T
[1 6] H D MI _C T R LC L K SC L S C L _S I N K 29 +5 V
[ 1 6] H D MI _C T R LD A TA H D MI _C T RLD A TA 8 H D MI B _E X T1_ S D A 17
SD A S D A _S I N K H D MI B _E X T1 _S D A 16 D D C/ C E C GN D
[ 16 ] POR T C _H P D R 39 8 * 10 mil _0 4 M_P OR TB _ H PD # _R 7 30 H D MI _ H PD -C R 55 10 0K _ 04 S DA 15 HD MI B _E XT 1_ S C L
H PD H P D _S I N K 14 S CL
R6 1 *4. 7 K_ 04 25 2 R E SE R V E D 13 HD MI _C EC
3 . 3V S OE# V C C [ 1 ] 11 3. 3V S T MD S _C LO C K# 12 CE C
R6 8 *0_ 04 V C C [ 2 ] 15 TMD S C LO C K-
D C C _E N # 32 C 33 8 C 3 39 11 R 70 *0_ 04
10 D C C _E N # V C C [ 3 ] 21 T MD S _C LO C K 10 CLK S H IE L D
R T_E N# V C C [ 4 ] 26 0. 1 u_ 16V _ Y 5V _0 4 0. 1 u_ 16 V_ Y 5V _ 04 TMD S C LO C K+ 9 TM D S_ DA TA 0# 4 3 H D MI B _D A TA 0 N
P C0 3 V C C [ 5 ] 33 8 T MDS D A T A0 - L1 0
P C1 4 PC 0 V C C [ 6 ] 40 S H I EL D 0 7 TM D S_ DA TA 0 1 2 H D MI B _D A T A0 P
10/28 PC 1 V C C [ 7 ] 46 TMD S D A TA 0+
R 3 96 4. 02 K _1% _0 4 6 T MD S _D A TA 1# 6 *W CM20 12 F2 S -SH OR T
R EX T V CC[8 ] TMD S D A TA 1- 5 R 69 *0_ 04
1 T MD S _D A TA 1 4 S H I E LD 1 R 72 *0_ 04
3. 3 VS R5 3 *4. 7 K_ 04 34 GN D [ 1 ] 5 C 31 C 3 40 TMD S D A TA 1+ 3 TM D S_ DA TA 2# 4 3 H D MI B _D A TA 2 N
R5 1 *4. 7 K_ 04 35 OE_ 1 GN D [ 2 ] 12 2 T MDS D A T A2 - L1 2
QE_ 2 GN D [ 3 ] 18
GN D [ 4 ] 24
GN D [ 5 ] 27
GN D [ 6 ] 31
0. 1 u_ 16V _ Y 5V _0 4 0. 1 u_ 16 V_ Y 5V _ 04 S H I EL D 2
TMD S D A TA 2+
1 TM D S_ DA TA 2 1 2
*W CM20 12 F2 S -SH OR T
R 71 *0_ 04
H D MI B _D A T A2 P
Sheet 12 of 43
G ND
GND
GND
GND
GN D [ 7 ] 36
49
GN D
GN D [ 8 ] 37
GN D [ 9 ] 43
GN D [ 10 ]
C 30
HDMI, CRT
GND1
GND2
GND3
GND4
0. 1 u_ 16V _ Y 5V _0 4
S N 75 D P 139 R 64 *0_ 04
P I N 4 9= GN D
HD MI B_ C LOC K P 4 3 T MD S _C L OC K C 12 81 7-11 9A 5 -L
L9
HD MI B_ C LOC K N 1 2 T MD S _C L OC K #
PS8101 (6-03-08101-032) PIN TO PIN *W C M20 12 F 2S -SH OR T
R 65 *0_ 04
R 66 *0_ 04
R 54 4. 7 K_ 04 D C C _E N #
3. 3V S HD MI B_ D A TA 1P 4 3 T MD S _D A TA 1
R 52 4. 7 K_ 04 P C0 L 11
HD MI B_ D A TA 1N 1 2 T MD S _D A TA 1 #
R 395 *4. 7 K_ 04 P C1 *W C M20 12 F 2S -SH OR T
? ? ?
R 67 *0_ 04
CRT PORT 3. 3 V S 5 VS
J_ C R T1 6-20-14X30-015
6-19-31001-264 10 8A H 15 F ST 04 A 1C C
10/29
1
2
3
4
RE D 1
9
L7 . 0_ 04 L8 . FC M1 00 5MF -60 0T 01 2 24 mil
RN1 [ 16 ] D AC _ R E D L6 . 0_ 04 L5 . FC M1 00 5MF -60 0T 01 GR N 10
2. 2 K _8P 4 R _0 4 [ 16 ] D AC _ GR E EN L4 . 0_ 04 L3 . FC M1 00 5MF -60 0T 01 B LU E 3
[ 16 ] D AC _ BL UE 11
8
7
6
5
1 50 _1 %_0 4 4
*10 p_ 50 V_ N P O _0 4
C 1 7 * 10 p_5 0V _ N PO _ 04
C 2 1 *1 0p _5 0V _N P O _ 04
22 p_ 50 V_ N P O _0 4
2 2p _5 0V _N P O _0 4
1 0p _50 V _N P O _0 4
10 p_ 50 V_ N P O _0 4
150 _1 %_ 04
15 0_ 1% _04
22p _5 0V _ N PO _ 04
10 p_5 0V _ N PO _ 04
12 DDCDAT A
U 33 5
10 9 DD C D A TA 13 HS Y NC
[ 16 ] D A C _D D C AD A TA DDC_ IN1 D D C _OU T 1 6
11 12 DD C L K 14 V S Y NC
[ 16 ] D A C _D D C AC L K DDC_ IN2 D D C _OU T 2 7
13 14 C R T_ H S Y N C R 37 2 3 3_0 4 HS Y N C 15 DDCL K
[ 16 ] D A C _HS Y N C S Y N C _ IN 1 S Y N C _OU T 1 8
R1 4
C2 0
C1 4
C 1 5 1 000 p_ 50 V_ X 7R _ 04
C 7 10 00 p_ 50 V_ X 7R _0 4
15 16 C R T_ V SY N C R 37 3 3 3_0 4 VS Y NC
R 15
R 13
C 13
C 12
C 16
C 18
C 19
C 11 22 0p _50 V _N P O _0 4
C 9 2 20 p_ 50 V_ N PO _04
[ 16 ] D A C _ VS Y N C S Y N C _ IN 2 S Y N C _OU T 2
1 3
GN D1
GN D2
5V S B LU E
V C C _ SY N C V ID E O_ 1
2 4 GR N
3 . 3V S V C C _ VI D E O V ID E O_ 2
7 5 RE D
3. 3V S V CC_ DDC V ID E O_ 3
8 6
BYP GN D
TP D 7S 0 19
0. 2 2u _1 0V _Y 5V _ 04
0. 22 u_ 10 V_ Y 5V _0 4
0 . 22u _1 0V _Y 5 V_ 04
C 3 13
C 31 2
C 3 11
[ 3, 9 ,1 0, 1 1, 13 , 14 , 15, 1 6, 1 7, 18 , 19 ,2 0, 2 3, 24 , 25 , 27, 2 8, 2 9, 30 , 31 ,3 6] 3. 3 VS
[ 1 1, 19 , 20 , 25, 2 9, 3 0, 31 , 36 ,3 7] 5V S
HDMI, CRT B - 13
Schematic Diagrams
CougarPoint - M 1/9
RT C V CC
V DD 3
20mil D 17
B A T5 4 C S 3
1 A
20mil
CougarPoint - M 3 .3 VS
C 3 C 4 66 1 u_ 6 . 3 V _ X5 R _0 6 C4 6 8
2 A
R T C_ V B A T _ 1
R 47 6
R4 7 7
2 0K _1 % _ 04 R TC CL EA R
1 8 p_ 5 0 V _ N P O _0 4
(HDA,JTAG,SATA) S A T A _ L E D # R 4 45
S E R IRQ R 1 68
*1 0 K _ 0 4
1 0K _0 4
11 /05
2
1
2
1
X 12 G P I O2 1 R 1 83 1 0K _0 4
1 K_ 0 4 X1 3 R 4 78
U 3 7A
*3 2 . 7 68 K H z
C4 6 5 JO P E N 1 MC -30 6 _ 32 . 7 6 8K H z
1 0 M_ 0 4
3
4
3
4
J _R T C 1 1 u _6 . 3 V _ X5 R _0 6 *OP E N _ 1 0m i l -1M M C4 6 3 RT C_ X 1 A2 0 C3 8
R T C_ V B A T 1 RT CX 1 F W H0 / L A D 0 A3 8 LP C _ A D 0 [ 2 3 , 27 ]
1 8 p_ 5 0 V _ N P O _0 4
1 F W H1 / L A D 1 LP C _ A D 1 [ 2 3 , 27 ]
2
10mil R TC _ X2 C2 0 B3 7
LPC
RT CX 2 F W H2 / L A D 2 C3 7 LP C _ A D 2 [ 2 3 , 27 ]
J_RTC1 2 R2 3 7
Zo= 5 0O? 5% R T C _ R S T# D2 0 F W H3 / L A D 3 LP C _ A D 3 [ 2 3 , 27 ] R 2 30
RT CR S T # D3 6 3 . 3V S
2 0K _1 % _ 04
8 52 0 5 -02 7 0 1 S R T C _ R S T# G2 2 F W H 4 / LF R A M E # LP C _ F R A M E # [ 23 , 2 7 ] 1 0 K_ 0 4
S RT C RS T # E3 6
R 2 36 C2 0 6 S M_ I N T R U D E R # K2 2 L DRQ 0 # K3 6 B o a rd I D R2 2 9
1 2
RTC
INT RU DE R # L D R Q1 # / GP I O 2 3
*1 0 K _ 04
1 M _0 4 1 u _6 . 3 V _ X5 R _0 6 R2 3 5 3 3 0 K _0 4 P C H _I N T V R M E N C1 7 V5
R T CVC C I N T V R ME N S E RI RQ S E R I R Q [ 2 3 , 2 7]
A M3
H DA _ B IT CL K _ R N3 4 S AT A0 RXN A M1 S A TA RX N0 [2 5 ]
HD A _ B CL K S A TA 0 R XP AP7 S A TA RX P 0 [ 2 5]
SATA HDD
SATA 6G
H DA _ S Y N C_ R L34 S A T A 0T X N AP5 S A TA TX N 0 [2 5 ]
R2 2 4 1 K_ 0 4
3. 3 V S NO REBOOT STRAP 3 . 3A _ 1 . 5 A _ H D A _I O HD A _ SYN C S A T A 0 T XP S A TA TX P 0 [2 5 ]
H DA _ S P K R T10 A M1 0
[2 9 ] HD A _ S P K R SPKR S AT A1 RXN A M8
HD A _ S P K R H DA _ RS T # _ R K3 4 S A TA 1 R XP AP1 1
R 19 5 *1 K _ 0 4
HD A _ RS T # S A T A 1T X N AP1 0
S A T A 1 T XP
N O REB OO T ST RA P: HD A_ SP KR Hi gh E na bl e E3 4 A D7
Sheet 13 of 43 [ 29 ] H D A _ S D I N 0 HD A _ S DIN 0 S AT A2 RXN A D5 S A T A RX N2 [2 5 ]
S A T A R X P 2 [ 2 5]
[ 28 ] H D A _ S D I N 1
G3 4
HD A _ S DIN 1
S A TA 2 R XP
S A T A 2T X N
A H5
A H4 S A T A TX N 2 [ 2 5 ] SATA ODD
CougarPoint - M 1/9 3. 3 V S iTPM ENABLE/DISABLE
10/29
C3 4
HD A _ S DIN 2
S A T A 2 T XP
AB8
S A T A TX P 2 [ 2 5 ]
IHDA
R 16 7 *1 K _ 0 4 SPI_ SI R2 6 9 *1 K _ 04 A3 4 S AT A3 RXN AB1 0
3. 3 A _ 1 . 5 A _H D A _ I O HD A _ S DIN 3 S A TA 3 R XP AF3
R B 7 5 1S - 40 C 2 D1 2 S A T A 3T X N AF1
T PM FU NC TI ON :S PI_ SI H ig h Ena bl e S A T A 3 T XP
R 46 8 * 28 m i l_ 0 6 A C H DA _ S DO UT _ R A3 6
[ 2 7 ] M E _W E HD A _ S DO Y7
SATA
S AT A4 RXN Y5
R5 3 8 * 1 0K _ 0 4 C3 6 S A TA 4 R XP A D3
11/05 3. 3 V H D A _ D OC K _ E N # / G P I O3 3 S A T A 4T X N A D1
Flash Descriptor Security Overide R5 3 9 0_04 N3 2 S A T A 4 T XP
[ 26 ] U S B 3 0_ S M I # H D A _ D OC K _ R S T # / GP I O1 3 Y3
S AT A5 RXN Y1
HDA_SDOUT HIGH = Enable 10/28 S A TA 5 R XP AB3
LOW = Disable P C H _ J T A G_ T C K _ B U F J3 S A T A 5T X N AB1
Flash Descriptor J TA G _ TC K S A T A 5 T XP
Security Overide P C H _ J T A G_ T MS H 7 Y1 1 S A T A I C OMP R1 7 2 3 7. 4 _ 1 % _0 4 1. 0 5 V S
J TA G _ TM S S A TA I C OM P O
Low = Disabled-(Default)
JTAG
P C H _ J T A G_ T D I K5 Y1 0
High = Enabled J TA G _ TD I S A T A I C O MP I
P C H _ J T A G_ T D O H 1
3. 3 V S J TA G _ TD O AB1 2 S A T A 3 C O MP R1 7 1 4 9. 9 _ 1 % _0 4
NC 1 BIOS ROM S A T A 3 R C OM P O
S A T A 3 C O MP I
AB1 3
1. 0 5 V S
*N C _ 0 4 SPI_* = 1.5"~6.5"
C 22 1 R N 16 S P I _ S C LK R4 4 4 * 0 _0 4 S P I_ S CL K _ R T 3 A H1 R B IA S _ S A T A 3 R4 3 2 7 50 _ 1 %_ 0 4
* 0. 1 u _ 16 V _ Y 5V _ 0 4 0_ 8 P 4 R _ 0 4 S P I_ CL K S A T A 3 RB IA S
S P I_ S CL K _ R 8 1 S P I _ C S 0# R1 7 6 * 0 _0 4 S P I _ C S 0 # _R Y 1 4
U 17 32Mbit S P I_ S I_ R 7 2
H S P I _ S C L K [ 2 7]
H S P I _ M S I [ 2 7]
S P I_ CS 0 #
3 .3 VS_ SPI 8 5 SPI_ SI S P I _ S O_ R 6 3 S P I_ CS 1 # T1
VD D SI HS P I_ M S O [2 7 ] S P I_ CS 1 #
S P I_ CS 0 # _ R 5 4 P3 S A TA _L E D #
SPI
2 SPI_ SO H S P I _ C E # [ 27 ] S A TA L E D # S A T A _ L E D# [2 8 ]
R2 9 4
*3 . 3 K _ 1% _ 0 4 SO S P I_ S I R1 7 8 * 0 _0 4 S P I_ S I_ R V4 V1 4 G P I O 21
3 1 S P I _ MO S I S A TA 0 G P / GP I O 2 1
S P I _W P # S P I_ CS 0 #
W P# CE # S P I_ S O R 4 41 *3 3 _ 04 S P I _ S O_ R U 3 P1
6 S P I _ MI S O S A TA 1 G P / GP I O 1 9 B B S _ B I T 0 [ 1 7]
R2 9 1 SPI_ SCL K
*3 . 3 K _ 1% _ 0 4 S CK
S P I _H OL D # 7 4 C o u g ar P oi n t _ R e v _ 1p 0
H OL D # VSS
* P C T 2 5 V F 0 32 B
P C B F oo t p ri nt = M -S OP 8B 10/29
3. 3 V
R N1 7
* 3 3_ 8 P 4 R _ 0 4
8 1 H D A _ S D OU T _ R 4 5
[ 2 8 ] H D A _ S D O _M D C 7 2 3 6 H D A _ S D O U T [ 2 9]
H DA _ S Y NC_ R
[ 2 8 ] H D A _ S Y N C _ MD C 6 3 H D A _ R S T# _ R 2 7 H D A _ S Y N C [ 2 9]
R 23 8 R 21 8 R 22 3 [ 2 8] H D A _R S T #_ M D C H DA _ RS T # [2 9 ]
5 4 H DA _ B IT CL K _ R 1 8
[ 2 8 ] H D A _ B I T C L K _ MD C H D A _ B I TC L K [ 2 9]
2 1 0_ 1 % _0 6 2 1 0_ 1 % _0 6 2 1 0_ 1 % _ 06
33 _ 8 P 4R _ 04
11/04
P C H _ J T A G_ T MS R N1 8
P C H _ J T A G_ T D I [ 20 ] 3 . 3 A _ 1. 5 A _ H D A _ I O
P C H _ J T A G_ T D O [ 15 , 2 0 ] R T C V C C
[ 11 , 1 2 , 1 9, 2 0 , 2 5, 29 , 3 0 , 31 , 3 6 , 3 7] 5 V S
[ 2 2, 24 , 2 7 , 31 , 3 2 , 3 8] V D D 3
[ 2 , 3, 8, 1 1 , 1 4, 1 5 , 1 7 , 18 , 1 9 , 20 , 2 2 , 2 3, 2 6 , 2 8, 30 , 3 1 , 33 , 3 4 , 3 5] 3 . 3 V
[ 3 , 9 , 10 , 1 1 , 1 2, 1 4 , 1 5, 1 6 , 1 7 , 18 , 1 9 , 20 , 2 3 , 2 4, 2 5 , 2 7, 28 , 2 9 , 30 , 3 1 , 3 6] 3 . 3 V S
R 45 9 R 21 1 R 20 9
[ 14 , 1 5 , 19 , 2 0 , 3 4] 1 . 0 5 V S
10 0 _ 1% _ 0 4 1 0 0_ 1 % _0 4 1 0 0_ 1 % _ 04
R4 5 8 5 1 _0 4 P C H _ J T A G_ T C K _ B U F
B - 14 CougarPoint - M 1/9
Schematic Diagrams
CougarPoint - M 2/9
3 .3 V
CougarPoint - M (PCI-E,SMBUS,CLK) S MB _ C L K 8
R N9
2 . 2 K _ 8P 4R _ 04
1
S MB _ D A T A 7 2
S ML 0 _ D A T A 6 3
S ML 0 _ C L K 5 4
U 3 7B S MC _ C P U _ TH E R M R 2 49 2. 2 K _ 0 4
S MD _ C P U _ TH E R M R 2 56 2. 2 K _ 0 4
T 71 PCI E _ RX N1 B G 34 D R A MR S T _ C N TR L R 4 82 1K _ 0 4
T 72 PCI E _ RX P 1 B J 34 P E RN 1 E1 2 B T _S B D #
PCI E _ TX N 1 A V 32 P E RP 1 S MB A LE R T # / GP I O1 1 B T _ S B D # [ 2 2] B T _S B D #
T 12 R 2 48 10 K _ 0 4
T 13 PCI E _ TX P 1 A U 32 P E T N1 H 14 S MB _C L K LP D _ S P I _ I N T R # R 2 50 10 K _ 0 4
P ETP1 S MB C L K S M B _ CL K [9 ,1 0 ]
P E G_ B _ C L K R Q # R 4 81 *1 0 K _ 04
BE 34 C 9 S MB _D A T A P C I E C L K R Q0 # R 5 40 *1 0 K _ 04
[ 26 ] P C I E _ R XN 2 _ U S B 3 0 P E RN 2 SM BD ATA S M B _ DA T A [9 ,1 0 ]
BF 34 P C I E C L K R Q7 # R 5 41 *1 0 K _ 04
[ 26 ] P C I E _ R XP 2_ U S B 3 0 BB 32 P E RP 2
C 13 1 0 . 1 u _1 0 V _ X 7R _ 0 4 P C I E _ TX N 2_ C
[ 2 6 ] P C I E _ T XN 2 _ U S B 3 0 P C I E _ TX P 2 _ C AY 32 P E T N2 P E G_ C L K R E Q #
[ 2 6 ] P C I E _ T XP 2_ U S B 3 0 C 13 2 0 . 1 u _1 0 V _ X 7R _ 0 4 R 2 19 *1 0 K _ 04
SMBUS
P ETP2 A1 2 D R A MR S T _ C N T R L 3G _ B _ C L K R Q# R 2 62 *1 0 K _ 04
B G 36 S M L 0A LE R T # / GP I O6 0 DR A M RS T _ CN T RL [3 ,8 ]
[ 22 ] P C I E _ R XN 3 _ W L A N B J 36 P E RN 3 C 8 S ML 0 _ C L K 3 .3 V S
[ 22 ] P C I E _ R XP 3_ W L A N A V 34 P E RP 3 S M L0 C L K
C 14 2 0 . 1 u _1 0 V _ X 7R _ 0 4 P C I E _ TX N 3_ C
[ 22 ] P C I E _ T X N 3 _ W L A N P C I E _ TX P 3 _ C A U 34 P E T N3 G 12 S ML 0 _ D A T A P C I E C L K R Q1 #
[ 2 2 ] P C I E _ T XP 3_ W L A N C 14 3 0 . 1 u _1 0 V _ X 7R _ 0 4 R 5 43 *1 0 K _ 04
P ETP3 S M L0 D A T A D G P U _ P R S N T# R 4 63 *1 0 K _ 04
1 0/ 29
B F 36 P C I E C L K R Q2 # R 1 69 *1 0 K _ 04
[2 4 ] P C I E _ R X N 4_ G L A N B E 36 P E RN 4
[2 4 ] P C I E _ R X P 4 _ GL A N A Y 34 P E RP 4 C 13
C 13 0 0 . 1 u _1 0 V _ X 7R _ 0 4 P C I E _ TX N 4_ C L P D_ S P I_ IN T R#
[2 4 ] P C I E _ T XN 4 _G L A N P C I E _ TX P 4 _ C B B 34 P E T N4 S M L1 A L E R T # / P C H H OT # / GP I O7 4
[2 4 ] P C I E _T X P 4 _ GL A N C 12 9 0 . 1 u _1 0 V _ X 7R _ 0 4
P ETP4 E1 4 S MC _ C P U _ T H E R M
BG 37 S M L1 C LK / GP I O5 8 S M C _ C P U _ T H E R M [ 2 , 27 ]
PCI-E*
BH 37 P E RN 5 M 16 S MD _ C P U _ T H E R M
AY 36 P E RP 5 S ML 1 D A TA / GP I O7 5 S M D _ C P U _ T H E R M [ 2 , 27 ]
BB 36 P E T N5
P ETP5
B J 38 CL K _ B U F _ CP Y CL K _ N R1 3 2 1 0K _ 0 4
10 /2 9
B G 38 P E RN 6 CL K _ B U F _ CP Y CL K _ P R1 3 4 1 0K _ 0 4
Sheet 14 of 43
Controller
A U 36 P E RP 6 M7 CL _ CL K 1 CL K _ B U F _ D O T9 6 _ N R2 3 2 1 0K _ 0 4
A V 36 P E T N6 C L _C L K 1 CL _ CL K1 [2 2 ] CL K _ B U F _ D O T9 6 _ P R2 4 0 1 0K _ 0 4
P ETP6
CougarPoint - M 2/9
Link
B G 40 T11 C L _ D A TA 1 R N1 9
P E RN 7 C L _D A T A 1 C L _ D A TA 1 [ 22 ]
B J 40 1 0 K _ 8P 4R _ 0 4
A Y 40 P E RP 7 CL K _ P C IE _ ICH 8 1
PCI-E x1 Usage B B 40 P E T N7 P1 0 C L _ R S T# 1 CL K _ P C IE _ ICH # 7 2
P ETP7 CL _ RS T 1 # C L _ R S T# 1 [ 2 2 ]
CL K _ S A T A # 6 3
BE 38 CL K _ S A T A 5 4
Lane 1 X BC 38 P E RN 8
P E RP 8
Lane 2 USB3.0 AW
AY
38
38 P E T N8
P E G_ C L K R E Q # R 2 12 *1 0 K _ 04
Lane 3 WLAN P ETP8 P C I E C L K R Q2 # R 1 75 10 K _ 0 4
M 10
Lane 4 GLAN / CARD READER Y 40 P E G _A _C L K R Q # / GP I O4 7
P E G_ C L K R E Q # CL K _ B U F _ RE F 1 4
LA N _ C L K R E Q #
R 2 08 10 K _ 0 4
R 2 39 *1 0 K _ 04
Lane 5 NEW CARD Y 39 C L K OU T _ P C I E 0N
C L K OU T _ P C I E 0P AB3 7
Lane 6 X C L K O U T _ P E G_ A _ N
CLOCKS
P C I E C L K R Q0 # J2 AB3 8
P C I E C L K R Q 0 # / GP I O7 3 CL K O UT _ P E G _ A _ P
Lane 7 X
Lane 8 X A B 49 AV2 2 10 0M Hz
A B 47 C L K OU T _ P C I E 1N C L K OU T _D MI _ N AU 2 2 C LK _E XP _N [3 ]
C L K OU T _ P C I E 1P CL K O UT _ DM I_ P C LK _E XP _P [3 ]
P C I E C L K R Q1 # M1
P C I E C L K R Q 1 # / GP I O1 8 AM 1 2 C L K _ D P _ N _R R 154 *1 0 m i _l 0 4
1 20 M Hz
CL K O UT _ DP _ N AM 1 3 C L K _ DP _ P _ R R 150 *1 0 m i _l 0 4 C L K _ D P _N [3 ]
A A 48 C LK O U T_ D P _ P C L K _ D P _P [3 ]
[ 2 6 ] C LK _P C I E _ U S B 3 0 # A A 47 C L K OU T _ P C I E 2N
[2 6 ] CL K _ P C IE _ US B 3 0 C L K OU T _ P C I E 2P BF1 8 C L K _ P C I E _I C H # 10 0M Hz
V 10 C L K I N _D MI _ N BE1 8
P C I E C L K R Q2 # C L K _ P C I E _I C H
[ 2 6 ] P C I E C LK R Q 2# P C I E C L K R Q 2 # / GP I O2 0 CL KIN _ DM I_ P
1 00 MHz Y 37 BJ 3 0 C L K _ BUF _ C PY C L K_ N
[ 2 2 ] C L K _P C I E _ M I N I # Y 36 C L K OU T _ P C I E 3N C L K I N _ G N D 1_ N BG 3 0 C L K _ BUF _ C PY C L K_ P
[ 2 2] C L K _ P C I E _ MI N I C L K OU T _ P C I E 3P C L K I N _G N D 1 _ P
A8
[ 2 2 ] W LA N _ C L K R E Q # P C I E C L K R Q 3 # / GP I O2 5 G 24 C L K _ B U F _ D OT 9 6 _N 96 M Hz
C LK I N _ D OT _ 96 N E2 4 C L K _ B U F _ D OT 9 6 _P
1 00 MHz Y 43 C L K I N _D OT _ 9 6 P
[ 2 4 ] C L K _ P C I E _ GL A N # Y 45 C L K OU T _ P C I E 4N
[ 2 4 ] C L K _ P C I E _G L A N C L K OU T _ P C I E 4P AK7 C L K_ SATA# 1 00 M Hz
L A N _ C LK R E Q # L 12 C L K IN_ S A T A _ N AK5 C L K_ SATA
O nly PC IECLKRQ [ 2:1 ]# on PCH a re core w e l l pow e re d. P C I E C L K R Q 4 # / GP I O2 6 CL K IN _ S A T A _ P
*X 8 A 0 25 0 0 0 F G1 H _2 5 M H z
Al l othe r PC IECLKRQ x # a re suspe nd w e ll pow e re d. V 45 K4 5 1 4.3 1 8M Hz C4 4 7 22 p _ 5 0 V _N P O _0 4
C L K _ BUF _ R EF 1 4
V 46 C L K OU T _ P C I E 5N R E F C LK 14 I N
C L K OU T _ P C I E 5P
1
1 0/ 29 R 43 8
3 3M Hz
4
L 14 H 45 X1 X 11
P C I E C L K R Q 5 # / GP I O4 4 C LK I N _ P C I L OO P B A C K C LK _P C I _ F B [ 17 ]
X 8A 02 5 0 0 0F G1 H _ 2 5 MH z
3
2
A B 42 V4 7 X T A L 2 5_ I N 1 M _ 04
A B 40 C L K OU T _ P E G_ B _ N X T A L 2 5_ I N V4 9 X T A L 2 5_ O U T C4 4 4 22 p _ 5 0 V _N P O _0 4
C L K OU T _ P E G_ B _ P X T A L 25 _ OU T
P E G _B _C L K R Q # E6
P E G_ B _ C LK R Q # / GP I O 5 6
Y 47 X C LK _R C O MP R4 3 7 9 0 . 9 _1 % _ 0 4
X C L K _ R C OM P 1 . 0 5V S
V 40
V 42 C L K OU T _ P C I E 6N
C L K OU T _ P C I E 6P 90.9-O ? % pullup to +VccIO [ 2 , 3, 8, 1 1 , 1 3 , 1 5, 1 7 , 1 8 , 1 9, 20 , 2 2 , 2 3 , 26 , 2 8 , 3 0 , 31 , 3 3 , 3 4 , 35 ] 3. 3 V
(1.05V, S0 rail)close to [ 3, 9, 1 0 , 1 1 , 1 2, 1 3 , 1 5 , 1 6, 1 7 , 1 8 , 1 9, 20 , 2 3 , 2 4 , 25 , 2 7 , 2 8 , 29 , 3 0 , 3 1 , 36 ] 3. 3 V S
3 G_ B _ C L K R Q# T 13
P C I E C L K R Q 6 # / GP I O4 5 [ 1 3 , 15 , 1 9 , 2 0 , 34 ] 1. 0 5 V S
PCH
V 38 K4 3
V 37 C L K OU T _ P C I E 7N C L K O U T F L E X 0 / GP I O6 4
FLEX CLOCKS
C L K OU T _ P C I E 7P F47
P C I E C L K R Q7 # K 12 C L K O U T F L E X 1 / GP I O6 5
P C I E C L K R Q 7 # / GP I O4 6 H 47
A K 14 C L K O U T F L E X 2 / GP I O6 6
A K 13 C L K OU T _ I T P XD P _ N K4 9 D GP U _ P R S N T #
C L K OU T _ I T P XD P _ P C L K O U T F L E X 3 / GP I O6 7
C o u g arP oi n t _ R e v _ 1 p 0
CougarPoint - M 2/9 B - 15
Schematic Diagrams
CougarPoint - M 3/9
CougarPoint -M (DMI,FDI,GPIO) 3. 3V
A C _ P RE S E NT R 54 4 1 0K _0 4
U3 7 C
P C IE _ W A K E # R 48 6 1 0K _0 4
BC 2 4 B J 14 P M _ S L P _ LA N # R 24 7 *1 0 K _ 0 4
[ 2] D MI _R XN0 BE2 0 DM I0 RX N F DI_ RX N 0 AY1 4 FD I _ TX N 0 [ 2]
[ 2] D MI _R XN1 BG 1 8 DM I1 RX N F DI_ RX N 1 BE1 4 FD I _ TX N 1 [ 2] S W I#
[ 2] D MI _R XN2 FD I _ TX N 2 [ 2] R 48 5 1 0K _0 4
BG 2 0 DM I2 RX N F DI_ RX N 2 B H1 3
[ 2] D MI _R XN3 DM I3 RX N F DI_ RX N 3 B C1 2 FD I _ TX N 3 [ 2] P W R_ B T N#
FD I _ TX N 4 [ 2] R 25 2 *1 0 K _ 0 4
BE2 4 F DI_ RX N 4 B J 12
[ 2] D MI _R X P 0 BC 2 0 DM I0 RX P F DI_ RX N 5 B G1 0 FD I _ TX N 5 [ 2] P M _ B A T L OW # R 24 6 8 . 2 K _0 4
[ 2] D MI _R X P 1 BJ 1 8 DM I1 RX P F DI_ RX N 6 B G9 FD I _ TX N 6 [ 2]
[ 2] D MI _R X P 2 BJ 2 0 DM I2 RX P F DI_ RX N 7 FD I _ TX N 7 [ 2]
S U S _ P W R _A C K R 48 3 1 0K _0 4
[ 2] D MI _R X P 3 DM I3 RX P B G1 4
AW 2 4 F DI_ R XP 0 BB1 4 FD I _ TX P 0 [2 ]
[ 2] D MI _T X N 0 AW 2 0 DM I 0 TX N F DI_ R XP 1 BF1 4 FD I _ TX P 1 [2 ] 3. 3V S
[ 2] D MI _T X N 1 BB1 8 DM I 1 TX N F DI_ R XP 2 B G1 3 FD I _ TX P 2 [2 ]
[ 2] D MI _T X N 2 AV1 8 DM I 2 TX N F DI_ R XP 3 BE1 2 FD I _ TX P 3 [2 ] P M _ CL K R UN #
[ 2] D MI _T X N 3 FD I _ TX P 4 [2 ] R 44 7 8 . 2 K _0 4
DM I 3 TX N F DI_ R XP 4 B G1 2
DMI
FDI
AY 24 F DI_ R XP 5 B J 10 FD I _ TX P 5 [2 ]
[ 2 ] D MI _ T X P 0 AY 20 D M I 0 TX P F DI_ R XP 6 B H9 FD I _ TX P 6 [2 ]
[ 2 ] D MI _ T X P 1 AY 18 D M I 1 TX P F DI_ R XP 7 FD I _ TX P 7 [2 ]
[ 2 ] D MI _ T X P 2 AU 18 D M I 2 TX P
[ 2 ] D MI _ T X P 3 D M I 3 TX P AW 1 6
F DI_ IN T F D I_ INT [2 ]
R4 2 3 49 . 9 _ 1% _ 0 4 D M I _C OM P _ R BJ 2 4 AV1 2
1 . 0 5V S D M I _ Z C O MP F DI_ F S Y NC 0 F D I_ F S Y N C0 [2 ] R TC V C C
BG 2 5 B C1 0
D M I _ I R C OM P F DI_ F S Y NC 1 F D I_ F S Y N C1 [2 ]
R4 2 2 75 0 _ 1% _ 0 4 D M I _2 R B I A S BH 2 1 AV1 4 D S W O DV R E N R4 7 2 3 30 K _ 0 4
DM I2 RB IAS F DI_ L S Y NC 0 F D I _ LS Y N C 0 [ 2 ]
BB1 0 R4 7 9 *3 3 0 K _ 04
Sheet 15 of 43 F DI_ L S Y NC 1 F D I _ LS Y N C 1 [ 2 ]
A1 8 D S W OD V R E N
CougarPoint - M 3/9 DS W V RM E N
System Power Management

S U S _ P W R_ A C K C 12 E2 2 D P W RO K R2 5 7 * 1 0m i l _0 4 R S MR S T #
DSWODVREN - On Die DSW VR Enable
S USA CK # D P W R OK
R 45 3 1 0 K_ 0 4
3. 3 V S
K3 B9
HI Enabled (DEFAULT)
S Y S _ RE S E T # P C IE _ W A K E #
SYS_ R ESET # W AKE # P C I E _W A K E # [ 2 2 , 24 , 2 6 ]
S Y S _ P W RO K P1 2 N3 P M _ CL K RU N#
LOW Disabled
S Y S_ P W RO K C L K R U N # / GP I O 3 2 P M _ C L K R U N # [ 23 ]
C 5 89 *0 . 1 u _ 16 V _ Y 5V _0 4
R2 7 0 1 0 K _ 04 P M_ P C H _ P W R OK _ R L22 G8
[ 27 ] P M_ P C H _ P W R OK P W R OK S U S _ S T A T # / GP I O 6 1 S 4 _ S T A T E # [ 2 3]
R2 1 3 *1 0 mi l _ 04 P M_ MP W R O K L10 N1 4 S U S CL K
A P W R OK S U S C LK / GP I O 6 2
11/03
B1 3 D1 0 SL P_ S5 #
[ 3 ] P M_ D R A M_ P W R G D D R A MP W R O K S L P _ S 5 # / GP I O 6 3
R S MR S T # C 21 H4
[ 27 ] R S MR S T # RS M RS T # SL P_ S4 # S U S C # [ 27 , 3 3 ]
R 26 1 1 0K _0 4
S US _ P W R _ A CK K1 6 F4
[ 2 7] S US _ P W R _ A CK S U S W A R N # / S U S P W R D N A C K / GP I O3 0 SL P_ S3 # S U S B # [ 2 6 , 2 7, 3 1 ]
P W R _ B T N# E2 0 G1 0 SL P_ A#
[2 7 ] P W R_ B T N# P W R B TN # S L P _A #
A C_ PR E S ENT H 20 G1 6 SL P_ SU S#
[ 17 , 2 7 ] A C _P R E S E N T A C P R E S E N T / GP I O 3 1 S L P_ S US #
P M_ B A T L OW # E1 0 AP1 4
B A T L OW # / G P I O7 2 P MS Y N C H H _ P M_ S Y N C [3 ]
SW I# A1 0 K1 4 P M _ S LP _L A N #
[2 7 ] S W I# RI# S LP _L A N # / GP I O 2 9
C o u g a rP oi n t _ R e v _ 1 p 0
3 .3 V
U 1 5D
7 4 L V C0 8 PW
14
12
[ 3 6] D E L A Y _P W R G D 1 1 S Y S _ P W R _O K S Y S _ P W R OK
R 23 4 * 1 0m i l _0 4
13
[ 27 ] P M_ P C H _ P W R O K
3 .3 V 3 .3 V R2 5 3
3 .3 V
7
U 15 C
U 1 5B 7 4 L V C0 8 P W 1 0 K _0 4
U 15 A 7 4 L VC0 8 P W
14
7 4 LV C 0 8 P W
14
9
[ 35 ] 0 . 8 5 V S _ P W R GD
14
4 8
1 [ 3, 33 ] 1 . 8 V S _ P W R GD 6 10 A L L _S Y S _ P W R GD [ 1 1 , 27 , 3 6 ]
1 . 0 5 V S _ V T T_ E N
[ 3 3] DD R1 .5 V _ P W RG D 3 DD R_ 1 .0 5 V S _ P W RG D 5
2 R 54 5
[ 3 4] 1. 0 5 V S _ P W R GD
7
1 0 K _ 04
7
1 . 0 5 V S _ V T T _E N [3 4 ]
7
R 27 8 *1 0 K _ 0 4 P M_ M P W R O K
[ 9 , 1 0 , 3 3] V TT _ ME M
ON [ 1 3 , 2 0] RT CV C C
[ 1 3 , 1 4, 19 , 2 0 , 3 4] 1. 0 5 V S
[ 2 , 3 , 8, 11 , 1 3 , 1 4, 1 7 , 1 8 , 19 , 2 0 , 2 2, 2 3 , 2 6 , 28 , 3 0 , 3 1, 33 , 3 4 , 3 5] 3. 3 V
[ 3 , 9 , 10 , 1 1 , 1 2, 13 , 1 4 , 1 6, 1 7 , 1 8 , 19 , 2 0 , 2 3, 2 4 , 2 5 , 27 , 2 8 , 2 9, 30 , 3 1 , 3 6] 3. 3 V S
Schematic Diagrams
CougarPoint - M 4/9
CougarPoint -M
(LVDS,DDI,CRT)
U3 7 D
J47 AP 4 3
[ 1 1 ] B L ON M4 5 L _ B K LT E N S D V O _ T V CL K I NN AP 4 5
[ 1 1, 27 ] NB _ E NA V DD L _ V D D_ E N S D V O_ T V C L K I N P
P4 5 AM 4 2
L _ B K LT C T L S D V O_ S T A L L N AM 4 0
Ver:1.0 T40 SD VO _ ST AL L P
[ 1 1 ] P _D D C _ C L K K4 7 L _ D DC _ CL K AP 3 9
pull up 2.2K [1 1 ] P _ D DC _ D A T A L _ D D C _ D A TA S D V O _ INT N AP 4 0
L _ C T RL _ CL K T45 S D V O_ I N T P
3 .3 VS R1 6 3 1 0 K _ 04
R2 1 5 1 0 K _ 04 L _ C T RL _ DA T A P3 9 L _ C T RL _ CL K
L _ C T RL _ DA T A
R1 7 0 2 . 3 7K _ 1% _ 0 4 L V D S _ IB G AF3 7 P3 8
AF3 6 L V D _ IBG S D V O_ C T R L C L K M 39
L VD _ VBG S D V O _ C TR L D A T A
AE4 8
AE4 7 L VD _ VR EFH AT4 9
L VD _ VR EFL D D P B _A U X N
D D PB_ AU XP
AT4 7
AT4 0 Sheet 16 of 43
Display Port B
AK3 9 DD PB_ H PD
[ 1 1 ] LV D S - LC L K N L VD SA_ C L K#
CougarPoint - M 4/9
LVDS
AK4 0 AV 42
[ 1 1 ] L V D S -L C L K P
SDVO
L VD SA_ C L K DD PB_ 0 N AV 40
A N4 8 D DP B_ 0 P AV 45
[ 1 1 ] L V D S -L 0 N A M4 7 L VD SA_ D ATA# 0 DD PB_ 1 N AV 46
Digital Display Interface

[ 1 1 ] L V D S -L 1 N L VD SA_ D ATA# 1 D DP B_ 1 P
AK4 7 AU 48
[ 1 1 ] L V D S -L 2 N AJ 4 8 L VD SA_ D ATA# 2 DD PB_ 2 N AU 47
L VD SA_ D ATA# 3 D DP B_ 2 P AV 47
A N4 7 DD PB_ 3 N AV 49 R 271 2 . 2 K _0 4
[ 1 1 ] L V D S -L 0 P A M4 9 L VD SA_ D ATA0 D DP B_ 3 P 3 .3 VS
R 272 2 . 2 K _0 4
[ 1 1 ] L V D S -L 1 P AK4 9 L VD SA_ D ATA1
[ 1 1 ] L V D S -L 2 P AJ 4 7 L VD SA_ D ATA2 P4 6
L VD SA_ D ATA3 D DP C_ C T RL C L K H D M I _ C TR L C L K [ 1 2 ]
P4 2
D D P C _ C TR L D A T A H D M I _ C TR L D A T A [ 1 2 ]
AF4 0
[ 1 1 ] L V D S -U C L K N AF3 9 L VD SB_ C L K# AP 4 7
Display Port C
[ 1 1 ] L V D S -U C L K P L VD SB_ C L K D D P C _A U X N AP 4 9
A H4 5 D DP C _ A U X P AT3 8 P C H_ D DP C_ H P D R1 5 3 *1 0 m i l _0 4 P O RT C _ HP D [1 2 ]
[ 1 1 ] L V D S -U 0 N A H4 7 L VD SB_ D ATA# 0 D D P C_ H P D
[ 1 1 ] L V D S -U 1 N AF4 9 L VD SB_ D ATA# 1 AY 47 H DM IB_ D 2B N_ C C 140 0 . 1 u _1 0 V _ X 7 R _0 4
[ 1 1 ] L V D S -U 2 N AF4 5 L VD SB_ D ATA# 2 D D P C_ 0 N AY 49 H DM IB _ D 2 B N [1 2 ]
H DM IB_ D 2B P_ C C 141 0 . 1 u _1 0 V _ X 7 R _0 4
L VD SB_ D ATA# 3 DD PC _ 0 P AY 43 H DM IB_ D 1B N_ C H DM IB _ D 2 B P [1 2 ]
C 124 0 . 1 u _1 0 V _ X 7 R _0 4
A H4 3 D D P C_ 1 N AY 45 H DM IB_ D 1B P_ C H DM IB _ D 1 B N [1 2 ]
[ 1 1 ] L V D S -U 0 P C 125 0 . 1 u _1 0 V _ X 7 R _0 4 H DM IB _ D 1 B P [1 2 ]
A H4 9 L VD SB_ D ATA0 DD PC _ 1 P BA 47 H DM IB_ D 0B N_ C C 126 0 . 1 u _1 0 V _ X 7 R _0 4
[ 1 1 ] L V D S -U 1 P AF4 7 L VD SB_ D ATA1 D D P C_ 2 N BA 48 H DM IB _ D 0 B N [1 2 ]
H DM IB_ D 0B P_ C C 127 0 . 1 u _1 0 V _ X 7 R _0 4
[ 1 1 ] L V D S -U 2 P AF4 3 L VD SB_ D ATA2 DD PC _ 2 P BB 47 H DM IB_ C LK B N_ C H DM IB _ D 0 B P [1 2 ]
C 137 0 . 1 u _1 0 V _ X 7 R _0 4
L VD SB_ D ATA3 D D P C_ 3 N BB 49 H DM IB_ C LK BP_ C C 138 0 . 1 u _1 0 V _ X 7 R _0 4 H DM IB _ C L K BN [1 2 ]
DD PC _ 3 P H DM IB _ C L K B P [ 1 2]
DA C_ B L U E R2 0 0 1 5 0_ 1 % _ 0 4 DA C_ B L U E N4 8 M 43
[ 12 ] DAC _ B L U E C R T_ B L U E D DP D_ C T RL C L K
C 196 R1 8 7 1 5 0_ 1 % _ 0 4 DA C_ G RE E N P4 9 M 36
T49 C R T_ G R E E N D D P D _ C TR L D A T A
* 3 3p _ 5 0 V _ N P O_ 0 4 DA C_ G RE E N R1 9 2 1 5 0_ 1 % _ 0 4 DA C_ R E D
[ 12 ] D A C _ GR E E N C R T_ R E D
C 188
* 3 3p _ 5 0 V _ N P O_ 0 4 DA C_ R E D AT4 5
Display Port D
[ 12 ] DAC _ RE D
C 169
[ 1 2 ] D A C _D D C A C L K
T39
M4 0 C R T_ D D C _ C LK CRT D D P D _A U X N
D DP D _ A U X P
AT4 3
BH 4 1
* 3 3p _ 5 0 V _ N P O_ 0 4
EMI NEAR PCH [1 2 ] D A C _ DD CA DA T A
M4 7
C R T_ D D C _ D A T A D D P D_ H P D
D D P D_ 0 N
BB 4 3
BB 4 5
[ 12 ] DAC _ H S YN C M4 9 C R T_ H S Y N C DD PD _ 0 P BF 4 4
[ 12 ] DAC _ V SY N C C R T_ V S Y N C D D P D_ 1 N BE 4 4
DD PD _ 1 P BF 4 2
T43 D D P D_ 2 N BE 4 2
R1 6 5 1K _1 % _ 0 4 DA C_ IR E F
T42 D A C _ IRE F DD PD _ 2 P BJ 4 2
C R T_ I R T N D D P D_ 3 N BG 4 2
DD PD _ 3 P
C o u g a rP o ni t _ R e v _ 1 p 0
Connect to GND
[ 11 , 1 2 , 1 9 , 2 0 , 2 5 , 2 9, 30 , 3 1 , 3 6 , 3 7 ] 5 V S
[ 3 , 9 , 1 0 , 1 1 , 1 2, 13 , 1 4 , 1 5 , 1 7 , 1 8 , 1 9, 20 , 2 3 , 2 4 , 2 5 , 2 7 , 2 8, 29 , 3 0 , 3 1 , 3 6 ] 3 . 3 V S
Schematic Diagrams
CougarPoint - M 5/9
Boot BIOS Strap

BBS_BIT1 BBS_BIT0 Boot BIOS Location
0 0 LPC
CougarPoint -M (PCI,USB,NVRAM)
0 1 Reserved (NAND) U 37 E
AY 7 FOR LAYOUT SWAP
1 0 PCI R SVD 1 AV7
BG 2 6 R SVD 2 AU 3 R N5 3 .3 V S
1 1 SPI TP1 R SVD 3
BJ 2 6 BG 4 1 0K _8 P 4 R _ 04
BH 2 5 TP2 R SVD 4 I N T _ P I R QD # 4 5
BJ 1 6 TP3 AT1 0 D_ G P U_ P W R_ E N # 3 6
B B S _ B I T1 BG 1 6 TP4 R SVD 5 BC 8 S A T A _ OD D _D A # 2 7
R2 2 6 * 1 K _ 04
AH 3 8 TP5 R SVD 6 I N T _ P I R QG # 1 8
R4 4 6 * 1 K _ 04 AH 3 7 TP6 AU 2
B B S _ B I T0 [ 1 3 ] A K4 3 TP7 R SVD 7 AT4 R N4
A K4 5 TP8 R SVD 8 AT3 1 0K _8 P 4 R _ 04
C 18 TP9 R SVD 9 AT1 IN T _ P IRQ A# 4 5
N 30 TP1 0 R SVD 1 0 AY 3 D GP U _ H OL D _ R S T # 3 6
H 3 TP1 1 R SVD 1 1 AT5 D GP U _ S E L E C T # 2 7
AH 1 2 TP1 2 R SVD 1 2 AV3 1 8

IN T _ P IRQ E#
AM 4 TP1 3 R SVD 1 3 AV1
Flash Descriptor security override strap AM 5 TP1 4
TP1 5
R SVD 1 4
R SVD 1 5
BB1
Y 13 BA3 I N T _ P I R QB # 10 K _ 0 4 R2 2 8
K2 4 TP1 6 R SVD 1 6 BB5 I N T _P I R Q C # 10 K _ 0 4 R2 6 5
LOW = PCI_GNT#3 swap override L24 TP1 7 R SVD 1 7 BB3 I N T _P I R Q H # 10 K _ 0 4 R2 5 1
PCI_GNT#3 A B4 6 TP1 8 R SVD 1 8 BB7 D G P U _P W M_ S E LE C T # *1 0 K _ 0 4 R2 4 1
HIGH = Default A B4 5 TP1 9 R SVD 1 9 BE8
Sheet 17 of 43 TP2 0 R SVD 2 0 BD 4
RSVD
R SVD 2 1 BF6
R2 2 5 * 1K _0 4 P C I _ GN T #3 R SVD 2 2
CougarPoint - M 5/9 B2 1
M 20
AY 1 6
TP2 1
TP2 2
R SVD 2 3
R SVD 2 4
AV5
AV1 0
BG 4 6 TP2 3 AT8
TP2 4 R SVD 2 5
AY 5
R SVD 2 6 BA2
B E2 8 R SVD 2 7
BC 3 0 TP2 5 AT1 2
IN T _ P IRQ E # B E3 2 TP2 6 R SVD 2 8 BF3
R 2 43 *1 K _ 0 4
BJ 3 2 TP2 7 R SVD 2 9
BC 2 8 TP2 8
B E3 0 TP2 9
B F32 TP3 0
BG 3 2 TP3 1 C2 4
MPC Switch Control A V2 6 TP3 2 U SBP0 N A2 4 US B _ PN0 [2 6 ]
MPC ON -- 0 B B2 6 TP3 3 U SBP0 P C2 5 US
US
B_ PP0
B _ PN1
[2 6 ]
[3 0 ]
USB PORT0 (J_USB_1)
AU 2 8 TP3 4 U SBP1 N B2 5
MPC OFF -- 1 DEFAULT AY 3 0 TP3 5 U SBP1 P C2 6 US
US
B_ PP1
B _ PN2
[3 0 ]
[2 2 ]
USB PORT1 (J_USB3_1; USB3.0)
AU 2 6 TP3 6 U SBP2 N A2 6
AY 2 6 TP3 7 U SBP2 P K2 8 US B_ PP2 [2 2 ] WLAN
A V2 8 TP3 8 U SBP3 N H2 8
A W30 TP3 9 U SBP3 P E2 8 10/29 NEW CARD
TP4 0 U SBP4 N D2 8 US B _ PN4 [2 3 ]
U SBP4 P C2 8 US
US
B_ PP4
B _ PN5
[2 3 ]
[2 3 ]
3G
U SBP5 N A2 8
3 .3 V U SBP5 P C2 9 US B_ PP5 [2 3 ] CCD
PI N P LT_R ST# to B uff er U SBP6 N B2 9
C2 0 7 * 0 . 1u _ 1 6 V _ Y 5 V _ 0 4 I N T _P I R Q A # K4 0 U SBP6 P N2 8
I N T _P I R Q B # K3 8 P IR QA # U SBP7 N M2 8
P IR QB # U SBP7 P
5
PCI
U1 3 I N T _P I R Q C # H 38 L 30
P L T _R S T # 1 74 A H C 1 G 0 8G W I N T _P I R Q D # G 38 P IR QC # U SBP8 N K3 0
4 P IR QD # U SBP8 P G3 0
B U F _ P L T _ R S T # [ 2 2 , 2 4 , 26 , 2 7 ] U SBP9 N US B _ P N9 [3 0 ]
2 D GP U _ H O L D _ R S T # C 4 6 E3 0
C 44 R E Q1 # / G P I O5 0 U SBP9 P C3 0 US B _ P P 9 [3 0 ] USB PORT2 (AJ_USB1)
USB
D GP U _ S E L E C T#
D _G P U _ P W R _E N # E4 0 R E Q2 # / G P I O5 2 U SBP1 0 N A3 0
R2 4 5
R E Q3 # / G P I O5 4 U S B P 10 P L 32
3
D 47 U SBP1 1 N K3 2 U S B _P N 1 1 [ 2 8 ]
1 00 K _ 0 4 B B S _B I T 1
D G P U _ P W M_ S E L E C T # E 4 2 GN T 1 # / GP I O 5 1 U S B P 11 P G3 2 U S B _ P P 1 1 [2 8 ] BT PORT11
P C I _ GN T #3 F46 GN T 2 # / GP I O 5 3 U SBP1 2 N E3 2
GN T 3 # / GP I O 5 5 U S B P 12 P C3 2
U SBP1 3 N A3 2
I N T _P I R Q E # G 42 U S B P 13 P
S A T A _ O DD _ DA # G 40 P I R QE # / G P I O 2 3 .3 V
R N6
[ 2 5 ] S A TA _O D D _ D A # I N T _P I R Q G# C 42 P I R QF # / G P I O 3 C3 3 U S B _ B IA S R 4 67 2 2 . 6 _1 % _ 0 4 1 0K _8 P 4 R _ 04
I N T _P I R Q H # D 44 P I R QG # / GP I O4 US BR B IA S # U SB_ O C# 4 5 5 4
P I R QH # / GP I O5 U SB_ O C # 1 0 11 6 3
B3 3 U SB_ O C# 6 7 7 2
K1 0 U SB R B IA S U SB_ O C # 1 2 13 8 1
[ 27 ] P ME # PM E#
P L T _ RST # C 6 A1 4 U S B _ OC #01 R N7
[ 3 , 2 3 ] P L T _ R S T# P L T RS T # O C 0# / G P IO 5 9 K2 0 U S B _ O C# 0 1 [3 0 ]
U S B _ OC #23 1 0K _8 P 4 R _ 04
O C 1# / G P IO 4 0 B1 7 U S B _ OC #45 U SB_ O C# 0 1 5 4
H 49 O C 2# / G P IO 4 1 C1 6 10/29 6 3
U S B _ OC #67 U SB_ O C# 1 4
P C L K _ TP M_ P C H H 43 CL KO UT _ P C I0 O C 3# / G P IO 4 2 L 16 U S B _ OC #89 U SB_ O C# 2 3 7 2
R2 1 4 *2 2 _ 0 4
[ 2 3] PCL K_ T P M R2 2 7 2 2 _0 4 C LK _P C I _ F B _ R J48 CL KO UT _ P C I1 O C 4# / G P IO 4 3 A1 6 U S B _ OC # 1 01 1 U SB_ O C# 8 9 8 1
[ 1 4] CL K _ P C I_ F B K4 2 CL KO UT _ P C I2 O C5 # / G P IO 9 D1 4 U S B _ OC # 1 21 3
C LK _P C I _ K B C _ R H 40 CL KO UT _ P C I3 O C 6# / G P IO 1 0 C1 4 U S B _ OC #14
R2 6 0 2 2 _0 4
[ 2 7 ] P C LK _K B C CL KO UT _ P C I4 O C 7# / G P IO 1 4
R2 3 3 * 0 _0 4
A C _ P R E S E N T [ 1 5 , 27 ]
C ou g a rP o i nt _R e v _ 1 p0
[ 2 , 3 , 8 , 1 1, 13 , 1 4 , 1 5 , 1 8, 1 9 , 2 0 , 2 2 , 23 , 2 6 , 2 8 , 3 0, 31 , 3 3 , 3 4 , 3 5] 3. 3V
[ 3, 9, 1 0 , 1 1 , 1 2 , 13 , 1 4 , 1 5 , 1 6, 18 , 1 9 , 2 0 , 2 3, 2 4 , 2 5 , 2 7 , 28 , 2 9 , 3 0 , 3 1, 36 ] 3 . 3 V S
Schematic Diagrams
CougarPoint - M 6/9
R1 8 0 1 0K _0 4 B IO S _ RE C
3 .3V S
R1 8 4 *0 _ 0 4
CougarPoint - M (GPIO,VSS_NCTF,RSVD)
BIOS RECOVERY
U 3 7F
DISABLE----R349 NO STUFF (DEFAULT)
ENABLE-----R349 STUFF S _G P IO T7 C4 0 S A TA _O D D _ P W R GT
B M B U S Y # / GP I O0 T A C H 4 / GP I O 6 8 S A T A _ OD D _ P W R GT [2 5 ]
S MI# A4 2 B4 1 P C H _ G P IO 57 R4 6 9 1 . 5K _1 % _ 0 4
[2 7 ] S M I # T A C H 1 / GP IO1 T A C H 5 / GP I O 6 9
D GP U _ H P D _ IN T R # H3 6 C4 1 G P I O 70 R4 7 4 1 . 5K _1 % _ 0 4
GF X _ C R B _ D E T T A C H 2 / GP IO6 T A C H 6 / GP I O 7 0 3 .3 VS
3 .3V S R4 5 1 *1 0 K _ 04
S C I# E3 8 A4 0 G P I O 71 R4 7 1 1 . 5K _1 % _ 0 4
[2 7 ] S C I # T A C H 3 / GP IO7 T A C H 7 / GP I O 7 1 3 .3 VS
R4 5 0 10 0 K _ 0 4 IC C_ E N # C1 0
G P I O8
10/28 G P IO 12 C4
L A N _ P H Y _ P W R _ C T R L / GP I O 1 2
R3 1 4 *0 _ 04 H OS T_ A L E R T #1 G2 P4
[ 27 ] O C P P E # G P I O1 5 A 2 0 GA TE R1 3 7 * 1 0K _ 0 4 GA 2 0 [2 7 ]
A U1 6 1 .0 5 VS_ VT T
Internal GFX: Low (Default) H P E C I_R R1 3 8 *0 _ 0 4
S A TA _D E T # 4 U2 P E CI H _ P E C I [3 , 2 7]
S A T A 4 G P / GP IO1 6 P5 K B C _ R S T#
External GFX: High
R CIN # K B C _ R S T # [ 27 ]
GPIO
D GP U _ P W R OK D4 0 AY1 1
T A C H 0 / GP IO1 7 P R OC P W R G D H _ C P U P W R GD [ 3 ]
CPU/MISC
3 .3V
B IOS _ R E C
H OS T_ A L E R T #2
T5
E8
S C LO C K / GP I O2 2 T H R MT R I P #
AY1 0
T 14
H T H R MT R I P #_ R
IN IT 3 _3 V #
R1 2 5 3 90 _ 1 % _0 6
R4 3 0
H _ T H R MT R I P # [3]
2 . 2K _0 4
Sheet 18 of 43
1 .8 VS
R4 8 4 *1 0 K _ 0 4
[ 1 1] S B _ B L ON
E1 6
G P I O2 4 / M E M_ L E D
G P I O2 7
I N IT 3 _ 3 V #
D F _T V S
AY1 N V _ CL E R4 2 9 1 K_ 0 4
H _ S N B _ IV B # [ 3 ]
CougarPoint - M 6/9
P8
10/28
R4 6 5 1 K _ 04 IC C _ E N # P LL _ OD V R _E N
G P I O2 8 A H 8 R 54 7 *1 0 mi l _ 04 DMI & FDI Termination Voltage
G P IO 34 K1 TS _ V S S 1
S T P _ P C I# / GP IO 3 4 A K 1 1 R 54 8 *1 0 mi l _ 04 Set to Vss when LOW
P C H _M U T E # K4 TS _ V S S 2 NV_CLE
G P I O3 5 A H 1 0 R 54 9 *1 0 mi l _ 04
Set to Vcc when HIGH
S A TA _O D D _ P R S N T # V8 TS _ V S S 3
[2 5 ] S A T A _ OD D _ P R S N T # S A T A 2 G P / GP IO3 6
INTEGRATE CLOCK A K 1 0 R 55 0 *1 0 mi l _ 04
F D I_ OV R V L T G M5 TS _ V S S 4
DISABLE----R465 NO STUFF (DEFAULT) S A T A 3 G P / GP IO3 7
ENABLE-----R465 STUFF R4 4 9 10 K _ 0 4 M F G _M OD E N2 P3 7
3 .3 V S S L OA D / G P IO 38 NC _ 1
G F X _ CR B _ DE T M3
S D A T A OU T 0 / GP IO 3 9
R1 8 1 10 K _ 0 4 T E S T _ S E T _ UP V1 3 B G2
3 .3 V S S D A T A OU T 1 / GP IO 4 8 V S S _ N CT F _ 1 5
R4 3 5 *0 _ 04 C R IT _ T E M P _R E P # _ R V3 B G4 8
3.3 V [ 2 ] C R I T _ T E MP _ R E P # S A T A 5 G P / GP IO4 9 V S S _ N CT F _ 1 6
R2 2 2 10 0 K _ 0 4 T E S T _ DE T D6 B H3
G P I O5 7 V S S _ N CT F _ 1 7
B H4 7
H OS T _ A L E R T# 1 V S S _ N CT F _ 1 8
R 46 2 1 K_ 0 4
R 25 4 1 K_ 0 4 H OS T _ A L E R T# 2 A4 BJ 4
G P IO 12 V S S _ N CT F _ 1 V S S _ N CT F _ 1 9
R 46 1 * 10 K _ 0 4
10/28 A4 4 BJ 4 4
V S S _ N CT F _ 2 V S S _ N CT F _ 2 0
3 .3 V S R N8 A4 5 BJ 4 5
1 0 K _ 8 P 4R _ 0 4 V S S _ N CT F _ 3 V S S _ N CT F _ 2 1
NCTF
1 8 S C I# A4 6 BJ 4 6
2 7 S M I# V S S _ N CT F _ 4 V S S _ N CT F _ 2 2
3 6 G A2 0 A5 BJ 5
4 5 K B C _ R S T# V S S _ N CT F _ 5 V S S _ N CT F _ 2 3
A6 BJ 6
V S S _ N CT F _ 6 V S S _ N CT F _ 2 4
R 17 9 1 0 K _ 04 S _ GP IO B3 C2
S A T A _ OD D _ P R S N T # V S S _ N CT F _ 7 V S S _ N CT F _ 2 5
R 16 6 2 0 0K _0 4
R 26 4 1 0 K _ 04 D G P U _ H P D _ IN T R # B4 7 C4 8
R 47 0 1 K_ 0 4 S A T A _ OD D _ P W R GT V S S _ N CT F _ 8 V S S _ N CT F _ 2 6
R 45 5 * 1K _ 0 4 GP IO 3 4 BD 1 D1
R 43 6 1 0 K _ 04 C R I T _T E M P _ R E P #_ R V S S _ N CT F _ 9 V S S _ N CT F _ 2 7
R 48 0 * 10 K _ 0 4 DG P U_ P W RO K B D4 9 D4 9
R 44 2 1 0 K _ 04 S A T A _ DE T # 4 V S S _ N CT F _ 1 0 V S S _ N CT F _ 2 8
BE1 E1
V S S _ N CT F _ 1 1 V S S _ N CT F _ 2 9
R 19 4 * 1K _ 0 4 P L L _ OD V R _ E N BE4 9 E4 9
V S S _ N CT F _ 1 2 V S S _ N CT F _ 3 0
R 20 1 1 0 0K _0 4 F D I_ OV R V L T G BF1 F1
V S S _ N CT F _ 1 3 V S S _ N CT F _ 3 1
BF4 9 F49
V S S _ N CT F _ 1 4 V S S _ N CT F _ 3 2
C o ug a rP o i nt_ R e v _1 p 0
[ 2, 3,5 , 1 9 ,2 0 , 34 ,3 6 ] 1 .0 5 V S _ V T T
[ 6 , 1 9, 3 3 ] 1 . 8 V S
[2 , 3 ,8 ,11 ,1 3 , 1 4, 15 ,1 7 , 1 9, 20 ,2 2 ,2 3,2 6 , 2 8 ,3 0,3 1 , 3 3 , 3 4, 3 5 ] 3 . 3 V
[ 3 ,9 , 10 , 1 1 ,1 2 , 13 ,1 4 , 1 5, 16 ,1 7 , 1 9, 20 ,2 3 ,2 4,2 5 , 2 7 ,2 8,2 9 , 3 0 , 3 1, 3 6 ] 3 . 3 V S
Schematic Diagrams
CougarPoint - M 7/9
CougarPoint -M (POWER) L17
HC B 1 00 5 K F -1 2 1 T2 0
3 . 3V S
5 VS
1 .0 5 VS U3 7 G POWER V C CA _ D A C_ 3 . 3 V S
All VCCORE = 1.3A 1mA U 39
5 1
AA2 3 U4 8 OU T IN
C1 6 8 C 1 58 C1 7 8 C1 7 4 AC 2 3 V CC CO R E [1 ] V C CA D A C C 4 51 C4 5 2 C4 5 3 C5 3 9 C 45 7 C4 5 9
AD 2 1 V CC CO R E [2 ] R 45 7 3
V CC CO R E [3 ] S H DN #
CRT
1 0u _ 6 . 3 V _ X5 R _0 6 1 u_ 6 .3 V _ Y 5 V _ 0 4 1 u _ 6. 3V _ Y 5 V _0 4 1 u _6 . 3 V _ Y 5 V _ 0 4 AD 2 3 U4 7 0 .0 1 u_ 1 6 V _ X7 R _ 04 0 .1 u_ 1 0 V _ X5 R _0 4 1 0u _ 6 .3 V _ X5 R _0 6 *0 .1 u _ 10 V _ X 5 R_ 0 4 *2 2 u _ 6.3 V _ X 5 R _ 0 8 * 23 . 7 K _ 1 %_ 0 4 * 1 u_ 6 . 3 V _ X5 R _0 4
AF2 1 V CC CO R E [4 ] VSSAD AC 4 2
V CC CORE
AF2 3 V CC CO R E [5 ] SET G ND
AG 2 1 V CC CO R E [6 ] 3 .3 V S _ V C CA _ L V D * A P L 5 6 03 -3 3 B
AG 2 3 V CC CO R E [7 ]
AG 2 4 V CC CO R E [8 ] AK3 6
1mA R 1 59 * 20 m i l_ 0 4
AG 2 6 V CC CO R E [9 ] V CC A L V D S 3. 3 V S
R 46 0
AG 2 7 V CC CO R E [1 0 ] AK3 7 C1 5 6
AG 2 9 V CC CO R E [1 1 ] V SS AL VDS * 10 K _ 1 % _0 4
AJ 2 3 V CC CO R E [1 2 ] 1 .8 V S _ V C C T X_ L V D
0 . 1u _ 1 0 V _X 5 R _0 4 L 34 APL5603-33B 6-02-56033-4C0
AJ 2 6 V CC CO R E [1 3 ] A M3 7 HC B 1 60 8 K F -1 2 1 T2 5
LVDS
V CC CO R E [1 4 ] V CC T X_ L V DS [1] 60mA G9091-330T11UF 6-02-90913-4C0
1. 0 5 V S 1 . 0 5V S _V CC A P L L_ E X P AJ 2 7 . 1 . 8V S
AJ 2 9 V CC CO R E [1 5 ] A M3 8
AJ 3 1 V CC CO R E [1 6 ] V CC T X_ L V DS [2] C 1 53 C1 5 0 C4 3 9
R1 5 2 *2 0 m li _ 0 4 V CC CO R E [1 7 ] AP3 6
V CC T X_ L V DS [3] 0 .0 1 u_ 1 6 V _ X7 R _ 04 0 .0 1u _ 1 6V _X 7 R _ 0 4 2 2u _ 6 .3 V _ X5 R _0 8
Sheet 19 of 43 1 .05 V S _ V C CA P LL _ E X P AN 1 9
V CC I O[ 2 8 ]
V CC T X_ L V DS [4]
AP3 7
L3 1
CougarPoint - M 7/9 *HC B 1 0 05 K F -12 1 T 20
. V C C A _P L L _ E X P BJ 2 2
V CC A P L L E X P 266mA
3. 3V S
V3 3
AN 1 6 V C C3 _ 3 [ 6]
C 4 24 C1 7 9
HV CMOS
V CC I O[ 1 5 ]
* 1 0u _ 6 . 3V _X 5 R_ 0 6 AN 1 7 0 .1 u_ 1 0 V _ X5 R _0 4
V CC I O[ 1 6 ] V3 4
V C C3 _ 3 [ 7]
AN 2 1
1 .0 5 V S V CC I O[ 1 7 ] 1. 5V S _1 . 8 V S
AN 2 6
All VCCIO = 2.92A V CC I O[ 1 8 ]
AN 2 7 AT1 6
160mA
C 14 7 C 1 71 C 1 49 C 1 51 C 1 52 V CC I O[ 1 9 ] V CC V RM [3]
AP2 1
1 0 u _6 . 3 V _ X 5R _ 06 1 u _ 6.3 V _ Y 5V _0 4 1 u _ 6. 3V _ Y 5V _0 4 1 u _ 6. 3V _ Y 5 V _0 4 1 u _ 6 . 3V _Y 5 V _ 04 V CC I O[ 2 0 ]
AP2 3 AT2 0
42mA
V CC I O[ 2 1 ] V CC DM I [ 1] 1 .0 5 V S_ VT T
AP2 4 C 14 6 C1 2 8
DM I
V CC I O[ 2 2 ] 2mA
VCC I O
AP2 6 AB3 6 V C CC L K DM I R1 6 4 * 2 0m i l _0 4 1u _ 6 .3 V _Y 5 V _ 04 10 u _ 6 .3V _ X 5 R_ 0 6
V CC I O[ 2 3 ] V C CC LK D MI 1 . 05 V S
AT2 4
V CC I O[ 2 4 ]
AN 3 3
V CC I O[ 2 5 ]
3 .3 V S AN 3 4 A G1 6
V CC I O[ 2 6 ] V C CD F T E RM [1] V _ N V RA M _ V CC Q 1 .8 V S 3 .3 VS
190mA
266mA Z2501 BH 2 9 A G1 7
CougarPoint power supply range
R1 4 0 * 20 m i _l 0 4
V CC 3 _3 [ 3 ] V C CD F T E RM [2]
DF T / S PI
C 14 4 1 .5 V S _ 1 . 8V S R 1 41 * 0_ 0 4 Min Voltage Max
AJ 1 6 C1 6 0
0 .1 u _1 0 V _ X 5R _ 0 4 V C CD F T E RM [3]
160mA AP1 6 0 . 1u _ 1 0 V _X 5 R _0 4
1.00V 1.05V 1.10V
1 . 0 5V S _V CC A P L L_ F D I V CC V R M [2 ] AJ 1 7
V C CD F T E RM [4] 1.43V 1.5V 1.58V
R 42 1 *0 _ 0 4 BG 6 V CC ME 3 .3 V 3 .3 V S 3. 3V 1.71V 1.8V 1.89V
1.0 5 V S V c cA F DI P L L
11/ 01 R 43 9 *0 _ 0 4 3.14V 3.3V 3.47V

AP1 7
V CC I O[ 2 7 ] V1
20mA
R 44 0 0 _ 04 4.75V 5V 5.25V
F DI
V C CSPI
1. 0 5 S _ V CC _ DM I AU 2 0 C4 4 6
V CC DM I [ 2 ] 11/03
42mA
R 1 49 * 20 m i l _0 4 1 u _6 . 3 V _ Y 5 V _ 0 4
1 .0 5 V S _ V TT Co u g ar P oi n t _ Re v _ 1 p 0
[2 0] 1. 5V S _1 . 8 V S
[1 1, 1 2 , 2 0 , 2 5, 2 9 , 3 0 , 31 ,3 6 ,3 7] 5V S
1. 0 5 V S 1 .5 V S 1 .8V S 1.5 V S _1 . 8 V S [2 ,3 , 8,1 1 ,1 3 ,14 , 1 5 , 1 7 , 18 ,2 0 ,2 2, 2 3 , 2 6 , 2 8, 3 0 , 3 1 , 33 ,3 4 ,3 5] 3. 3V
[ 3 ,9, 10 , 1 1 , 1 2,1 3 ,1 4 ,15 , 1 6 , 1 7 , 18 ,2 0 ,2 3, 2 4 , 2 5 , 2 7, 2 8 , 2 9 , 30 ,3 1 ,3 6] 3. 3V S
[6 ,1 8 ,3 3] 1. 8V S
[2 9 ,3 1] 1. 5V S
R 14 3 *0 _ 0 4
[ 2 , 3 , 5 , 1 8 , 20 ,3 4 ,3 6] 1. 05 V S _ V T T
[ 1 3 , 1 4 , 15 ,2 0 ,3 4] 1. 05 V S
R 14 8 *2 0 m li _ 0 4
R 14 7 *0 _ 0 4
Schematic Diagrams
CougarPoint - M 8/9
CougarPoint power supply range CougarPoint - M (POWER) Vo lt age R ai l Vol ta ge S0 I cc ma x Cur re nt ( A)

L 36 1 . 0 5V S _V C C A _C LK V_ CP U_I O 1. 05 1 (m A)
Min Voltage Max * H C B 1 00 5 K F -1 2 1T 2 0 V5 RE F 5 1 (m A)
1 . 05 V S
1.00V 1.05V 1.10V V5 RE F_S us 5 1 (m A)
3 . 3V
U3 7 J PO WE R Vc c3 _3 3. 3 0. 26 6
1.43V 1.5V 1.58V C1 9 4 AD 4 9 N 26 All VCCIO=2.92A Vc cA DAC 3 1. 05 1 (m A)
V CC A CL K V C C I O[ 29 ] 1 .0 5 V S
1.71V 1.8V 1.89V 0 . 1u _ 1 0V _X 5 R _ 0 4 P2 6 C 19 2 Vc cA DPL LA 1. 05 0. 08
3mA T16 V C C I O[ 30 ]
3.14V 3.3V 3.47V V CC DS W 3 _ 3 P2 8 Vc cA DPL LB 1. 05 0. 08
1 u _ 6. 3 V _ Y 5 V _ 0 4
V C C I O[ 31 ]
4.75V 5V 5.25V Vc cC ore 1. 05 1. 3
C 1 90 *0 . 1 u _1 0 V _ X5 R _0 4 P C H_ V CC DS W V1 2 T27
DC P S US B Y P V C C I O[ 32 ] Vc cD MI 1. 1 0. 04 2
L 16
H C B 1 0 0 5K F -12 1 T 20 T29
2 66 mA V C C I O[ 33 ] Vc cI O 1. 05 2. 92 5
V C C3 _ 3 T38 3 .3 V
3. 3 V S V C C 3_ 3 [ 5 ]
97mA Vc cA SW 1. 05 1. 01
C1 7 6 C 1 87 T23
11/01 V C C S U S 3 _3 [ 7 ] Vc cS PI 3. 3 0. 02 0
BH 2 3
V C C A P L LD MI 2 T24
1 0u _ 6 . 3V _X 5 R _ 0 6 1 u _ 6. 3 V _ Y 5 V _ 0 4 C 18 4 C1 9 7 Vc cD SW3 _3 3. 3 2 (m A)
L 30 AL 2 9 V C C S U S 3 _3 [ 8 ]
V C C I O[ 1 4 ] V2 3 Vc cD FTE RM 1. 8 0. 19
* H C B 1 00 5 K F -1 2 1T 2 0 0 . 1 u _1 0 V _ X5 R _0 4 0 . 1u _ 1 0V _ X 5 R _ 0 4
+ V C C A P L L _C P Y _ P C H V C C S U S 3 _3 [ 9 ]
Vc cS us3 _3 3. 3 0. 09 7
US B
1 . 05 V S AL 2 4 V2 4
C 1 61 *1 u _ 6. 3 V _ X 5R _ 04 DCP S US DC P S US [3 ] V C C S U S 3 _ 3[ 10 ] Vc cS usH DA 3. 3 1 (m A)
1 1/01
1 .0 5 VS P2 4
V C C S U S 3 _3 [ 6 ] Vc cV RM 1. 5 0. 16
A ll V CC ASW =1 .0 1A D 10 R B 7 5 1 S -40 C 2
AA1 9 C A Vc cC lKD MI 1. 05 0. 02
C 4 41 C4 3 8 C 2 00 C1 7 3 C 1 83
AA2 1
V CC A S W [1 ]
V CC A S W [2 ]
V C C I O[ 34 ]
T26 R1 9 6 * 20 m i _l 0 4
1 .0 5 V S
1mA
R2 4 2 1 0 _0 4
3 . 3V
5V
Vc cS SC
Vc cD IFF CL KN
1. 05
1. 05
0. 09 5
0. 05 5
Sheet 20 of 43
AA2 4 M 26 + V 5 A _P C H _ V C C 5 R E F S U S
2 2 u _6 . 3 V _ X 5R _ 08 2 2u _ 6 . 3V _X 5 R _ 0 8 1 u _ 6. 3 V _ Y 5V _ 0 4 1 u_ 6 . 3 V _ Y 5 V _ 04 1 u _ 6. 3 V _ Y 5 V _ 0 4 V CC A S W [3 ] V 5 R E F _S U S
C2 0 3 0 . 1 u _1 0 V _ X5 R _0 4
Vc cA LVD S 3. 3 1 (m A)
CougarPoint - M 8/9
Clock and Miscellaneous

AA2 6
V CC A S W [4 ] Vc cT X_L VD S 1. 8 0. 06
A N 2 3 + V C C A _ U S B S U S C 15 4 *1 u _6 . 3 V _ X 5R _ 04
AA2 7 DCP S US [4 ]
V CC A S W [5 ] AN 2 4
AA2 9 V C C S U S 3 _3 [ 1 ] 3 .3 V
V CC A S W [6 ]
AA3 1 + 5 V _P C H _ V C C 5 R E F S U S
V CC A S W [7 ] D 11 R B 7 5 1 S -40 C 2
AC 2 6 P3 4
1mA C A
Note: C1289- STUFFED ONLY FOR CPT INTERPOSER; V CC A S W [8 ] V 5R E F 3 . 3V S
UNSTUFF FOR CPT AC 2 7 R2 6 3 1 0 _0 4
V CC A S W [9 ] N 20 5 VS
AC 2 9 V C C S U S 3 _3 [ 2 ]
97mA C2 0 2 1u _ 6 . 3 V _X 5 R _ 0 4
PC I/ GP IO /L PC
V CC A S W [1 0 ] N 22 3 .3 V
AC 3 1 V C C S U S 3 _3 [ 3 ]
V CC A S W [1 1 ] 11/03
P2 0
AD 2 9 V C C S U S 3 _3 [ 4 ]
V CC A S W [1 2 ] P2 2 3. 3 V S C 18 6
AD 3 1 V C C S U S 3 _3 [ 5 ]
V CC A S W [1 3 ] 1 u _6 . 3 V _ Y 5 V _ 0 4
W21 AA1 6
266mA
V CC A S W [1 4 ] V C C 3 _3 [ 1 ]
W23 W16
V CC A S W [1 5 ] V C C 3 _3 [ 8 ]
W24 T34 C 1 81 C1 9 3 C 1 80
V CC A S W [1 6 ] V C C 3 _3 [ 4 ]
0 . 1 u _1 0 V _ X 5R _0 4 0 . 1u _ 1 0V _ X 5 R _ 0 4 0 . 1 u _1 0 V _ X5 R _0 4
W26
V CC A S W [1 7 ]
W29
V CC A S W [1 8 ]
C2 0 1 0 . 1 u _1 0 V _ X 5R _0 4 W31 AJ 2
V CC A S W [1 9 ] V C C 3 _3 [ 2 ] + V 1 . 0 5S _S A T A 3 L1 5
W33 H C B 16 0 8 K F -1 21 T 2 5
V CC A S W [2 0 ] All VCCIO=2.92A
1 . 0 5 V S L3 2 1 . 0 5V S _V C C A _A _ D P L
1. 5 V S _ 1 . 8 V S V C C I O[ 5 ]
AF1 3 . 1 .0 5 V S
H C B 1 0 0 5K F -12 1 T 20
+V C C R T C E X T N 16 C 16 6 C1 5 9
DC P RT C AH 1 3
+C 4 36 C 4 23 C4 2 7 V C C I O[ 12 ] 1 u _ 6. 3 V _ Y 5 V _ 0 4 *1 0 u_ 6 . 3 V _ X5 R _ 0 6
16mA Y 49 AH 1 4
R 4 24
* 2 20 u _ 6. 3 V _ 6 . 3 *4 . 2 2 2 u _6 . 3 V _ X 5R _ 08 1 u_ 6 . 3 V _ Y 5 V _ 04 V C C V R M [ 4] V C C I O[ 13 ]
* 0 _0 4
80mA AF1 4 L 33
1. 1 V S _ V C C A _ B _ D P L BD 4 7 V C C I O[ 6 ]
L3 5 *H C B 1 0 05 K F -1 2 1 T2 0
H C B 1 0 0 5K F -12 1 T 20 V CC A DP L L A AK1 1 . 0 5 V S _ V C C A P L L_ S A T A 3
80mA
SA TA
BF4 7 V C C A P LL S A T A 1 . 05 V S
V CC A DP L L B 3 . 3 A _ 1. 5 A _ H D A _ I O
1. 05 V S AF1 1 3. 3V 1. 5V
C 4 49 C 4 22 C4 2 6 55mA
C 1 64 C 1 63 AF1 7 V C C V R M[ 1 ] 1 . 5 V S _ 1 . 8V S
AF3 3 V C C I O[ 7 ]
* 2 2u _ 6 . 3V _X 5 R _ 0 8 2 2 u _6 . 3 V _ X 5R _ 08 1 u_ 6 . 3 V _ Y 5 V _ 04 R 25 8 *0 _ 06
1 u _ 6. 3 V _ Y 5V _ 0 4 1 u _ 6. 3 V _ Y 5 V _ 0 4 A F 3 4 V CC DIF F C L K N[1 ] AC 1 6
AG 3 4 V CC DIF F C L K N[2 ] V C C I O[ 2 ] 1 . 05 V S
R 25 9 0_ 0 6
V CC DIF F C L K N[3 ] AC 1 7
11/03 V C C I O[ 3 ]
C 16 7
AG 3 3 AD 1 7
1 .0 5 V S V CC S S C V C C I O[ 4 ]
1 u _ 6. 3 V _ Y 5 V _ 0 4
C1 5 5 V C CS S T V1 6
C1 9 1 0 . 1 u _1 0 V _ X 5R _0 4 DC P S S T [ 13 ] 3 . 3 A _ 1. 5 A _ H D A _ I O
1 u_ 6 . 3 V _ Y 5V _0 4
[ 19 ] 1 . 5 V S _ 1 . 8V S
+ V 1 . 05 M _V C C S U S 1. 01 A
C1 8 2 * 1 u_ 6 . 3 V _X 5 R _ 0 4 T17 T21 [ 1 3 , 15 ] R T C V C C
V1 9 DC P S US [1 ] V C C A S W [ 22 ] 1 .0 5 VS [ 2 3 , 2 6, 30 , 3 1 , 33 , 3 4 , 35 ] 5 V
DC P S US [2 ] [ 1 1 , 1 2, 1 9 , 2 5, 29 , 3 0 , 31 , 3 6 , 37 ] 5 V S
MI SC
V2 1 [ 2 , 3 , 8, 11 , 1 3 , 14 , 1 5 , 17 , 1 8 , 1 9, 2 2 , 2 3, 2 6 , 2 8, 30 , 3 1 , 33 , 3 4 , 35 ] 3 . 3 V
1 . 0 5 V S _ V TT V C C A S W [ 23 ] [ 3 , 9 , 1 0, 1 1 , 1 2, 13 , 1 4 , 15 , 1 6 , 17 , 1 8 , 1 9, 2 3 , 2 4, 2 5 , 2 7, 28 , 2 9 , 30 , 3 1 , 36 ] 3 . 3 V S
1mA BJ 8 [ 3 , 6 , 8 , 9, 10 , 2 6 , 28 , 3 1 , 33 ] 1 . 5 V
CP U
C 4 03 C4 1 2 C4 1 3
V _P R OC _ I O T19 [ 13 , 1 4 , 15 , 1 9 , 34 ] 1 . 0 5 V S
V C C A S W [ 21 ] [ 2, 3 , 5 , 1 8 , 19 , 3 4 , 36 ] 1 . 0 5 V S _ V TT
4 . 7 u _6 . 3 V _ X 5R _ 06 *0 . 1 u _1 0 V _ X5 R _0 4 *0 . 1 u _1 0 V _ X5 R _0 4
A2 2 P3 2
16mA
RT CV CC V CC RT C V CCS US H DA 3 . 3A _ 1 . 5 A _ H D A _I O
RT C
HD A
C 4 60 C4 6 2 C4 6 1 11/ 01
C o u g arP o i n t _R e v _1 p 0 C2 0 4
1 u _ 6. 3 V _ Y 5V _ 0 4 0 . 1u _ 1 0V _X 5 R _ 0 4 0 . 1u _ 1 0V _X 5 R _ 0 4
0 . 1u _ 1 0V _ X 5 R _ 0 4
Schematic Diagrams
CougarPoint - M 9/9
CougarPoint -M (GND)
U37I
U37H
AY 4 H46 H5
AY 42 VSS [159] VS S[259] K 18 VS S[0]
AY 46 VSS [160] VS S[260] K 26 AA 17 A K38
AY 8 VSS [161] VS S[261] K 39 A A2 VS S[1] VSS [80] A K4
B11 VSS [162] VS S[262] K 46 A A3 VS S[2] VSS [81] A K42
B15 VSS [163] VS S[263] K7 AA 33 VS S[3] VSS [82] A K46
B19 VSS [164] VS S[264] L18 AA 34 VS S[4] VSS [83] A K8
B23 VSS [165] VS S[265] L2 AB 11 VS S[5] VSS [84] A L16
B35 VSS [168] VS S[268] L28 A B4 VS S[8] VSS [87] A L2
B7 VSS [170] VS S[270] L48 A B5 VS S[10] VSS [89] A L23
F45 VSS [171] VS S[271] M12 A B7 VS S[11] VSS [90] A L26
BB12 VSS [172] VS S[272] P 16 AC 19 VS S[12] VSS [91] A L27
BB16 VSS [173] VS S[273] M18 AC2 VS S[13] VSS [92] A L31
BB20 VSS [174] VS S[274] M22 AC 21 VS S[14] VSS [93] A L33
BB28 VSS [177] VS S[277] M32 AC 34 VS S[17] VSS [96] A M11
BB30 VSS [178] VS S[278] M34 AC 48 VS S[18] VSS [97] A M14
BB38 VSS [179] VS S[279] M38 AD 10 VS S[19] VSS [98] A M36

B B4 VSS [180] VS S[280] M4 AD 11 VS S[20] VSS [99] A M39
BB46 VSS [181] VS S[281] M42 AD 12 VS S[21] VS S[100] A M43
BC14 VSS [182] VS S[282] M46 AD 13 VS S[22] VS S[101] A M45
Sheet 21 of 43 BC18
BC2
BC22
VSS [183]
VSS [184]
VSS [185]
VS S[283]
VS S[284]
VS S[285]
M8
N18
P 30
AD 19
AD 24
AD 26
VS S[23]
VS S[24]
VS S[25]
VS S[102]
VS S[103]
VS S[104]
A M46
A M7
A N2
BC26 VSS [186] VS S[286] N47 AD 27 VS S[26] VS S[105] A N29
CougarPoint - M 9/9 BC32
BC34
BC36
VSS [187]
VSS [188]
VSS [189]
VS S[287]
VS S[288]
VS S[289]
P 11
P 18
T33
AD 33
AD 34
AD 36
VS S[27]
VS S[28]
VS S[29]
VS S[106]
VS S[107]
VS S[108]
A N3
A N31
A P12
BC40 VSS [190] VS S[290] P 40 AD 37 VS S[30] VS S[109] A P19
BD46 VSS [193] VS S[293] P7 AD4 VS S[33] VS S[112] A P32
BD5 VSS [194] VS S[294] R2 AD 40 VS S[34] VS S[113] A P38
BE22 VSS [195] VS S[295] R48 AD 42 VS S[35] VS S[114] A P4
BE26 VSS [196] VS S[296] T12 AD 43 VS S[36] VS S[115] A P42
BE40 VSS [197] VS S[297] T31 AD 45 VS S[37] VS S[116] A P46
BF10 VSS [198] VS S[298] T37 AD 46 VS S[38] VS S[117] A P8
BF12 VSS [199] VS S[299] T4 AD8 VS S[39] VS S[118] A R2
BF16 VSS [200] VS S[300] W 34 A E2 VS S[40] VS S[119] A R48
BF20 VSS [201] VS S[301] T46 A E3 VS S[41] VS S[120] A T11
BF22 VSS [202] VS S[302] T47 AF 10 VS S[42] VS S[121] A T13
BF24 VSS [203] VS S[303] T8 AF 12 VS S[43] VS S[122] A T18
BF26 VSS [204] VS S[304] V 11 AD 14 VS S[44] VS S[123] A T22
BF28 VSS [205] VS S[305] V 17 AD 16 VS S[45] VS S[124] A T26
BD3 VSS [206] VS S[306] V 26 AF 16 VS S[46] VS S[125] A T28
BF30 VSS [207] VS S[307] V 27 AF 19 VS S[47] VS S[126] A T30
B F8 VSS [210] VS S[310] V 36 AF 27 VS S[50] VS S[129] A T39
BG17 VSS [211] VS S[311] V 39 AF 29 VS S[51] VS S[130] A T42
BG21 VSS [212] VS S[312] V 43 AF 31 VS S[52] VS S[131] A T46
BG33 VSS [213] VS S[313] V7 AF 38 VS S[53] VS S[132] A T7
BG44 VSS [214] VS S[314] W 17 A F4 VS S[54] VS S[133] A U24
BG8 VSS [215] VS S[315] W 19 AF 42 VS S[55] VS S[134] A U30
BH11 VSS [216] VS S[316] W2 AF 46 VS S[56] VS S[135] A V16
BH15 VSS [217] VS S[317] W 27 A F5 VS S[57] VS S[136] A V20
BH17 VSS [218] VS S[318] W 48 A F7 VS S[58] VS S[137] A V24
BH19 VSS [219] VS S[319] Y 12 A F8 VS S[59] VS S[138] A V30
H10 VSS [220] VS S[320] Y 38 AG 19 VS S[60] VS S[139] A V38
BH27 VSS [221] VS S[321] Y4 AG2 VS S[61] VS S[140] A V4
BH31 VSS [222] VS S[322] Y 42 AG 31 VS S[62] VS S[141] A V43
BH33 VSS [223] VS S[323] Y 46 AG 48 VS S[63] VS S[142] A V8
BH35 VSS [224] VS S[324] Y8 AH 11 VS S[64] VS S[143] A W14
BH39 VSS [225] VS S[325] B G29 AH3 VS S[65] VS S[144] A W18
BH43 VSS [226] VS S[328] N24 AH 36 VS S[66] VS S[145] A W2
BH7 VSS [227] VS S[329] A J3 AH 39 VS S[67] VS S[146] A W22
D3 VSS [228] VS S[330] A D47 AH 40 VS S[68] VS S[147] A W26
D12 VSS [229] VS S[331] B 43 AH 42 VS S[69] VS S[148] A W28
D16 VSS [230] VS S[333] B E10 AH 46 VS S[70] VS S[149] A W32
D18 VSS [231] VS S[334] B G41 AH7 VS S[71] VS S[150] A W34
D22 VSS [232] VS S[335] G14 AJ 19 VS S[72] VS S[151] A W36
D24 VSS [233] VS S[337] H16 AJ 21 VS S[73] VS S[152] A W40
D26 VSS [234] VS S[338] T36 AJ 24 VS S[74] VS S[153] A W48
D30 VSS [235] VS S[340] B G22 AJ 33 VS S[75] VS S[154] A V11
D32 VSS [236] VS S[342] B G24 AJ 34 VS S[76] VS S[155] A Y 12
D34 VSS [237] VS S[343] C22 AK 12 VS S[77] VS S[156] A Y 22
D38 VSS [238] VS S[344] A P13 A K3 VS S[78] VS S[157] A Y 28
D42 VSS [239] VS S[345] M14 VS S[79] VS S[158]
D8 VSS [240] VS S[346] A P3 CougarPoi nt_Rev _1p0
E18 VSS [241] VS S[347] A P1
E26 VSS [242] VS S[348] B E16
G18 VSS [243] VS S[349] B C16
G20 VSS [244] VS S[350] B G28
G26 VSS [245] VS S[351] B J28
G28 VSS [246] VS S[352]
G36 VSS [247]
G48 VSS [248]
H12 VSS [249]
H18 VSS [250]
H22 VSS [251]
H24 VSS [252]
H26 VSS [253]
H30 VSS [254]
H32 VSS [255]
H34 VSS [256]
F3 VSS [257]
VSS [258]
CougarPoint_Rev _1p0
Schematic Diagrams
New Card, Mini PCIE
NEW CARD(Port 3)
Sheet 22 of 43
New Card, Mini
PCIE
10 /29
MINI CARD WLAN 20 mil

3 .3 V
C4 7 2
11/01 0 . 1 u_ 1 6V _Y 5 V _0 4
J _M I N I 1
R6 0 5 *0 _ 04 1 2
[ 15 , 2 4 , 26 ] P C I E _ W A K E # 3 W AKE# 3. 3 V A U X_ 0 6
R 4 90 1 0 K _ 04 5 C O E X1 1 . 5V _ 0 8
3 .3 V C O E X2 U I M _P W R 10 VD D3
R5 5 2 *0 _ 0 4 B T_ S B D #
7 UIM _ DA T A 12
[ 1 4 ] W L A N _ C L K R E Q# 11 C L K R E Q# U I M_ C L K 14 8 0C LK [ 27 ]
R4 9 1 *1 0 m li _ 04
[1 4 ] CL K_ PCIE _ M INI# 13 REF C L K- UIM _ RE S E T 16
[ 1 4 ] C L K _ P C I E _M I N I 9 REF C L K+ U I M_ V P P 3 I N 1 [ 2 7]
15 GN D 0 4
GN D 1 GN D 5
KEY
21 18
27 GN D 2 GN D 6 26
29 GN D 3 GN D 7 34
GN D 4 GN D 8 40
35 GN D 9 50
[ 2 7 ] W L A N _ D E T# 23 GN D 1 1 G ND1 0
[ 14 ] P C I E _ R X N 3 _ W L A N 25 P E T n0 20
[ 1 4 ] P C I E _R XP 3_ W L A N 31 P E T p0 W _ DIS A B L E # 22 W L A N _ E N [ 27 , 2 8 ]
[ 1 4 ] P C I E _T X N 3 _ W L A N 33 P ERn 0 P ERSE T # 30 B U F _ P L T _R S T # [ 17 , 2 4 , 26 , 2 7 ]
[ 1 4] P C I E _ T XP 3_ W L A N P ERp 0 SM B _ CL K 32
17 S M B _ DA T A 36 US B _ D # B T _D E T # [ 2 7 , 2 8]
R3 5 7 * 1 0m i _l 0 4 U S B _ P N 2 [ 17 ]
R4 9 4 *0 _ 04 19 R e s erv ed 0 U S B _D - 38 US B _ D R3 5 6 * 1 0m i _l 0 4
[ 27 , 2 8 ] B T _E N 37 R e s erv ed 1 U S B_ D+ USB _ P P 2 [1 7 ]
39 GN D 1 2 24 R4 8 9 0 _ 04
3. 3 V 3. 3V A U X _3 3. 3 V A U X_ 1 3 . 3V
41 28
43 3. 3V A U X _4 1 . 5V _ 1 48
R 1 99 * 0_ 0 4 CL _ CL K _ 1 45 GN D 1 3 1 . 5V _ 2 52
[ 1 4] C L _C L K 1 47 R e s erv ed 2 3. 3 V A U X_ 2 42 3 . 3V
R 2 04 * 0_ 0 4 CL _ DA T A _ 1
[ 1 4] C L _D A T A 1 R 4 98 * 0_ 0 4 CL _ RS T # _ 1 49 R e s erv ed 3 L E D _W W A N # 44
[ 1 4] C L _R S T #1 51 R e s erv ed 4 L E D_ W L A N# 46 W L A N _ L E D # [ 2 7 , 28 ]
R4 9 9 * 10 K _ 0 4
3 . 3V R e s erv ed 5 L E D _W P A N #
R5 0 1 0 _0 4 MP C E C - S 00 F 1 -T P 0 0
[ 27 , 2 8 ] B T _E N
B T _S B D # R5 5 3 *0 _ 04
[ 1 4 ] B T _S B D # 1 0/ 29
[ 3 , 6, 8, 9 , 1 0 , 20 , 2 6 , 28 , 3 1 , 33 ] 1 . 5 V
[ 19 , 2 9 , 31 ] 1 . 5 V S
[ 2 , 3, 8 , 1 1 , 13 , 1 4 , 1 5, 1 7 , 1 8, 1 9 , 2 0, 2 3 , 2 6, 2 8 , 3 0, 31 , 3 3 , 34 , 3 5 ] 3. 3 V
[ 3, 9 , 1 0 , 11 , 1 2 , 13 , 1 4 , 15 , 1 6 , 1 7, 1 8 , 1 9, 2 0 , 2 3, 2 4 , 2 5, 2 7 , 2 8, 29 , 3 0 , 31 , 3 6 ] 3. 3 V S
[ 1 3 , 2 4, 27 , 3 1 , 32 , 3 8 ] V D D 3
New Card, Mini PCIE B - 23
Schematic Diagrams
CCD, 3G, TPM

MINI CARD 3G(Port 6) 3G POWER R5 0 9 *0 _ 06
3 .3 V Q3 0 3G _3 . 3 V
3 G_ 3 . 3V A O 34 1 5
>48 mil >48 mil
S D
J_ 3 G1 60m ils
1 2
3 W AKE # 3. 3V A U X_ 0 6 C 50 0 C5 0 7 C 4 83
G
5 C OE X 1 1 . 5V _ 0 8 U I M_ P W R R 51 5
C OE X 2 U I M _P W R 10 U I M_ D A TA C2 0 9 C 2 87 1 0 u_ 1 0V _Y 5V _ 0 8 0. 1 u _1 6 V _ Y 5 V _ 04
7 U I M_ D A T A 12 +
U I M_ C L K C2 1 2 0 . 1 u _1 6 V _ Y 5 V _0 4 R5 2 0 1 0 _0 6
11 C LK R E Q# U I M_ C L K 14 U I M_ R S T 0. 1 u _ 16 V _ Y 5 V _ 04 22 0 u_ 6 . 3 V _6 . 3 *6 . 3 *4 . 2
13 R E F CL K - UIM _ RE S E T 16 U I M_ V P P 0. 1 u _ 16 V _ Y 5 V _ 04 1 0 0K _ 0 4
D
9 R E F CL K + U I M_ V P P
15 G ND0 4 R5 1 9 Q 33
G ND1 GN D 5 G M TN 7 00 2 Z H S 3
S
KEY 3 30 K _ 04
Q3 5
21 18 G MT N 70 0 2Z H S 3
27 G ND2 GN D 6 26 [ 2 7 ] 3 G_ P W R _ E N
29 G ND3 GN D 7 34
S
G ND4 GN D 8 40
GN D 9 From H8 default HI
35 50
[ 2 7 ] 3 G_ D E T # 23 G ND1 1 G ND1 0
25 PETn 0 20
31 PETp 0 W _ DIS A B L E # 22 3 G _E N [ 2 7]
33 P E R n0 P E RS E T # 30
3 G_ 3 . 3 V
17
19
P E R p0
R es e rv e d0
S MB _ C L K
S M B _ DA T A
U S B _D -
32
36
38 U S B _P N 4 [ 17 ]
SIM CONN
37 R es e rv e d1 US B _ D+ U S B _P P 4 [ 1 7 ]
39 G ND1 2 24
41 3 .3 V A UX _ 3 3. 3V A U X_ 1 28 3 G_ 3 . 3 V
43 3 .3 V A UX _ 4 1 . 5V _ 1 48 U I M_ P W R R5 0 3 *4 . 7K _ 0 4 U I M_ D A T A
45 G ND1 3 1 . 5V _ 2 52
C2 4 2 C2 6 7 C2 3 5
Sheet 23 of 43 0 . 1u _ 1 6V _ Y 5 V _ 0 4 1 0u _ 10 V _ Y 5 V _ 0 8
47
49
51
R es e rv e d2
R es e rv e d3
R es e rv e d4
3. 3V A U X_ 2
LE D _ W W A N #
L E D_ W L A N#
42
44
46 C2 8 6
3G _3 . 3 V
0. 1 u _ 16 V _ Y 5 V _ 04
J_ S I M 1
CCD, 3G, TPM

R es e rv e d5 LE D _ W P A N # +
88 9 10 -5 2 04 M-0 1 2 20 u _4 V _ V _ A R 5 04 LOCK R 48 8
*1 0m i l _0 4 (TOP VIEW) * 1 0m i _l 0 4
U I M _C LK U I M _C C 3 C 7 U I M_ D U I M_ D A T A
U I M _R S T C 2 U I M_ C L K U I M_ D A T A C 6 U I M_ V P P
U I M _P W R C 1 U I M_ R S T U I M_ V P P C 5
U I M_ P W R U I M_ GN D
C 4 70 C 46 9 C4 7 1
OPEN
C 4 89 C 1 7 70 6 61 -1 S I M LO C K * 2 2p _ 50 V _ N P O _0 4 * 22 p _ 50 V _ N P O _0 4 *2 2 p_ 5 0V _ N P O_ 0 4
* 22 p _ 50 V _ N P O _0 4
3. 3 V S
TPM 1.2
A sse rted bef ore en te ring S3
C5 0 8 C2 8 5 C2 9 4 C 3 00
L PC r es et timing:
L PCPD# inact ive to LRST# inact ive 3 2~96us
*0 . 1 u_ 1 6 V _Y 5V _ 0 4 *0 . 1 u_ 1 6V _Y 5V _ 0 4 *0 . 1 u_ 1 6V _ Y 5V _ 0 4 *1 u_ 1 6 V _X 5 R _ 0 6 CCD
U 28 5V 5 V _C C D
26 10 U 41
[ 1 3 , 27 ] L P C_ A D 0 48 mil
23 L A D0 V D D1 19 4 1
[ 1 3 , 27 ] L P C_ A D 1 20 L A D1 V D D2 24 5 VIN V OU T
[ 1 3 , 27 ] L P C_ A D 2 17 L A D2 V D D3 VIN
[ 1 3 , 27 ] L P C_ A D 3 L A D3 MJ_CCD1
C2 R1 1 C 6 C5 C4
21 3 2 1
[ 17 ] P C LK _ T P M L CL K TPM EN G ND
3 . 3V S *1 u _6 . 3 V _ Y 5 V _ 04 *1 00 K _ 0 4 0 . 1 u_ 1 6V _Y 5V _ 0 4 1 u_ 6 . 3 V _Y 5 V _0 4 1 u_ 6 . 3 V _Y 5 V _0 4
22 5 G 5 24 3 A
[ 1 3 , 27 ] L P C _ F R A ME # 16 L F RA M E # VSB 5
[ 3 , 17 ] P L T _R S T # 27 L RE S E T # C2 8 2
[ 1 3 , 27 ] S E R IRQ 15 S E R IRQ
[ 15 ] P M _C L K R U N # C LK R U N # *0 . 1 u_ 1 6V _Y 5V _ 0 4 J _ CC D1
28 6 T P M3 0 0 4
[ 15 ] S 4 _ S TA TE # L P CP D # GP I O 2 [ 27 ] C C D _ E N 1
T P M3 0 0 5
T P M_ B A D D 9 G P I O2 [ 17 ] U S B _P N 5 2
T E S T B I/B A DD 13 [ 1 7] U S B _ P P 5 3
XTALI C C D _D E T #
TP M _P P 7 XT A L I [2 7 ] CC D_ DE T # 4
PP X7 5
14 XTALO 4 1 * MC -1 4 6 _3 2 . 7 68 K H z 8 5 2 05 -0 50 0 1
T P M 30 0 1 1 XTAL O 3 2
HI: ACCESS N C_ 1
6-22-32R76-0B4 From H8 default HI
T PM _PP T P M 30 0 2 3 4 C 3 05 C 30 2
L OW: NORMAL ( Int ernal PD) T P M 30 0 3 12 N C_ 2 G ND_ 1 11
N C_ 3 G ND_ 2 18 * 18 p _ 50 V _ N P O _0 4 * 18 p _5 0 V _ N P O _0 4
HI: 4E/ 4F H G ND_ 3
8 25
T PM _BADD L OW: 2E/ 2F H TESTI G ND_ 4
* S L B 96 3 5T T
R3 4 9 C 2 92 X TA L O
P C LK _ T P M P C LK _ T P M1
X TA L I [ 2 , 3, 8, 1 1 , 13 , 1 4 , 15 , 1 7 , 18 , 1 9, 20 , 2 2, 2 6 , 2 8, 3 0 , 3 1, 3 3 , 3 4, 3 5 ] 3 . 3V
Co-layout X7, X8 [ 3 , 9 , 1 0, 1 1 , 1 2, 1 3 , 14 , 1 5 , 16 , 1 7 , 18 , 1 9, 20 , 2 4, 2 5 , 2 7, 2 8 , 2 9, 3 0 , 3 1, 3 6 ] 3 . 3V S
*3 3 _0 4 *1 0 p_ 5 0V _ N P O_ 06
[ 2 0 , 2 6, 3 0 , 3 1, 3 3 , 3 4, 3 5 ] 5 V
3 . 3V S 1 4 X8
2 3
*1 T JS 12 5 D J 4 A 42 0 P _ 32 . 7 68 K H z
T P M _P P R 3 41 *1 0 K _0 4
6-22-32R76-0B2
T P M _B A D D R 3 48 *1 0 K _1 % _0 4 6-22-32R76-0BG
R 3 52 *1 0 K _1 % _0 4
B - 24 CCD, 3G, TPM
Schematic Diagrams
Card Reader/LAN JMC251C

S D _C L K
JMC251C C 4 54 ne ar P in# 41
Switch ing Regulator
close to PIN33
3. 3V _ LA N
3 .3 V S V D D 3
*1 0p _5 0V _N P O_0 6 11 /0 2 D VD D R 42 5 * 4. 7K _ 04
SD _ C LK R 4 48 *2 0mi l _0 4 (>20 mil) L3 7 10/29 U 35
R E GLX . DV DD LA N _ SC L R 42 6 * 4. 7K _ 04 8 7
(>20mil) VCC WP MP D R 21 6 1 0K _0 4
S D X C _P OWE R S WF 25 20 C F -4R 7M-M C 17 7 C 44 8 6
3 .3 V S LA N _ SD A 5 SCL 1 R 21 7 * 4. 7K _0 4
SD X C _ POW E R
SDA A0 2
I SON_ 25 1C
S D _ C LK _C
C 16 5 For JMC251/261 only 10 u_ 6. 3 V_ X5 R _0 6 0. 1 u_ 16 V_ Y 5V _0 4
LA N _ LE D0
LA N _ LE D1
3. 3V _ LA N
R 49 7 *4 . 7K _0 4 S D _C D # C 17 0 Pi n#3 3 Pi n# 33 4 A1 3
MD I O1 1
S D _ BS
REGL X
GN D A2
S D _D3
S D _D2
S D _D1
S D _D0
DV DD
0. 1 u_ 16 V_ Y 5V _0 4 2. 2 u_ 6. 3V _ Y 5V _0 6 C 44 0 0 . 1u _16 V _Y 5 V_ 04
R 49 3 1 0K _0 4 MS _I N S # *A T2 4C 0 2B N
V DD3
V C C _ C AR D
R 15 8 1 K_ 04 S D _W P
45
44
43
42
41
34
33
48
47
46
40
39
38
37
36
35
U 36
R 2 07
M DI O5
M DI O4
M DIO 3
Ca rd Rea der Pu ll High /Lo w
MDI O1 1
LA N _ LE D0
LA N _ LE D1
MD IO 2
MD I O1
MD I O0
F B1 2
VD DI O
I SON
GND
GND
LX
VD DO
* 28m li _0 6
Re sis tor s V D D R EG 3. 3 V S
(>20mil) (>20mi l) (>20mil)
MD I O10 49 32 VD D R EG
MD I O9 50 MD I O1 0 V DDRE G 31 (>20mil)
MD I O8 51 MD I O9 V C C 3V 30 3 . 3V S
V C C _ C AR D C 1 99 C 198 C 44 3 C 44 2
R 162 *2 0mi l _04 A V D D 12 _52 52 MD I O8 P W RCR 29
D VD D 53 V DD TE S T 28 MPD
[2 5] LA N _ MD I P0 V I P _1 MP D 1 0u _6 . 3V _X 5R _ 06 0 . 1u _1 6V _Y 5 V _04 *10 u_ 6. 3V _ Y 5V _0 6 0. 1u _1 6V _ Y 5V _0 4
54 27 LA N _P C I E _W A KE # P in# 32 P in #3 2 P in #3 1 Pi n# 31
R 156 *2 0mi l _04 [2 5] LA N _ MD I N 0 A V D D 12 _55 55 V I N _1 W AK E N 26 LA N _S C L 3 . 3V _L A N V DD3
D VD D 56 A V D D 12 LA N _L ED 2 25 LA N _S D A
2[ 5] LA N _ MD I P1
[2 5] LA N _ MD I N 1
57
58
V I P _2
V I N _2 JMC251 C C R _ LE D
R ST N
24
23 C PP E N BU F _ PL T_ R ST # [ 17 , 22 ,2 6, 2 7] V DD3
R 43 1 *0_ 06
59 GN D C PP E N 22 11 /0 2
3. 3 V_ LA N LA N _ MD I P2 60 A V D D 33 GN D 21 I S ON _2 51 CR 1 91 *20 mi _l 04
[2 5] LA N _ MD I P2 (LQFP 64) 3 . 3V _L AN
2[ 5] LA N _ MD I N 2 LA N _ MD I N 2 61 V I P _3 V DDIO 20 SD _ WP
D VD D R 144 *2 0mi l _04 A V D D 12 _62 62 V I N _3 MD IO 6 19 MD I O12 R 1 90 *10 0K _0 4 3. 3 V_ LA N
LA N _ MD I P3 63 A V D D 12 MD I O1 2 18 MD I O14
2[ 5] LA N _ MD I P3 LA N _ MD I N 3 64 V I P _4 MD I O1 4 17 SD _ C D #
[2 5] LA N _ MD I N 3 V I N _4 C R _C D 0 N
C R_C D1 N
R 434 1 0K _0 4
A V DD 33
AV DD 1 2
A V DD 12
MDI O1 3
D1 6
MDI O7
REXT
X OUT
C LK N
C LK P
RXN
GND
T XN
T XP
X IN
R XP
P C I E_ WA K E # A C LA N _ PC I E _W A K E#
10/2 9 [ 15 , 22, 2 6] P C I E_ WA K E # LA N _P C I E _W AK E # [ 27 ]
PCIe D ifferential
16
R B 7 51 S-4 0C 2
1
2
3
4
5
6
7
*20 mi _l 04 8
9
10
11
12
A V DD 12 _13 13
14
15
J MC 25 1-LGB Z 0C Pairs = 100 Ohm
R E X T_C
AV D D1 2_ 7
CR _CD 1 N
LA N X OUT
MD I O1 3
LA N X I N
MD I O7
R 14 2
12 K_ 1% _0 4
Sheet 24 of 43
4 IN 1 SO CKET SD/MM C/MS/ MS Pr o
Card Reader/LAN
*2 0m li _0 4
R 14 5
DV DD R 1 46
AV D D 1 2_ 7 AV D D 1 2_ 13
3. 3 V_ LA N
R 13 6 *0 _0 4 MS _I N S # J_ C AR D -R E V 1
DVDD
P1
C 43 5
0. 1u _1 6V _Y 5 V _0 4
C 13 9
0. 1u _1 6V _Y 5V _0 4 P C I E_ R XP _4 _GL A N
R 42 7
C 4 33
*2 0m li _0 4 11 /0 2
0. 1 u_ 10 V_ X7 R _0 4 P C I E _R X P 4_GL A N [ 1 4]
Card Reader
S D _C D #
S D _D 2
S D _D 3
S D _B S
P2
P3
P4
C D _ SD
D A T2 _S D
C D / D A T3 _S D
C MD _ SD
JMC251C
Pi n#7 Pi n#1 3 P C I E_ R XN _ 4_ GLA N C 4 34 0. 1 u_ 10 V_ X7 R _0 4 Power P5
PC I E _ R XN 4 _GLA N [ 14 ] P6 V S S_ S D
V C C _C A R D V CC_ CA RD S D _C L K P7 V D D _S D
C 48 2 P8 C L K_ S D
AV D D 1 2_ 52 AV D D 1 2_ 55 A VD D 1 2_ 62 A VD D 12_ 7 S D _D 0 P9 V S S_ S D
P C I E _TX N 4_ GLA N [ 14 ] 0. 1u _1 6V _Y 5 V _0 4 S D _D 1 P 10 D A T0 _S D
P C I E_ TX P4 _GL A N [ 1 4] S D _W P P 11 D A T1 _S D
C L K_ P C I E_ GLA N [ 14 ] P 12 W P _S D
C LK _ PC I E _GL A N # [ 14 ] R 49 6
C 44 5 C 15 7 C 14 5 C 13 6 L AN X OU T *7 5_ 04 P 13 V S S_ MS
V CC_ CA RD S D _C L K P 14 V C C _MS
S D _D 3 P 15 S C LK _ MS
0. 1u _1 6V _Y 5 V _0 4 0. 1u _1 6V _Y 5V _0 4 0. 1 u_1 6V _ Y 5V _0 4 *1 0u_ 6. 3 V_ X5 R _0 6 C 47 9 D A T3 _MS
Pi n#5 2 Pi n#5 5 Pi n# 62 Pi n# 7 R 428 *1 M_04 LA N X IN MS _I N S # P 16
Re se rv ed 0. 1u _1 6V _Y 5 V _0 4 S D _D 2 P 17 I N S _MS
X 10 S D _D 0 P 18 D A T2 _MS
2 1 For JMC251 C S D _D 1 P 19 S D I O/ D A T0_ MS
S D _B S P 20 D A T1 _MS P2 2
3. 3 V_ LA N FS X 5L_ 25 MH Z P 21 B S _MS GN D P2 3
X9 V S S_ MS GN D
3. 3 V_ LA N
MD R 01 9-C 0 -1 04 2
3 4
C 13 4 C 14 8 C 45 0 C 19 5
2 1
0. 1u _1 6V _Y 5 V _0 4 0. 1u _1 6V _Y 5V _0 4 C 43 1 * FS X5 L_ 25 MH z C 432 0 . 1u _16 V _Y 5 V_ 04 * 10u _6 . 3V _X 5R _ 06
Pi n#4 3 Pi n#4 3
2 2p _50 V _N P O_0 4 P in #2 P in #2
22p _5 0V _N PO_ 04
3. 3 V_ LA N
6-22-25R00-1B4
6-22-25R00-1B5 V C C _C A R D VC C _C A R D
C 13 3 C 13 5 C 18 9 C 43 7
*10 u_ 6. 3V _ X5R _06 *0. 1 u_ 16V _ Y 5V _0 4 *0. 1 u_ 16 V_ Y 5V _0 4 0. 1 u_ 16 V_ Y 5V _0 4

Pi n#5 9 Pi n#5 9 Pi n# 2 Pi n# 21 C 4 78 C 4 81 C 4 80
Re ser ve d
* 0. 1u _1 6V _Y 5 V _0 4 *0 . 1u _1 6V _Y 5 V_ 04 *0 . 1u _1 6V _Y 5 V_ 04
P lac e a l c a p ac ito rs c lo se d to c h ip .
Near Ca rdr ead er CON N
T h e s u b sc rip t in e ac h CA P in c ic ate s th e p in
n u mb er o f J M C 25 1 /JM C2 6 1 t h at s h o u ld b e
c ol s e d to .
VD D 3
2A V DD3
P C 1 02 1.2V
U 20 *1 u_ 10 V_ Y 5V _ 06
5 6 D VD D
P C 99 P R 1 15 9
7
VIN
VIN
V C N TL
4
1A
*0 _0 4 P OK V OU T
*0 .1 u_ 16 V_ Y 5V _0 4
3
8 V OU T P R 1 16
EN * 1. 27 K _1 %_0 4
1 2
GN D VFB
PC9 8
*A X 6 6 1 0
* 82 p_5 0V _ N PO_ 04
PR 1 14
GS 711 3 *2. 4 9K _1 %_ 04
10/29
6- 02- 071 13- 320
AX 661 0
6- 02- 066 10- 320
[ 13, 2 2, 2 7, 31 , 32 ,3 8] V D D 3
[ 25 ] D VD D
[ 3, 9 , 10 1, 1, 1 2, 13 , 14 , 15, 1 6, 1 7, 18 , 19 ,2 0, 2 3, 25 , 27 , 28, 2 9, 3 0, 31 , 36 ] 3 . 3V S
[3 , 6, 8 9, , 10 , 20, 2 6, 2 8, 31 , 33 ] 1 . 5V
[ 2 0, 23 , 26 , 30, 3 1, 3 3, 34 , 35 ] 5 V
Card Reader/LAN JMC251C B - 25
Schematic Diagrams
LAN (JMC251C), SATA HDD, ODD

R3 7 4 * 0_ 0 4
1L 25 2
GIGA LAN (JMC251C) 4
R3 7 5
3
* W CM 20 1 2 F 2 S -S H O R T
* 0_ 0 4
R3 7 6 * 0 _0 4
L29 1L 26 2
J _R J 1
L A N_ MD IP 0 12 13 L MX 1+ 4 3 D L MX 1 + 1 GN D 1
DV D D [2 4 ] L A N_ M D IP 0 L A N_ MD IN 0 11 T D4 + M X4 + 14 L MX 1- *W C M 2 01 2 F 2 S -S H O R T D L MX 1 - 2 DA + s h ei l d GN D 2
[2 4 ] L A N_ M D IN 0 L A N_ MD IP 1 9 T D4 - M X4 - 16 L MX 2+ D L MX 2 + 3 DA - s h ei l d
R3 7 8 *0 _ 04 R3 7 7 * 0 _0 4
[2 4 ] L A N_ M D IP 1 L A N_ MD IN 1 8 T D3 + M X3 + 17 L MX 2- D L MX 2 - 6 DB +
[2 4 ] L A N_ M D IN 1 T D3 - MX 3 - 1L 27 2 DB -
G ND
R 75
L A N_ MD IP 2 6 19 L MX 3+ 4 3 D L MX 3 + 4
* 0_ 0 4 [2 4 ] L A N_ M D IP 2 L A N_ MD IN 2 5 T D2 + MX 2 + 20 L MX 3- * W CM 20 1 2 F 2 S -S H O R T D L MX 3 - 5 DC+
[2 4 ] L A N_ M D IN 2 L A N_ MD IP 3 3 T D2 - M X2 - 22 L MX 4+ D L MX 4 + 7 DC-
[2 4 ] L A N_ M D IP 3 T D1 + MX 1 + R3 8 0 *0 _ 04 R3 8 5 * 0 _0 4
L A N_ MD IN 3 2 23 L MX 4- D L MX 4 - 8 DD+
[2 4 ] L A N_ M D IN 3 T D1 - MX 1 - 1L 28 2 DD-
10 15 P J S -0 8S L 3 B
7 T CT 4 MC T 4 18 4 3
4 T CT 3 MC T 3 21 *W C M 2 01 2 F 2 S -S H O R T
1 T CT 2 MC T 2 24
W240HU PJS-08SL3B
R3 8 7 * 0 _0 4
T CT 1 MC T 1 W250HU PJS-08SO1B-1
C 54 C3 4 3 C3 4 2 C3 4 1 G S T 50 0 9 LF
0 .0 1u _ 1 6V _ X 7 R _ 0 4 *0 . 0 1u _ 1 6V _ X 7 R _ 0 4
*0 .0 1 u_ 1 6 V _X 7 R _ 0 4 *0 .0 1u _ 16 V _ X 7 R _ 04 N MC T_ 1 R4 0 2 75 _ 1 %_ 0 4 N M C T _R
N MC T_ 2 R3 9 9 75 _ 1 %_ 0 4
N MC T_ 3 R3 9 7 75 _ 1 %_ 0 4
N MC T_ 4 R3 9 4 75 _ 1 %_ 0 4
C 3 35
1 0 0 0p _ 2 K V _ X7 R _ 1 2
Sheet 25 of 43
LAN(JMC251C),
SATA HDD, ODD
SATA HDD SATA ODD

Zero Power ODD 5 VS
J _ HD D1
S1 J _ OD D 1
S2 S A TA _ T X P 0 C4 8 7 0 .0 1 u_ 1 6 V _X 7 R _ 0 4 S1
S3 S A TA _ T X N 0 C4 8 6 0 .0 1 u_ 1 6 V _X 7 R _ 0 4 S A TA T X P 0 [1 3] G ND 1 S2 C4 3 0 0 .0 1u _ 1 6V _ X 7 R _ 0 4
S4 S A TA T X N 0 [1 3 ] A+ S3 S A T A T X P 2 [13 ]
C4 2 8 0 .0 1u _ 1 6V _ X 7 R _ 0 4
S5 S A TA _ R XN 0 C4 8 5 0 .0 1 u_ 1 6 V _X 7 R _ 0 4 A- S4 S A T A T X N 2 [1 3]
S6 S A TA _ R XP 0 S A TA R X N 0 [ 1 3] G ND 2 S5
C4 8 4 0 .0 1 u_ 1 6 V _X 7 R _ 0 4 C4 2 5 0 .0 1u _ 1 6V _ X 7 R _ 0 4
S7 S A TA R X P 0 [ 13 ] B- S6 C4 2 1 0 .0 1u _ 1 6V _ X 7 R _ 0 4 S A T A R XN 2 [ 13 ]
B+ S7 S A T A R XP 2 [1 3 ]
3 . 3V S
G ND 3 C 5 21 C 5 22
P1 1.5A
P2 0 . 1 u _1 6 V _ Y 5 V _ 04
P3 P1 5 V S _ OD D * 0 .01 u _ 16 V _ X 7R _ 04
P4 DP P2 S A T A _ OD D_ P R S N T # [1 8 ]
U 42
P5 V_ 5 0 P3 S A T A _ OD D_ D A # [1 7 ] 1 4
P6 V _5 0 _ 1 P4 V O UT VIN 5
P7 MD P5 VIN
5V S
P8 G ND 4 P6 C4 1 1 C 4 10 C4 0 8 C4 0 4 +C 3 9 3
P9 1A G ND 5 2 3
S A T A _ OD D_ P W R GT [1 8]
P1 0 C 18 5 5 3-1 1 3 05 -L *1 0 0 u_ 6 . 3 V _B 2 GN D EN
P1 1 H D D _N C 0
0 . 1u _ 1 6V _ Y 5 V _ 0 4
0 . 1u _ 1 6V _ Y 5 V _ 0 4
0 . 1u _ 1 6V _ Y 5V _ 0 4 0. 1 u _ 16 V _ Y 5 V _ 0 4 1 u_ 6 .3 V _Y 5 V _0 4 10 u _ 10 V _ Y 5 V _ 0 8 G5 2 43 A
*0 . 1 u _1 6 V _ Y 5 V _0 4
1u _ 6 . 3V _Y 5 V _ 0 4
10 u _ 10 V _ Y 5 V _ 08
P1 2
P1 3 H D D _N C 1 R 5 55 1 0 0K _ 0 4
P1 4 H D D _N C 2
P1 5 H D D _N C 3
+ C 2 08
A LL T OP -C 16 6 N 5 -1 2 20 5 -L
P IN G N D1 ~ 2 = G N D *1 00 u _ 6. 3 V _ B _ A
5 V S [1 1 ,12 ,1 9 ,2 0,2 9 ,3 0,3 1 ,3 6,3 7 ]
C4 7 6
C4 7 3
C4 7 4
C4 7 5
C2 1 0
D V D D [ 24 ]
3 .3 V [2 , 3, 8 ,1 1 ,1 3,1 4 ,1 5,1 7 ,1 8,1 9 ,2 0,2 2 ,2 3,2 6 ,2 8, 30 ,3 1 , 33 ,3 4 , 35 ]
1 .5 V [3 , 6, 8 ,9 ,1 0 , 20 ,2 6 , 28 ,3 1 , 33 ]
3 .3 V S [3 , 9 ,10 , 1 1 ,12 , 1 3 ,14 , 1 5 ,16 , 1 7 ,18 , 1 9 ,2 0, 2 3 ,2 4, 2 7 ,2 8, 2 9 ,3 0,3 1 ,3 6]
W240HU ALLTOP-C166N5-12205-L
W250HU 1-162-100561
B - 26 LAN (JMC251C), SATA HDD, ODD
Schematic Diagrams
USB 3.0 NEC, USB Charger

3. 3 V 3 3. V A 1. 0 5 V 3. 3 V A
L 63
. W/O U SB Cha rg er
RE /R F 1 0 /2 9
C 54 8 H C B 1 60 8 K F-1 2 1T 25 C 54 9 C 55 0 C 5 51
0. 1 u _1 0V _ X5 R _ 04 G_ D M0 _0 R 55 6 0 _ 04 U S B _P N 1_ A
0. 1 u_ 10 V _X 5 R _0 4 0. 1 u_ 1 0V _ X5 R _ 04 C5 5 2 C 5 53
0. 1 u_ 10 V _X 5 R _0 4 C 5 54 G_ D P 0_ 0 R 55 7 0 _ 04 U S B _P P 1 _A
0 . 1u _ 10 V _X 5R _0 4 5p _ 50 V _N P O_ 0 4
0 . 01 u_ 1 6V _ X7 R _ 04
C5 5 5
C 55 6
0 . 01 u _1 6V _ X7 R _ 04
C 55 7 C 55 8
C 55 9
0 . 01 u _1 6V _ X7 R _ 04 3 . 3V A USB C har ger c omp one nt s
0 . 01 u_ 1 6V _ X7 R _ 04 0. 0 1u _1 6 V_ X 7R _ 0 4 0 . 01 u _1 6V _ X7 R _ 04 V DD5 V C C _ T PS 2 5 40
17
C 5 61 C 5 64 80 mil U 43 80 mil
0. 0 1 u_ 16 V _X 7R _0 4 0. 0 1 u_ 16 V _X 7R _0 4 1 12
PPAD
C 56 0 C 5 62 C 56 3 C 5 65 IN O UT
0. 0 1u _1 6 V_ X 7R _ 0 4 0. 0 1u _ 16 V _X 7R _0 4 0. 0 1u _1 6 V_ X 7R _ 0 4 0 . 01 u_ 16 V _X 7 R _0 4 C 56 6 C 56 7 G _D M0_ 0 2 11 U S B _P N 1 _A
D M _O D M_I N
0. 1 u_ 10 V _X 5 R _0 4 G _D P 0_ 0 3 10 U S B _P P 1_ A
L13
E1 2
H1 1
K1 1
K1 2
P1 3
DP_ O D P _I N
D10
F 13
F 14
G3
L 10
L1 4
E 11
H 3
0 . 0 1u _1 6V _ X7 R _ 04
F3
G4
N4
N5
N6
P3
C4
C5
C6
C7
D5
C8
C9
D8
D9
E3
H4
D7
L9
E4
L5
L8
U4 4 4 14
I L I M_S E L GN D
V DD3 3
V DD 33
V D D33
V DD3 3
V DD3 3
V DD3 3
V DD 33
V DD3 3
V DD3 3
V DD 33
V DD3 3
V DD3 3
V DD1 0
V DD 10
V D D10
V DD1 0
V DD1 0
V DD1 0
V DD 10
V D D10
V DD1 0
V DD1 0
V DD1 0
V D D10
V DD1 0
V DD1 0
V DD 10
V DD1 0
V DD1 0
V DD1 0
U2 A V DD3 3
VD D33
VD D33
VD D10
VD D10
U3A V D D 33
R 56 0 *1 0K _ 04 5 16 R 56 1 *17 . 8K _ 1 %_ 04
P P ON VD D 5 R 58 2 *0 _0 4
E N/DS C I L I M0
6 15 R 56 3 *40 . 2K _ 0 4
B2 [ 2 7, 3 1, 3 2] D D _ON CT L 1 I L I M1
[ 14 ] C LK _ P C I E _U SB 3 0 B1 P E CL K P B6 7 9
S S TX 2 R 5 64 *1 0K _ 04
[ 1 4] C L K _P C I E _ U S B 30 # P E CL K N U 3T XD P2 VD D 5 CT L 2 NC
C 56 8 0 . 1u _ 10 V _X 5R _0 4 D 2 A6 S S TX 2 # R 5 65 *1 0K _ 04 A C _ I N 8 13 R 56 6 *0_ 0 4 G _ OC #
[ 1 4] P C I E _ R XP 2 _U SB 3 0 P E T XP U 3 TX D N 2 CT L 3 F A U LT #
[ 14 ] P C I E _R X N 2 _U SB 3 0 C 56 9 0 . 1u _ 10 V _X 5R _0 4 D 1 P E T XN U 2 D M2
N8 U 2 D M2
D
F2 P8 U2 DP 2 Q37 *TP S 2 54 0
[ 1 4] P C I E _ TX P 2_ U S B 30 F1 P E RX P U 2D P2 B8 G
S S RX 2 *MT N 7 00 2Z H S 3
[ 14 ] P C I E _T XN 2_ U S B 30 P E RX N U 3 R XD P2 [ 27 , 38 ] A C _I N #
M_ PQ FP16
S
3 . 3V A8 S S R X 2# 11 /19
U 3R X D N 2
H2 R 56 2
[ 17 , 22 , 2 4, 2 7] B U F _ P LT _R S T # K1 P E RS T B 10 K _0 4 CTL 1 CTL 2 CT L3 : 0 X 1-- ---> De dic ate d Cha rg in g P o rt , Aut o- de tec t
[ 1 5, 2 2, 2 4] P C I E _ W AK E # K2 PEW AKEB G1 4 G_ OC #
[ 14 ] P C I E C LK R Q2# P E C R E QB OC I 2B 3. 3 V
H1 3 CTL 1 CTL 2 CT L3 : 1 1 1- --- -> Ch ar g ing Do wn dtr ea m P or t, BC S pe c 1. 1
C
1 1 /0 1 A U X D E T_ R J2 OC I 1B
J1 A U XD E T H1 4 P P ON
D2 2 R 58 6 3 . 3V R 58 7 1 0K _ 04 CTL 1 CTL 2 CT L3 : X 1 0-- ---> S ta nd ar d Dow nstr ea m P or t, US B 2.0 Mo de .
H1 PSEL P P ON2 J1 4
[ 1 3] U S B 3 0_ S MI # S M IB P P ON1 CL OS E TO C O NN EC TO R
R B7 5 1S -4 0C 2 39 2K _ 1% _0 4
11 /0 1 1 0 /2 8 St uf f
A
C 57 1
P5
U S B _ S PI _ S C L K M2
P O N R S TB
U 3T XD P1
B 10
A 10
S S TX 1
S S TX 1 #
C 5 70
C 5 72
0 . 1 u_ 10 V _X 5 R _0 4
0 . 1 u_ 10 V _X 5 R _0 4
T XP 0 _R
T XN 0 _ R W / US B 3. 0, U SB C ha rg er
R A/ RB , US B 3. 0 c om po ne nt s,
U SB C ha rg er c om p on en ts , RH
Sheet 26 of 43
1 u _6 . 3V _ X5 R _ 04 U S B _ S PI _ C E # N 2 S P IS CK U 3 TX D N 1 N1 0 G_ D M0
3 .3 V R 5 93 47 K _0 4
U S B _ S PI _ S I
U S B _ S PI _ S O M1
N1 S P ICS B
SPISI
SPISO
U 2 D M1
U 2D P1
U 3 R XD P1
P 10
B 12
G_ D P 0
S S RX 1
W / US B 3. 0, W /o U SB C ha r ge r
R A/ RB , US B 3. 0 c om po ne nt s,
R E/ RF , RG USB 3.0 NEC, USB
uPD 720200
1 1/19 K1 3
K1 4
J1 3
G ND
G ND
U 3R X D N 1
A 12 S S R X 1#
W /o U S B3 .0 , US B Ch ar ge r R C/ RD , RE /R F, R G Charger
P4 G ND
G ND
RRE F
U 2A V S S
P 12 R 5 89
N1 2
1. 6 K _1 % _0 4
US B 3 .0/ PC H U SB 2.0 C o-l ayo ut
C1 4 N1 1
G ND U 2P V S S 1 0 /2 9
RG
D6
N1 4 U 3A V S S W/ o US B C ha rg er P ow er U S B 30 V C C
US B V CC R 5 58 0_ 0 6
M1 4 XT1
XT2 RH C 16 2 0 . 1u _ 16 V _Y 5 V _ 04
P6 U GN D W/ U SB C h ar ge r Po we r
C S EL
+
R 59 0 P 14 R 5 59 *0 _0 6 C 49 5 1 0 0u _6 . 3V _ B _B
G ND P 11 VC C _T P S 25 4 0
G ND P9
1 1 /0 5 1 0 0_ 04
A1 G ND P7 J _U S B3 _ 1
A2 G ND G ND P2
A3 G ND G ND P1 TX P 0_ R 9 G ND1
G ND G ND S S T X+ S H I E LD
S tandar d-A
A4 N1 3 1 G ND3
A5 G ND G ND N9 TX N 0 _R 8 V B US S H I E LD
A7 G ND G ND N7 U S B _P N 1 _A 4 3 U S B _P N 1 _A _ R 2 S S T X-
1 1/0 2
X 15 2 4. 0 0 0MH z / 16 pF / + 30 pp m A9 G ND G ND N3 4 D -
2 1 A1 1 G ND G ND M1 3 U S B _P P 1_ A L 64 1 2 U S B _P P 1 _A _ R 3 G ND
G ND G ND D +
A1 3
G ND G ND
M1 2 Diff. tr ace 90ohm SS R X1 6
S S RX +
C5 7 3 C 57 4 A1 4 M1 1 *W C M2 0 12 F 2S -S H OR T 7 G ND4
B3 G ND G ND M1 0 SS R X1 # 5 G ND_ D S H I E LD G ND2
2 0 p_ 50 V _N PO _0 4 2 0 p_ 50 V _N P O_0 4 B4 G ND G ND M9 S S RX - S H I E LD
B5 G ND G ND M8
B7 G ND G ND M7 R A/ RB U S B -09 E C E B -S D 0 01
B9 G ND G ND M6 P C B F o ot p ri nt = U S B C
- 19 00 5
B1 1 G ND G ND M5 G_ D M0 R 1 86 0_ 04
B1 3 G ND G ND M4 W 2 4 0H U: 6 -2 1 -B4 A 1 0 -0 0 9
B1 4 G ND G ND M3 G_ D P 0 R 1 93 0_ 04
C1 G ND G ND L1 2 /2n d: 6 -2 1 -B4 A 0 0 -0 0 9
C2 G ND G ND L1 1 R C/ RD W 2 5 0H UQ: 6 - 2 1- B4 A2 0 -0 0 9
C3 G ND G ND L7
C1 0 G ND G ND L6 G_ D M0 _0
G ND G ND [ 1 7] U SB _ P N 0 R 1 97 *0 _0 4
C1 1
G ND R 2 03 *0 _0 4 G_ D P 0_ 0
GN D
GN D
G ND
GN D
G ND
GN D
G ND
GN D
G ND
G ND
GN D
G ND
G ND
GN D
GN D
G ND
GN D
G ND
GN D
G ND
[ 1 7] U SB _ P P 0
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
PCH USB2.0
G9
H 8
C1 3
D3
D4
D1 1
D 12
E1
E2
E1 3
E1 4
F6
F7
F8
F9
F11
F12
G1
G2
G6
G7
G8
G1 2
G1 3
H6
H7
H9
H1 2
J4
J6
J7
J1 1
J 12
K3
K4
L4
C12
D13
D14
F4
G11
J3
J8
J9
L1
L2
L3
R 59 1 * 15 mi l _0 6 3. 3 V
NC 3
U GN D
*N C _0 4 512K bit KBC_SPI_*_R = 0.1"~0.5"
3 .3 V C5 7 5 0 . 1u _1 6 V_ Y 5 V _0 4
5V U4 5
5V 1. 5 V U S B _S P I _ V D D _ 1 8 5 U S B _ SP I _ S I _R R 59 4 47 _0 4 U S B _ SP I _ S I
2A C5 7 6 VD D SI
2 U S B _ SP I _ S O_ R
R 5 95 R 59 7 15 _1 %_ 0 4 U S B _ SP I _ S O
U4 6 1 u_ 6. 3 V _Y 5V _ 04 1 .0 5 V SO
10 K _0 4 R 5 96 5 6 R 5 98 1 K _0 4 U SB _ F LA S H 3 1 U S B _ SP I _ C E # _R R 59 9 15 _1 %_ 0 4 U S B _ SP I _ C E #
10 K _0 4
9
7
V IN
V IN
V C N TL
4
3A W P# CE #
6 U S B _ SP I _ S C L K_ R R 60 0 47 _0 4 U S B _ SP I _ S C L K
A U X D E T_ R P OK V OU T SC K
3 R 6 01 4 . 7K _ 04 U SB _ H OL D # 7 4
8 V OU T H O LD # V S S
EN C 5 80 MX 25 L5 1 21 E MC -2 0G
D
R 58 8 C 5 77 1 2 R 60 2 75 0_ 1 %_ 04 C5 7 8 C 57 9 [ 30 ] U S B V C C
Q4 6 GN D VFB [ 31 , 3 2] V D D 5
*0_ 0 4 [3 , 6 , 8, 9 , 10 , 20 , 28 , 31 , 3 3] 1 . 5V
G C5 8 1 1u _ 6. 3 V _Y 5 V _0 4 * 10 U _1 0 V _0 8 10 u_ 10 V _Y 5V _ 08 0 . 1u _1 6V _ Y 5 V _0 4
[1 5 , 27 , 31 ] S U S B # [ 2, 3 , 8, 1 1 ,1 3 , 14 , 15 , 17 , 18 , 1 9, 2 0, 2 2, 2 3 ,2 8 , 30 , 31 , 33 , 34 , 3 5] 3 . 3V
*MT N 7 00 2Z H S 3 AX6610 C 58 2 0 . 0 15 u_ 10 V _ X7 R _0 4 [ 2 0 ,2 3 , 30 , 31 , 33 , 34 , 3 5] 5 V
S
0 . 1u _1 6 V _Y 5 V _0 4
C 58 4
(15nF~ 48nF)
C 5 83
1 0 u_ 10 V _Y 5V _ 08 R 60 3
0 . 1u _1 6V _ Y 5 V _0 4
2 . 4 K_ 1 %_ 04
USB 3.0 NEC, USB Charger B - 27
Schematic Diagrams
KBC-ITE IT8518
K B C_ A V DD L1 9 VD D3 V D D3
H C B 1 0 0 5K F -12 1 T 20 RN1 1 MO DE L_I D RA RB
V D D3
. V D D3 2 . 2 K _8 P 4 R _ 0 4
C 2 22 C2 6 6 C2 1 1 C 26 4 C 2 56 S MC _ B A T 4 5 V 1. 0 1 0K X W 24 0H U
C2 3 4 C 23 3 C2 3 2 R 29 9 S MD _ B A T 3 6
0 . 1 u _1 6 V _ Y 5 V _ 04 10 u _ 10 V _ Y 5 V _ 0 8 0 . 1u _ 1 6V _ Y 5V _ 0 4 0 . 1 u_ 1 6 V _Y 5 V _0 4 0 . 1 u _1 6 V _ Y 5 V _ 04 2 7
W 25 0H UQ
0 . 1u _ 1 6V _ Y 5V _ 0 4 *0 . 1 u _1 6 V _ Y 5 V _ 04 *0 . 1 u_ 1 6 V _Y 5 V _0 4 1 0 0K _ 0 4 1 8
X 10K W 27 0H UQ
K B C_ W R E S E T # RN1 0 V D D3 V D D3
1 0 K _8 P 4 R _ 0 4 RA
L 21 HC B 10 0 5K F -12 1 T 20 E C_ V C C K B C _ A GN D C 23 8 B A T _ DE T 4 5 M OD E L_ I D R 29 2 1 0K _0 4
3. 3 V S . 3 6
AP_ KEY# R 29 3 *1 0 K _ 04
C2 5 2 1 J_KB1 24 0 . 1 u_ 1 6 V _Y 5 V _0 4 3 G_ D E T # 2 7
CC D_ DE T # 1 8
RB
127
0 . 1u _ 1 6V _ Y 5V _ 0 4 W 24 0HU /W 27 0HU J _K B 2 W25 0H U J _ KB1
11 4
1 21
11
26
92
74
50
3
U2 3 8 5 2 01 -2 4 05 1 *8 5 20 1 -2 40 5 1 11/02
VS TBY
VST BY
VST BY
VBAT
VCC
AVCC
VSTBY
VSTBY
VSTBY
10 58 K B -S I 0 4 K B -S I 0 4
[ 1 3 , 23 ] L P C _A D 0 9 L AD 0 K S I0 /S T B # 59 K B -S I 1 5 K B -S I 1 5 P CL K _ K B C R3 1 2 *1 0_ 0 4 P C LK _ K B C _R C2 4 6 *1 0 p _5 0 V _ N P O _0 6
[ 1 3 , 23 ] L P C _A D 1 8 L AD 1 K S I1 /A F D # 60 K B -S I 2 6 K B -S I 2 6
[ 1 3 , 23 ] L P C _A D 2 7 L AD 2 K S I2 /INIT # 61 K B -S I 3 8 K B -S I 3 8
[ 1 3 , 23 ] L P C _A D 3 P C LK _ K B C 13 L AD 3 K S I 3/ S LI N # 62 K B -S I 4 11 K B -S I 4 11 B A T_ V O LT C2 1 7 1 u _6 . 3 V _ Y 5 V _ 04
[ 1 7] P C L K _ K B C 6 L P C CL K KSI4 63 K B -S I 5 12 K B -S I 5 12
[ 1 3, 2 3 ] L P C _ F R A ME # 5 L F R A ME # KSI5 64 K B -S I 6 14 K B -S I 6 14
[ 13 , 2 3 ] S E R I R Q
22 S E RIRQ LPC K/B MATRIX KSI6 65 K B -S I 7 15 K B -S I 7 15 A C_ IN# C2 5 8 0 . 1 u_ 1 6V _Y 5V _0 4
[ 1 7 , 2 2, 2 4 , 2 6] B U F _ P L T_ R S T# L P C R S T # / W U I 4 / GP D 2 ( P U ) KSI7
K B C _W RE S E T # 14 36 K B -S O 0 1 K B -S O0 1
W R ST# K S O 0/ P D 0 37 K B -S O 1 2 K B -S O1 2
1 26 K S O 1/ P D 1 38 K B -S O 2 3 K B -S O2 3
[ 1 8 ] GA 2 0 4 G A 2 0/ G P B 5 K S O 2/ P D 2 39 K B -S O 3 7 K B -S O3 7
[ 26 , 3 8 ] A C _ I N # 16 K B R S T #/ GP B 6 ( P U ) K S O 3/ P D 3 40 9 9
K B -S O 4 K B -S O4
[ 28 ] L E D _ A C I N 20 P W U R E Q # / GP C 7( P U ) K S O 4/ P D 4 41 K B -S O 5 10 K B -S O5 10
[ 15 , 1 7 ] A C _ P R E S E NT *0 _ 0 4 R 30 0
*0 _ 0 4 R 30 3 L 8 0 LL A T / GP E 7 ( P U ) K S O 5/ P D 5 42 K B -S O 6 13 K B -S O6 13
[ 1 5 ] P M_ P C H _ P W R O K
[ 18 ] S M I #
23
15 E C S CI# /G P D3 ( P U )
K S O 6/ P D 6
K S O 7/ P D 7
43
44
K B -S O 7 16
17
K B -S O7 16
17
V DD 3 Co-lay SPI ROM
K B -S O 8 K B -S O8
[ 18 ] S C I # E C S MI # / G P D 4 ( P U ) K S O8 / A C K # 45 K B -S O 9 18 K B -S O9 18 U 31
K S O 9/ B U S Y 46 K B -S O 10 19 K B -S O 10 19 8 5 K B C_ S P I_ S I_ R
76 DAC K S O 1 0/ P E 51 K B -S O 11 20 K B -S O 11 20 VD D SI
[ 2 2, 2 8 ] W L A N _ E N 77 G PJ 0 K S O1 1 / E R R # 52 21 21 2
Sheet 27 of 43 [ 29 ] K B C _M U T E #
[ 1 3 ] ME _W E
[ 3 0] C P U _F A N
78
79
80
G
D
D
PJ 1
A C 2 / GP
A C 3 / GP
J2
J3
K S O1 2 / S LC T
K S O1 3
K S O1 4
53
54
55
K B -S O
K B -S O
K B -S O
K B -S O
12
13
14
15
22
23
24
K B -S O 12
K B -S O 13
K B -S O 14
K B -S O 15
22
23
24
K B C_ F L A S H 3
W P#
SO
CE #
1
K B C _ S P I _ S O_ R
K B C_ S P I_ CE # _ R
IT8518
KBC-ITE IT8518
[3 0 ] W E B _ W W W # 81 D A C 4 / GP J4 K S O1 5 6 K B C_ S P I_ S CL K _ R
D A C 5 / GP J5 S CK
K B C _ H O LD # 7 4
B A T _ DE T 66
ADC FLASH 10 0 H OL D # VSS
[ 3 8 ] B A T _ DE T B A T _ V OL T 67 AD C 0 / GP I0 F L F R A ME # / GP G 2 10 1 K B C_ S P I_ C E # 3 G_ P W R _E N [ 2 3]
[ 3 8] B A T_ V O LT M X 25 L 3 20 6 E
AP_ KEY # 68 AD C 1 / GP I1 F L A D0 /S C E # 10 2 K B C_ S P I_ S I P C B F o ot p ri nt = A C A -S P I -0 0 4-T 0 3
[3 0 ] AP_ KEY # 69 AD C 2 / GP I2 F L A D 1/ S I 10 3 K B C_ S P I_ S O
[ 2 ] T H E R M_ V OL T 70 AD C 3 / GP I3 F L A D2 /S O 10 4
[ 3 8 ] T OT A L _C U R AD C 4 / GP I4 F L A D 3 / GP G 6 V C H G-S E L [ 3 8 ] 11/0 1
3 G_ D E T# 71 10 5 K B C _ S P I _ S C LK
[ 2 3 ] 3 G_ D E T # 72 AD C 5 / GP I5 F L CL K /S CK 10 6
C C D _ D E T#
[ 2 3] C C D _ D E T # M OD E L_ I D 73 AD C 6 / GP I6 ( P D )F LR S T #/ W U I 7 / GP G 0/ T M CC D_ E N [ 23 ]
AD C 7 / GP I7 V DD 3
GPIO 56
S M C_ B A T 1 10 SMBUS ( P D )K S O1 6 / GP C 3 57 S U S B # [ 15 , 2 6 , 31 ]
C 2 88
[ 38 ] S M C _ B A T S M D_ B A T 1 11 SM C L K 0 / GP B 3 ( P D )K S O1 7 / GP C 5 S U S C # [ 1 5, 3 3 ] 0 . 1u _ 1 6V _ Y 5V _ 0 4 8 Mb it KBC_SPI_*_R = 0.1"~0.5"
[ 38 ] S M D _ B A T 1 15 SM D A T 0 / GP B 4 93
11/ 03 SM C L K 1 / GP C 1 ( PD )GP H 0/ I D 0 S U S _P W R _ A C K [ 1 5 ]
R 6 06 0 _0 4 1 16 94 U 30
[ 3 , 18 ] H _P E C I 1 17 SM D A T 1 / GP C 2 ( PD )GP H 1/ I D 1 95 B T _ E N [ 2 2 , 28 ] 8 5 K B C_ S P I_ S I_ R R 3 66 47 _ 0 4 K B C_ S P I _ S I
[ 2 , 1 4] S MC _ C P U _ T H E R M R 3 28 *0 _ 0 4 1 18 SM C L K 2 / GP F 6 ( P U ) ( PD )GP H 2/ I D 2 96 B K L _ E N [1 1 ] VD D SI 2 K B C _ S P I _ S O_ R R 3 55 15 _ 1 %_ 0 4 K B C_ S P I _ S O
[ 2 , 1 4] S MD _ C P U _ T H E R M SM D A T 2 / GP F 7 ( P U ) ( PD )GP H 3/ I D 3 97 H S P I _C E # [ 1 3] SO 1 K B C_ S P I_ CE # _ R K B C_ S P I _ C E #
R 3 42 15 _ 1 %_ 0 4
( PD )GP H 4/ I D 4 98 H S P I _S C L K [ 1 3] R3 6 0 1 K _ 0 4 CE # 6 K B C_ S P I_ S CL K _ R R 3 59 47 _ 0 4 K B C_ S P I _ S C LK
L C D _B R I GH T N E S S 24
PWM ( PD )GP H 5/ I D 5 99 H S P I _M S O [ 1 3 ] K B C_ F L A S H 3 S CK
25 PW M0 / GP A 0 ( PU ) ( PD )GP H 6/ I D 6 10 7 H S P I _M S I [ 1 3 ] W P#
[ 2 9] K B C _ B E E P 28 PW M1 / GP A 1 ( PU ) ( PD )GP G 1/ I D 7 D D _ ON [ 26 , 3 1 , 32 ]
[ 2 8 ] LE D _ S C R OL L # PW M2 / GP A 2 ( PU )
29 R 3 4 6 4 . 7 K _ 04
LOW ACTIVE [ 2 8 ] L E D _ N U M# 30 PW M3 / GP A 3 ( PU ) EXT GPIO 82 K B C _ H O LD # 7 4 K B C_ S P I_ S I C 30 3 *3 3p _ 5 0V _N P O_ 0 4
[2 8 ] L E D_ CA P # 31 PW M4 / GP A 4 ( PU ) ( P D )E G A D / G P E 1 83 H OL D # VSS
R 3 06 *0 _ 0 4 K B C_ S P I_ S O C 29 0 *3 3p _ 5 0V _N P O_ 0 4
[ 28 ] L E D _B A T _ C H G 32 PW M5 / GP A 5 ( PU ) ( P D )E GC S # / G P E 2 84 OC P P E # [ 1 8] K B C_ S P I_ CE #
R 3 15 *0 _ 0 4 * S S T 2 5V F 0 8 0 B S O8 C 28 4 *3 3p _ 5 0V _N P O_ 0 4
HIGH ACTIVE [ 2 8] LE D _ B A T_ F U LL 34 PW M6 / GP A 6 ( PU ) ( P D )E GC L K / G P E 3
10/29 K B C_ S P I_ S CL K C 29 7 *3 3p _ 5 0V _N P O_ 0 4
[ 2 8] LE D _ P W R PW M7 / GP A 7 ( PU ) 11/04
WAKE UP 35
80 C L K 85
PS/2 ( P D )W U I 5 / G P E 5 17 R S MR S T # [ 1 5 ]
[ 22 ] 8 0 C L K 86 PS 2C LK 0 / G PF0 ( PU ) ( P D )L P C P D# / W U I 6 / G P E 6 K B C _R S T # [ 1 8 ]
[ 22 , 2 8 ] B T _D E T # 8 0 P OR T _ D E T # 87 PS 2D A T0 / G PF1 ( PU )
R 32 0 0 _0 4
[ 2 2 ] 3I N 1 88 PS 2C LK 1 / G PF2 ( PU ) PWM/COUNTER 47
[ 3 0 ] W E B _ E MA I L # 89 PS 2D A T1 / G PF3 ( PU ) ( P D )T A C H 0 / GP D 6 48 C P U _ F A N S E N [ 3 0]
[ 30 ] T P _ C L K 90 PS 2C LK 2 / G PF4 ( PU ) ( P D )T A C H 1 / GP D 7 H _ P R O C H OT _ E C [ 3 ]
R3 3 0 0_ 0 4
[ 30 ] T P _ D A T A PS 2D A T2 / G PF5 ( PU ) 12 0 P MP C H _ P W R OK _ R R3 3 6 *0 _ 0 4 P M _P C H _ P W R OK [ 1 5 ]
( P D )T MR I 0/ W U I 2 / GP C 4 12 4 V C OR E _ O N [ 3 6 ]
1 25
WAKE UP ( P D )T MR I 1/ W U I 3 / GP C 6 A L L _S Y S _ P W R G D [ 1 1 , 1 5, 3 6 ]
[ 2 3 ] 3G _ E N P W RS W /G P E 4 ( P U )
18
CIR 11 9 R 3 29 0 _0 4
[ 3 1] P W R _ S W # 21 R I 1 #/ W U I 0 / GP D 0( P U ) ( P D )C R X / GP C 0 12 3 P ME # _ R C E L L _C ON TR OL [ 3 8 ]
R 3 35 *0 _ 04
[ 1 1 , 30 ] L I D _ S W # R I 2 #/ W U I 1 / GP D 1( P U ) ( P D )C TX / G P B 2 R 3 31 0 _0 4 P M E # [ 17 ]
L A N _ P C I E _W A K E # [ 24 ]
33 GP INTERRUPT LPC/WAKE UP 19
[1 5 ] P W R_ B T N# G I NT / GP D 5 ( P U ) ( P D )L 80 H LA T / G P E 0 S W I# [1 5 ]
11 2
( P D ) R I N G # / P W R F A I L # / L P C R S T# / G P B 7 C H G_ E N [ 38 ]
1 08 UART
[ 2 2, 2 8 ] W L A N _ L E D # 1 09 R X D / GP B 0( P U ) CLOCK 2 CK 3 2 K E *0 _ 04 R3 2 6
AVSS
[ 2 2 ] W L A N _ D E T# N B _E N A V D D [ 1 1, 1 6 ]
VS S
T X D/ G P B 1 ( P U ) C K 3 2K E 12 8
VSS
VSS
VSS
VSS
VSS
VSS
CK 3 2 K V DD 3
C K 3 2K
I T8 5 1 8E R3 2 7 *1 0 M_ 0 6 J _8 0 D E B U G1
1
27
91
113
75
12
49
1 22
R3 5 3
X4 *M C -1 4 6_ 3 2 . 76 8 K H z 1 3 IN1
2 1 00 K _ 0 4
C 2 50 0 . 1 u _1 6 V _ Y 5 V _ 04 E C _V S S 1 4 8 0C LK
2 3 3 8 0D E T #
4
X5 * C M -20 0 S _ 32 . 7 6 8K H z 5
R 33 3 1 4 *8 8 26 6 -0 50 0 1
2 3
NC 2 * NC_ 0 4 0 _ 04 C 26 2 11/29
C2 6 5 *1 5 p _5 0 V _ N P O _0 4
*1 5 p _5 0 V _ N P O_ 0 4
R2 8 8 *1 0 m li _ 0 4 L C D _B R I GH T N E S S
[1 1 ] B RIG HT NE S S
K B C _A G N D MC-146 & CM200S
C2 1 9 *0 . 1u _ 1 0V _ X 5 R _ 0 4
Co-layout [ 13 , 2 2 , 24 , 3 1 , 32 , 3 8 ] V D D 3
[ 3 , 9 , 1 0, 1 1 , 1 2, 1 3 , 1 4, 1 5 , 1 6, 1 7 , 1 8, 19 , 2 0, 23 , 2 4 , 25 , 2 8 , 29 , 3 0 , 31 , 3 6 ] 3. 3 V S
B - 28 KBC-ITE IT8518
Schematic Diagrams
LED, MDC, BT
Bluetooth(Port8)
MJ_MDC1
20 MIL 1 .5 V
12 11 3V _B T
R 51 3 * 0 _0 4
2 1 J _ BT1
3. 3V
1
J _M D C 1
2 3. 3 V 3. 3 V
P or t 11 1
2
R 51 2 * 0 _0 4
3 GN D RES E R V E D 4 [ 1 7 ] U S B _ P N 11 3
[ 1 3 ] H D A _ S DO _M D C 5
7
A za l ai _ S DO
GN D
RES E R V E D
3 . 3V M a ni / a u x
6
8
MD C_ 3 . 3 V 10mil L 4 1 *2 8 m li _ 06
[1 7 ] US B _ P P 1 1
[ 2 2, 2 7 ] B T _D E T # B T _ E N#
4
5
[ 1 3 ] H D A _ S Y N C_ MD C 9 A za l ai _ S Y N C GN D 10 6
R3 2 2 *3 3 _ 04 H D A _ S D I N 1_ R R 32 3
[ 1 3 ] H D A _ S DI N 1 11 A za l ai _ S DI GN D 12 *8 7 2 12 -0 6 G0
[ 1 3 ] H D A _ R S T # _M D C A za l ai _ R S T # A za l ai _ B C L K H D A _ B I T C L K _ MD C [ 1 3]
*1 0 K _ 04
*8 8 0 18 -1 2 0G C 2 37 C 2 55
B T _E N #
* 0 . 1u _ 1 6V _ Y 5 V _ 0 4 *2 2p _ 5 0V _ N P O_ 0 4
D
Q 24 C2 5 9
BT_ EN G *M T N 7 0 02 Z H S 3 3 . 3V 3 V_ BT
R 4 73
GN D 50 mil 50 mi l
*1 8 0p _ 5 0V _ N P O _ 04
S
1 0/ 29
*2 8 m li _ 0 6
C 4 64
*1 0u _ 6 . 3V _ X 5 R _ 0 6
3 .3 V S 3 .3 V S
L E D _A C I N [ 2 7 ] L E D _B A T_ C H G [ 2 7 ]
Sheet 28 of 43
LED 3 . 3V S 3. 3 V S 3 . 3V S 3. 3V S L E D_ P W R [ 27 ] L E D _ B A T _ F U L L [ 27 ]
LED, MDC, BT
R6 R7
R 3 R4 R 5 2 20 _ 04 22 0 _ 04
2 2 0_ 0 4 22 0 _0 4 2 2 0 _0 4
POWER ON BAT LED
BT WLAN LED
3
LED 1 3 LED
D 1 D 14 D 15
HDD/ODD NUM CAPS SCROLL
A
A
R2 2 4
SG
SG
SG
LED LOCK LOCK LOCK
Y
D3 D4 D5 K P B -3 0 2 5Y S GC K P B -30 2 5 Y S GC K P B -30 2 5 Y S G C
22 0 _0 4
LED LED LED
4
R Y - S P 17 0 Y G 3 4 - 5 M
R Y - S P 1 7 0 Y G 3 4- 5M
R 1
R Y - S P 17 0 Y G 3 4 - 5M
A
W L A N _ L E D # [ 2 2 , 27 ]
D2
C
C
C
*1 0 mi l _0 4 R 36 2 R3 6 1 R 36 3 R3 6 4
B
R Y -S P 17 0 Y G 3 4 - 5 M
W LA N _ E N [ 2 2 , 2 7]
2 2 0_ 0 4 2 20 _ 0 4 2 2 0_ 0 4 2 20 _ 0 4
Q3
C
*D TC 11 4 E UA
E
LE D _ N U M # [ 27 ] L E D _C A P # [ 2 7] L E D _ S C R OL L # [ 2 7 ]
S A TA _ L E D# [ 1 3 ]
C
6-52-52001-027 6-52-52001-027 6-5 2-5 20 01-02 7
B B T_ E N
B T_ E N [ 2 2, 2 7 ]
6 -52 -5 2001-027 Q1
DT C1 1 4 E UA [ 3 , 6, 8 , 9 , 1 0, 2 0 , 2 6, 3 1 , 3 3] 1. 5 V
[ 2 , 3 , 8 , 11 , 1 3, 14 , 1 5, 17 , 1 8, 19 , 2 0, 22 , 2 3, 2 6 , 3 0, 3 1 , 3 3, 3 4 , 3 5] 3. 3 V
E
[ 3, 9 , 1 0 , 11 , 1 2 , 13 , 1 4, 15 , 1 6, 17 , 1 8, 19 , 2 0, 23 , 2 4, 2 5 , 2 7, 2 9 , 3 0, 3 1 , 3 6] 3. 3 V S
H1 5 H2 4 H1 1
M2 M7 M6 M1 M8 2 9 2 9 2 9
M-M A RK 1 M -MA R K 1 M-MA R K 1 M-M A R K 1 M -MA R K 1 3 8 3 8 3 8
H1 2 H 10 4 1 7 4 1 7 4 1 7
H 6 _ 3 D 4 _4 H 6_ 3 D 4 _ 4 5 6 5 6 5 6
MT H 3 1 5 D1 11 MT H 3 1 5 D 1 1 1 MT H 31 5 D 1 1 1
H3 H4
C 1 11 D 11 1 N C 1 1 1D 1 11 N
M5 M4 M3 H5 H6 H1 3
M-MA R K 1 M-M A R K 1 M -MA R K 1 2 9 2 9 2 9
3 8 3 8 3 J _ TP 1
4 1 7 4 1 7 4 1
5 6 5 6 5 6 1 LE D _ PW R
2 LE D _ A CIN
3 LE D _ B A T _F U LL
MT H 3 1 5 D1 11 MT H 3 1 5 D 1 1 1 MT H 31 5 D 1 1 1
H1 7 H 20 H 18 H 14 4 LE D _ B A T _C HG
5
H 6 _ 0 D3 _7 S1 S 2 H 4_ 7 B 6 _0 D 3_ 7 H 4 _7 B 6 _ 0D 3_ 7H 6_ 3 D 4 _ 4
S MD 80 X 8 0 S MD 8 0 X 80 H9 H7 H2 5 6
2 9 2 9 2 9 *8 5 20 1 -06 0 5 1
3 8 3 8 3 8
1
4 1 7 4 1 7 4 1 7 G ND
5 6 5 6 5 6
1
MT H 3 1 5 D1 11 MT H 3 1 5 D 1 1 1 MT H 31 5 D 1 1 1
H2 3 H8 H 1 H2 H2 1 H 19 H2 2 H1 6
C6 7 D6 7 C 6 7 D6 7 C 1 11 D 11 1 N C 1 1 1D 1 11 N H 4 _ 0 B 7_ 0 D 3 _ 7 H 4_ 0 B 7 _0 D 3 _ 7 2 9 2 9
3 8 3 8
4 1 7 4 1 7
5 6 5 6
MT H 3 1 5 D1 11 MT H 31 5 D 1 1 1
LED, MDC, BT B - 29
Schematic Diagrams
Audio Codec ALC269
7
5
C
o
m
p
o
n
e
n
t
.
AUDIO CODEC
R5 2 7 * 0_ 0 4
ALC269 VB 1 . 5V S
DV D D_ IO P V DD1 _ 2 5 VS
La yo ut N ot e:
VT1802P 3 .3 V S _ A UD
R5 2 9 0 _ 04 R5 1 0 *2 8 mi l _0 6 Ve ry cl os e t o Au di o C od ec
C 51 3 C 29 9 C4 9 8 C2 7 1
10 u _ 10 V _ Y 5 V _ 0 8 0 . 1 u _1 6 V _ Y 5 V _ 04 10 u _ 10 V _ Y 5 V _ 0 8 0 . 1 u_ 1 6 V _Y 5 V _0 4
3 . 3V S 3 .3 V S _ A UD
R 5 67 0 _0 4 C 4 99 C2 7 0
*1 0 u_ 1 0V _Y 5V _0 8 0 . 1u _ 1 6V _Y 5V _0 4 5 VS_ AU D
C2 8 1 C 28 0 C 2 83 L 40 5 VS
H C B 1 0 0 5K F -12 1 T 20
0 . 1u _ 1 6V _ Y 5V _ 0 4 1 0 u_ 1 0 V _Y 5 V _0 8 0 . 1 u _1 6 V _ Y 5 V _ 04 1 2
C 4 97 C4 9 6 C 51 0 C 5 09 C4 9 4
5 VS L39
0. 1 u _ 16 V _ Y 5 V _ 0 4 1 0u _ 1 0V _ Y 5V _ 0 8 0 . 1 u_ 1 6 V _Y 5 V _0 4 1 0 u _1 0 V _ Y 5 V _ 0 8 1u _ 6 . 3V _ Y 5V _ 0 4 H C B 1 6 08 K F -1 2 1 T2 5
E A P D _M OD E C
D2 1
A
* R B 7 5 1 S -40 C 2
.
R 51 8
HD A _ RS T # C A A UD G AU DG C 50 3 0 . 1 u_ 1 6 V _Y 5 V _0 4
46
25
38
[ 13 ] H D A _ R S T #
39
1
9
D1 8 R B 7 51 S -4 0 C 2 1 0 K _0 4 U2 9
D VDD 1
D V D D -I O
PVD D1
PVDD 2
AVD D1
AVDD 2
C A P D# 4 13 S E NS E _ A R 36 9 2 0 K _1 % _ 04 M IC_ S E NS E C 50 2 0 . 1 u_ 1 6 V _Y 5 V _0 4
[ 27 ] K B C _ MU TE # MI C _ S E N S E [ 3 0 ]
D1 9 R B 7 51 S -4 0 C 2 PD# S en s e A
14 LI N E 2 -L R 36 8 3 9 . 2K _ 1 % _0 4 H P _S E N S E
40 L I N E 2 -L 15 HP _ S E N S E [3 0 ]
S P K OU T L+ LI N E 2 -R
S P K OU T L- 41 S P K -L + L I N E 2 -R
D
S P K -L - 16 MI C 2 _ L A U DG
Q 32 44 M I C 2 -L 17 MI C 2 _ R
G [ 30 ] S P K O U T R - 45 S P K -R - MI C 2 -R
5 VS R 51 4 *1 0 0K _ 0 4 * MT N 7 0 0 2Z H S 3 ALC269 20K_1%_04
[ 3 0] S P K OU TR + S P K -R + 18 S E N S E -B
EMI Require
Sheet 29 of 43
D
47 S en s e -B
S
Q 27
E A P D _ M OD E
S P DIF O 48 S P DIF C 2 /E A P D 19 JD R E F
VT1802
R 52 3
P 5. 1K_1%_04
20 K _ 1 %_ 0 4
HD A _ RS T # G *B S S 1 3 8_ N L S P DIF O J DRE F 20 MON O-O U T C5 1 2 *1 0 0 p_ 5 0 V _N P O_ 0 4
M ON O-OU T
Audio Codec D M I C -D A T 2
3 GP I O 0 21
S
D M I C -C LK MI C 1 -L _ R C 30 6 4 . 7 u_ 6 . 3 V _ X5 R _ 0 6 MI C 1 _ L A UD G
GP I O 1 M I C 1 -L 22 MI C 1 -R _R C 30 7 4 . 7 u_ 6 . 3 V _ X5 R _ 0 6 MI C 1 _ R
MI C 1 -R
ALC269 5
DIGITAL ANALOG L I N E 1 -L
23
24
LI N E 1 -L
LI N E 1 -R C3 0 1 0 . 1 u _1 6 V _ Y 5 V _ 04
Closed to SB. [ 1 3 ] H D A _S D OU T C2 9 1 2 2 p_ 5 0 V _N P O_ 0 4
6
S D A T A -O U T L I N E 1 -R
27 V R E F -A L C 26 9 C3 0 4 2 . 2 u _6 . 3 V _ X5 R _0 6
[ 1 3 ] H D A _B I TC L K B I T -C L K V RE F
Q2 5
R 35 4 33 _ 0 4 A Z _ S D IN0 _ R 8 28 LD O_ C A P ALC269 2.2u; VT1802P 10u
MT N 7 0 0 2Z H S 3 [ 13 ] H D A _ S D I N 0 S D A T A -I N LD O_ C A P 30 MI C 1 -V R E F O-R
D S A Z _ S Y N C _R 10 M I C 1 -V R E F O-R 29 MI C 2 -V R E F O C2 9 8 2 . 2 u _6 . 3 V _ X5 R _0 6
[1 3 ] HD A _ S Y N C SYN C MI C 2- V R E F O
H D A _ R S T# 11
RE S E T # H P -O U T -L
32 H E A D P H O N E -L
H E A D P H ON E -L [ 30 ] ALC269 2.2u
33 H E A D P H O N E -R
3 . 3V S H P -OU T -R H E A D P H ON E -R [ 3 0 ] VT1802P NC
G
B E E P _R 12
MI C 1 - V R E F O - L
A U DG
PCBEEP 35 C B N - A L2 6 9 C2 7 2 2 . 2 u_ 6 . 3 V _X 5 R _ 0 6
CB N
36 C B P -A L C 2 6 9
P VSS1
D VSS2
AVSS 2
CB P
PVSS2
AVSS1
34 OP V E E -A L C 26 9 L2 4
GN D
D 13 C 3 09 OP V E E F C M 10 0 5 K F -12 1 T 03 J _ SPKL 1
B A T 5 4 CW G H C2 7 9 S P K O U T L+ 1 2 S P K OU TL + _ L
1 A 1u _ 6 . 3V _ Y 5V _ 0 4 1
[ 27 ] K B C _B E E P 2
43
49
26
37
31
C 3 BEEP B E E P _C
42
R3 6 7 4 7K _ 0 4 A LC 26 9 Q-V B 5-G R C 2 93 C2 9 5
2 A 2 . 2 u_ 6 . 3 V _X 5 R _ 0 6 85 2 0 4-0 2 0 01
[ 13 ] H D A _ S P K R
FOR VOLUMN * 1 u_ 6 . 3 V _Y 5 V _0 4 *1 8 0p _ 5 0V _ N P O_ 0 4
R3 6 5 C 3 08 MI C 1-V R E F O -L
ADJUST A UD G S P K O U T L- 17/16 2 S P K OU TL -_ L
4. 7 K _ 0 4 10 0 p _5 0 V _ N P O _0 4 A U DG J_SPKL1
MI C 2 -V R E F O R 13 0 4. 7 K _ 0 4 F C M1 0 05 K F -1 2 1T 0 3 C2 8 9 2 1
J _ I N T MI C 1 L23
I N T _ MI C R 12 8 1K _ 0 4 *1 8 0p _ 5 0V _ N P O_ 0 4
1
2
C 1 18
8 8 2 66 -0 2 00 1
6 8 0 p_ 5 0 V _X 7 R _ 0 4 J_INTMIC1
2 1
3 .3 VS
Headphone Anti-Pop Circuit
R130 C118
R 5 68
AL269 4.7K_04 AL269 680p
H E A D P H ON E - L
H E A D P H ON E - R
VT1802P 2.2K_04 VT1802P 330p
* 2 20 K _ 0 4
3.3 VS_ AUD
S
E A P D _ MO D E G Q 39 Q4 0 MI C 1 _L R3 4 3 1K _ 0 4
MI C 1 -L [ 3 0 ]
D
Q 38 *2 N 7 0 02 W *2 N 70 0 2 W
* A O3 4 1 5 MI C 1 _R R3 5 1 1K _ 0 4
G G MI C 1 -R [ 3 0]
5V S
D
MI C 1 -V R E F O -R R 3 5 0 2. 2 K _ 0 4
S
20 ms R 5 69 R5 7 0 R5 7 1 MI C 1 -V R E F O -L R 3 4 5 2. 2 K _ 0 4
* 4 . 7K _ 0 4
*1 0 K _0 4 *1 0 K _ 04
AZ_RST# AUD G
R343 & R351 R345 & R350
AL269 1K_04 AL269 2.2K_04

PD# C 53 8
* 10 u _ 6. 3 V _ X 5R _ 06
VT1802P 75_04 VT1802P 4.7K_04
C5 1 1 4 . 7 u_ 6 . 3 V _X 5 R _ 0 6 M I C 2 _L
Spe a ke r w ire le ngth l e ss tha n 8 00 0mi ls , I t don't ne e d LC Fi lte r. AUD G I N T _M I C C5 1 4 4 . 7 u_ 6 . 3 V _X 5 R _ 0 6 M I C 2 _R
SPKO UTR+ ,R- ,L+ ,L- Tra ce wi dth
Spe a ke r 4 ohm- -- --- > 40 mil s 1 . 5 V S [ 1 9 , 3 1]
3 . 3 V S [ 3 , 9 , 1 0, 1 1 , 1 2, 1 3 , 1 4, 1 5 , 1 6, 17 , 1 8 , 19 , 2 0 , 23 , 2 4 , 25 , 2 7 , 28 , 3 0 , 3 1, 3 6 ]
Spe a ke r 8 ohm- -- --- > 20 mil s 5 V S [ 11 , 1 2 , 19 , 2 0 , 25 , 3 0 , 31 , 3 6 , 37 ]
B - 30 Audio Codec ALC269
Schematic Diagrams
USB, Fan, TP, Multi-Conn

USB 2.0 FAN CONTROL
U3 8
F O N# 1 8
2 F ON G ND 7
5 VS 3 VIN G ND 6
5V S _F A N V OU T G ND
4 5
[2 7 ] CP U _ F AN VSET G ND
80 mil A X 99 5 S A
U SBVC C
+
C 48 8
1 0 0u _ 6 . 3V _ B _ B
C 94
0 . 1 u _1 6 V _Y 5 V _0 4
Port 1
5 VS 5V S _ F A N
J_ F A N 1
J _ US B _ 1 C2 0 5 1 JFAN
R1 0 7 *0 _ 0 4 1 C 45 6 2
3
V+ 0 . 1u _ 16 V _ Y 5 V _ 0 4 3
4 3 A U S B _ PN1 _ R 2 1 0 u_ 6 . 3 V _X 5 R _ 0 6 8 5 20 5 -03 7 0 1
[ 1 7] U S B _ P N1 DA T A _ L 1
1 2 A U S B _ P P 1_ R 3
[ 1 7] U S B _ P P 1 DA T A _ H
L13 *W C M2 0 12 F 2 S -S H O R T
G ND 2
G ND 4
R1 1 3 *0 _ 0 4 4
GN D 1
GN D 3
GN D [ 2 7] C P U _ F A N S E N
3 1 7 D E 0 4P S A 7A 2 C 3. 3 V S R 20 2 4 . 7K _0 4
G ND1
GN D 2
G ND3
GN D 4
CO-LAY USB 3.0 J_USB2
W24 0HU
W25 0HU
31 7DE0 4PSA 7A 2C
1- 284- 8002 81 -1
CLICK B'd CONN Sheet 30 of 43
USB, Fan, TP,
US B V CC 5 V S _ TP
5 VS
R 13 1 *2 8 mi l _ 06 Multi-Conn
L62 C 1 13
G_ U S B V C C H C B 1 6 08 K F -1 2 1T 2 5 R 12 9 R 12 7
U4 0 100 MIL 1 u _ 6. 3 V _ Y 5 V _ 0 4
R5 2 4 *0 _0 4 F L G# 5 6 J _ TP2 1 0 K _ 04 1 0 K _ 04
[ 1 7 ] U S B _ OC # 01 F LG # V O U T 1
2 7 C 49 2 C 4 93 C 49 1 1
5V V IN1 V O UT 2 2 TP _ D A TA [ 2 7 ]
C5 0 1 0 . 1 u_ 1 6 V _Y 5V _0 4 3 8 0 . 1 u_ 1 6 V _Y 5V _0 4 *0 . 1u _ 1 6V _ Y 5V _ 0 4 1 0 u_ 6 . 3V _X 5 R _ 0 6 3 TP _ C L K [ 2 7 ]
V IN2 V O UT 3 4
C 11 4 C 11 5
4 1 8 5 2 01 -0 4 05 1
[ 3 1 , 3 3] D D _ ON # E N# G ND
4 7 p_ 5 0 V _N P O_ 0 4 4 7 p _5 0 V _N P O_ 0 4
R T 9 7 15 B GS
If system has AP ON function, uses J_SW1

Audio B'd CONN POWER SWITCH B'd CONN If system has no AP ON function, uses J_SW2
3 . 3V S 3 .3 V
1.1A 60mils CLOSE TO J_SW1
5V C2 2 3 0 . 0 1 u_ 1 6V _ X 7 R _ 0 4 3. 3 V S 3 .3 V
C2 9 C 27 J _ SW 1
J _ A U D I O1 A P _K E Y #
A P _ K E Y # [ 2 7] 1
20 mi l
1 0 . 0 1u _ 1 6V _ X 7 R _ 04 0. 0 1 u _1 6 V _ X7 R _ 0 4 2 M_ B T N #
[ 2 9] M I C 1 -R 2 3 W EB_ W W W #
[ 2 9] M I C 1 -L
D
3 4 W E B _ E MA I L #
R 33 9 2 2 0_ 0 4 H E A D P H ON E -R R 4 J _ SW 2 Q9 5 LI D _ S W #
[ 2 9 ] H E A D P H O N E -R
[ 2 9 ] H E A D P H O N E -L R 34 0 2 2 0_ 0 4 H E A D P H ON E -LL 5 20 mi l G * MT N 7 0 02 Z H S 3
6
M I C _ S E NS E 6 1 7 AP_ KEY#
[ 29 ] M I C _ S E N S E 7 2 8
S
SPK_ H P# M_ B T N #
8 3 M_ B TN # [ 31 ]
H P _S E N S E W EB_ W W W # 8 8 48 6 -0 80 1
[2 9 ] HP _ S E NS E 9 4 W E B _ E MA I L# W E B _ W W W # [ 27 ]
[1 7 ] US B _ P N 9 10 5 W E B _ E MA I L # [ 27 ]
[ 17 ] U S B _P P 9 L ID_ S W #
11 6 LI D _S W # [ 1 1 , 2 7]
C 5 4 6 C 5 47
S P K O UT R+ 12 7 A P _ ON
[ 2 9 ] S P K OU TR +
*0 . 1 u _1 6 V _ Y 5V _ 0 4
* 0. 1u _ 16 V _ Y 5 V _ 04
S P K O UT R- 13 8 A P _ ON [ 3 1 ]
[ 2 9 ] S P K OU TR - 14 9
8 72 1 3-1 4 0 0G 10 VIN
A UD G * 50 5 0 0-0 1 0 41 -0 01 L
[ 2 , 3 , 8 , 11 , 1 3 , 14 , 1 5, 17 , 1 8, 1 9 , 2 0, 2 2 , 2 3, 2 6 , 2 8, 3 1 , 3 3, 3 4 , 3 5] 3 .3 V
[ 1 1, 1 2 , 1 9, 2 0 , 2 5, 2 9 , 3 1, 3 6 , 3 7] 5 VS
[ 2 0, 2 3 , 2 6, 3 1 , 3 3, 3 4 , 3 5] 5V
[ 2 6] U S B V CC
[ 1 1, 3 1 , 3 2, 3 3 , 3 4, 3 5 , 3 6, 3 7 , 3 8] VIN
[ 3, 9 , 1 0 , 11 , 1 2 , 13 , 1 4 , 15 , 1 6, 17 , 1 8, 1 9 , 2 0, 2 3 , 2 4, 2 5 , 2 7, 2 8 , 2 9, 3 1 , 3 6] 3 .3 VS
USB, Fan, TP, Multi-Conn B - 31
Schematic Diagrams
5VS, 3VS, 1.05VS, 1.5VS_CPU

SYS5 V SYS5 V
VIN V A V IN 1
P R 22 4 P R 22 2
PC2 P C 1 10 P C 1 11 ON 1 0 K _ 04 1 0 K _0 4
DD_ON"L" T O
0 . 1u _ 5 0V _Y 5V _0 6 0 . 1 u _5 0 V _ Y 5 V _ 0 6 0 . 1 u _5 0 V _ Y 5 V _ 0 6
"H" FROM EC D D _ ON # S US B
D D _ ON # [ 3 0 , 3 3 ] S U S B [ 3 , 6, 3 3 , 3 4]
PU 7
1 8
VA V IN 1 P Q6 7 A 6 P Q6 7 B 3
2 7 R3 7 1 1 K _0 4 D D_ O N M TD N7 0 0 2Z H S 6 R D MT D N7 0 02 Z H S 6 R D
V IN D D _ O N _ L A TC H
P R2 2 6 1 K_ 0 4 3 6 R 60 4 1 K_ 0 4 D D _ ON 2 G 5 G
[ 3 0 ] M_ B T N # M_ B T N # P W R _S W # P W R_ S W # [2 7 ] [ 26 , 2 7 , 32 ] D D_ O N [ 1 5 , 2 6 , 27 ] S U S B #
S S
P R2 2 7 1 K_ 0 4 4 5 1 4
[ 30 ] A P _ O N I N S T A N T- ON GN D 10/28 P R 22 1 P R 22 0
ON ON
P 2 8 08 B 0 P R1 2 3 1 0K _ 0 4 VD D3
P R2 3 4 *1 0 K _ 0 4 11/02 1 0 0K _ 0 4 1 00 K _ 0 4
V IN
10/29
5V
ON ON
3. 3 V 3 .3 V S
C 5 04 C 5 05 C5 0 6 C2 4 7 C 22 4 C 2 25
0 . 0 1 u_ 1 6 V _ X7 R _0 4 0 . 0 1 u _1 6 V _ X7 R _0 4 0. 0 1 u _1 6 V _ X7 R _0 4 0. 0 1 u _1 6 V _ X 7R _ 04 0 . 0 1 u_ 1 6 V _X 7 R_ 0 4 0 . 0 1 u_ 1 6 V _ X7 R _0 4 1.5VS
1 .5 VS
S Y S 15 V 1 .5 V
NM OS
P Q6 4 A
Sheet 31 of 43 8
MT N N 2 0N 0 3Q 8
2
5VS, 3VS, 1.05VS, 5V 5VS P R2 1 8
1M _ 04
7 1
NMO S P C2 1 7 P C 2 16 P R 21 9
P Q6 5 A NMO S
3
S Y S 1 5V V DD 5
1.5VS_CPU M T NN 20 N 03 Q8 5V S Y S 1 5 V V D D5 P Q 6 6A 5 VS 0 . 1u _ 1 6V _Y 5V _0 4 1 0 u _6 . 3 V _ X 5R _ 06 1 0 0_ 0 4
1. 5 V S _ L O
8 2 M T N N2 0 N 0 3 Q8 1 .5 VS_ EN
P R2 2 5
3A 7 1 3A 8
7
2
1
Power Plane P R 2 23
4
1 M_ 0 4 P Q6 4 B
D
3
P R 23 1 1 M_ 0 4 P C 2 19 P R 23 2 MT N N 20 N 03 Q 8 P Q 63
3
5 V _ EN1 P C2 1 2 MT N 70 0 2 Z H S 3
1 0 0K _ 0 4 5 VS_ EN 1 0 . 1 u _1 6 V _ Y 5 V _ 0 4 *1 0 0 K _ 04 5 S US B G
4
P Q 6 5B 47 0 p _5 0 V _ X 7R _ 04
S
M TN N 2 0 N 0 3 Q8 P Q6 6 B
6
P C2 2 1 M TN N 2 0 N 0 3 Q8
5 DD _O N # P C 2 22
4 70 p _ 50 V _ X 7 R _ 04 5
S U S B [ 3 , 6, 33 , 3 4 ]
1
4 7 0p _ 5 0 V _X 7 R _ 0 4
6
1
PJ 2 0
6
PJ 1 9
*4 0m i l ON
1.5VS_CPU
2
* 4 0m i l
2
ON
11/03
3.3V 3.3VS 1 .5 V 1 .5 V _ CP U
PJ 1 5
NMO S NM O S 3 .3 VS * OP E N _5 A
S Y S 15 V V DD 3 P Q2 1A 3 . 3V S Y S 1 5V V DD 3 P Q 20 A 2 1 10A
M T N N 20 N 0 3 Q8 M TN N 2 0 N 0 3 Q8
3A 8 2 3A 8 2 SYS1 5 V PJ15 MUST SHORT
7 1 7 1 P R7 2
PR1 1 1 P R 10 9 P Q4 8 A NMO S
Power Plane *M TN N 2 0 N 0 3 Q8 * 2 20 _ 0 4
1 M_ 0 4 P R2 3 3 1 M_ 0 4 P C9 6 PC 9 4 P R 10 2 P R7 1 8 2
1 . 5 V S _ C P U _L O
3
7 1
3 . 3 V _E N 1 *1 00 K _ 0 4 0 . 1u _ 1 6V _ Y 5V _0 4 1 0 u _6 . 3 V _ X 5R _ 06 1 00 _ 0 4 *1 M_ 0 4
P C1 8 0 P C 1 79
4
3. 3 V S _ L O
P Q 2 1B 3 .3 V S_ E N1
3
M TN N 2 0 N 0 3 Q8 1 .5 VS _ CP U E N *0 . 1 u_ 1 0 V _ X7 R _0 4 * 10 u _ 6. 3V _ X 5 R _ 0 6
PC9 5
5 D D _O N #
4
P Q4 8 B
D
4
2 20 0 p _5 0 V _ X7 R _0 4 P C 89 P Q 20 B * MT N N2 0N 0 3Q 8 P Q1 1
D
MT N N2 0 N 0 3 Q8 P Q 16 P C4 6 * MT N7 0 0 2Z H S 3
6
4 7 0p _ 5 0V _ X 7 R _ 0 4 MT N 70 0 2 Z H S 3 5 SU SB G
5 S US B G *2 20 0 p _5 0 V _ X 7R _ 04
S
S
6
3 . 3 V [ 2 , 3 , 8, 1 1 , 1 3 , 14 , 1 5 , 17 , 1 8 , 1 9, 2 0 , 2 2, 23 , 2 6 , 28 , 3 0 , 3 3, 3 4 , 3 5]
6
1 . 5 V S [ 1 9 , 29 ]
5 V S [ 1 1 , 1 2, 1 9 , 2 0 , 25 , 2 9 , 30 , 3 6 , 3 7]
V I N [ 1 1, 30 , 3 2 , 33 , 3 4 , 3 5, 3 6 , 3 7, 3 8 ]
S Y S 1 5V [ 32 , 3 4 ]
V A [3 8 ] ON
ON 1 . 5V _ C P U [ 3 , 6 ]
1 . 5V [ 3, 6 , 8 , 9 , 1 0, 2 0 , 2 6, 28 , 3 3 ]
5 V [ 2 0, 2 3 , 2 6, 30 , 3 3 , 34 , 3 5 ]
V IN1 [3 2 ]
3 . 3V S [ 3, 9, 1 0 , 1 1, 1 2 , 1 3 , 14 , 1 5 , 16 , 1 7 , 1 8, 1 9 , 2 0, 23 , 2 4 , 25 , 2 7 , 2 8, 2 9 , 3 0, 3 6 ]
V D D 3 [ 13 , 2 2 , 2 4, 2 7 , 3 2, 38 ]
V D D 5 [ 26 , 3 2 ]
B - 32 5VS, 3VS, 1.05VS, 1.5VS_CPU
Schematic Diagrams
VDD3, VDD5
V RE F
P R1 95 * 0 _0 4 P R7 7 0_04
P C1 9 5
1 u _ 10 V _ Y 5 V _ 0 6
P R 19 8 P R1 9 7
E N_ 3 V E N_ 5 V
P C2 0 1
1 00 K _ 0 4 1 00 K _ 0 4 P C1 9 8
1 0 0 0p _ 5 0V _X 7 R_ 0 4 1 00 0 p _5 0 V _ X7 R _0 4
1
P U1 1
V RE G 3
EN 2
VFB2
TO NSEL
VFB1
EN1
VREF
V IN V IN
7 24
P C2 0 0 P C 64 VO 2 V O1
P C1 9 9 P R2 0 1 *1 0 K _ 04
4.7 u _ 25 V _ X 5R _ 08 4 .7 u_ 2 5 V _X 5 R_ 0 8 8 23
VDD3 P Q 56
P 1 2 03 B V
1 u _ 10 V _ Y 5V _ 0 6
P C 20 3 9
L DO 3 P OK
22
P C2 0 4
S Y S 5V
0 .1u _ 1 0V _X 7 R_ 0 4
P C2 0 6
0 .1 u _5 0 V _ Y 5 V _ 0 6
P C2 0 5
4 .7u _ 2 5V _X 5 R_ 0 8
PC 7 4
4 . 7 u _2 5 V _ X5 R _0 8 5A
VDD5
B O OT 2 B OO T1
8
7
6
5
5
6
7
8
5A uP6182
0 .1 u_ 1 0 V _X 7 R_ 0 4 P Q 13
4 10 21 4 P 1 2 03 B V S Y S 5V
V D D3 SY S3 V U GA T E 2 UGA TE 1 V D D5
P L1 0 PL 9
P J 10
3
2
1
1
2
3
PJ 8 4 .7 UH_ 6 .8 *7 .3 *3 . 5 4 . 7 UH _ 6.8 * 7. 3 *3 .5
2 1 2 1 11 20 1 2 1 2
PH ASE2 P HA S E 1
Ra
*5 m m PC7 2 P Q 60 *5 m m
Sheet 32 of 43
C
8
7
6
5
5
6
7
8
P C6 5 P 1 2 03 B V 12 19 P R7 5
L GA T E 2 L GA TE 1
GND P A D
C
C
0 . 1 u _1 6 V _ Y 5V _0 4
S K IP S E L
P Q1 2 P D 9 P D2 1 P C6 1
VDD3, VDD5
2 2 0u _ 6 . 3 V _6 . 3 *6 . 3 * 4 . 2
P R7 6 P C6 2 P D 6 P D5 4 4 3 0K _ 1 % _0 6
L DO 5
VCL K
GN D
EN 0
+ P 1 2 0 3B V 1 0 0 0p _ 5 0V _ X 7 R_ 0 4
V IN
3
2
1
1
2
3
13 K _ 1 %_ 0 6
C S O D 1 40 S H
*S K 3 4 S A
10 0 p _5 0 V _ N P O _0 4
PD 8 PD 7
C S O D 1 40 S H
* SK34SA
A
Rb
A
A
13
15
17
A C C A PC 6 3 PC5 8
14
25
16
18
V R E G5 V R E G5 +
P R 2 28 P R1 9 6
* RB 0 5 4 0S 2 P R2 0 9 E N_ A L L 11/05 2 2 0 u_ 6 .3 V _6 . 3 *6 .3 *4 . 20 . 1u _ 1 6V _ Y 5V _0 4
P R1 9 4 *R B 0 54 0 S 2 * 0 _0 4 1 9. 1 K _ 1 % _0 6
* 6 80 K _ 1 % _0 4 P R 2 1 3 P R2 10 P R2 11
M990125
20 K _ 1 %_ 0 4 P R2 12 P D2 2 R B 0 54 0 S 2
P R2 1 4 * 0 _0 4 * 0 _0 4 2 .2_ 0 6 * 0 _0 4 0_04 C A
VR EF S Y S 5V
P C2 09
V R E G5 P R2 1 5 0_04
P D2 3 R B 0 54 0 S 2
0 .0 1 u_ 5 0 V _ X7 R_ 0 4 A C
S Y S 10 V
V IN 1 V R E G5
P C6 9
V R E G5 P D2 4
D
P C2 0 7 P C2 0 8 P D1 9 R B 0 54 0 S 2
P Q7 3 P R 86 * 0 _0 4 E N_ 3 V C A 2 20 0 p _5 0 V _ X7 R _0 4
V IN
G C A
E N _3 V 5 V
[3 8 ] US B _A C _ IN P R9 0 4 .7 u _2 5 V _ X 5R _ 08 1 u_ 1 0 V _ Y 5 V _ 06
MT N7 0 02 Z H S 3 R B 0 5 40 S 2 P C2 10
E N_ 5 V
S
P R 82 0_04
10 K _ 0 4 P D2 0 R B 0 54 0 S 2
0 .0 1 u_ 5 0 V _ X7 R_ 0 4 A C
S Y S 15 V
D
PQ 1 4 P C6 8
DD _O N_ E N _V D D G
P Q1 8 MT N7 0 02 Z H S 3 2 20 0 p _5 0 V _ X7 R _0 4
D
S
PC7 1
PR8 4
1
G PJ 1 1
[2 6 ,2 7, 3 1 ] DD _ ON
M T N 70 0 2 Z H S 3
*4 0 m il
S
0. 1u _ 1 0V _ X 5 R _ 0 4
10 0 K _ 0 4
2
V IN [ 1 1,3 0 ,3 1,3 3 ,3 4, 35 , 3 6 , 37 ,3 8 ]
V IN 1 [ 31 ]
S Y S 15 V [3 1 ,3 4]
V D D 5 [2 6, 3 1 ]
V D D3 [1 3, 2 2 , 2 4 , 27 ,3 1 ,38 ]
VDD3, VDD5 B - 33
Schematic Diagrams
Power 1.5V/0.75V/1.8VS
V IN
P D4
PU 4 A C P C 51 P C 1 92 P C1 9 1 P C1 8 8 P C 1 86
5V +
5
6
7
8
0 . 1 u _5 0 V _ Y 5 V _ 0 6
4 . 7 u _ 2 5V _ X 5 R _0 8
4 . 7u _ 2 5 V _ X 5R _ 0 8
0 . 1 u _5 0 V _ Y 5 V _ 0 6
* 1 5u _ 2 5 V _ 6. 3 * 4. 4 _ C
u P 6 1 63 P Q5 2
R B 0 5 4 0S 2 4
MD U 2 6 57
VTT_MEM
P C5 6
1.5V
1
2
3
1 0 u _ 10 V _ Y 5V _0 8 V DD Q
P C 60 0 . 1 u _1 0 V _ X 7 R _ 0 4
23 22
V L DO IN VBS T
PJ 1 8 P R 1 92
2 1 24 21
V T T _ ME M
*OP E N _ 2 A
VTT DR VH
3 . 3 _ 06
PL 7
1 . 0 U H _ 11 . 5 *1 0 . 2 *3 . 0
V D DQ 30A PJ 6
1 .5 V
1 20 1 2 1 2
P C1 9 4 P C5 5 PC 5 4 V T T GN D LL
P R8 0 * OP E N _ 1 2A
0_ 0 6 2 19
1 0 u_ 1 0 V _ Y 5 V _ 0 8 10 u _ 1 0V _Y 5 V _ 08 * 1 0u _ 1 0V _Y 5 V _ 08 V T T S NS D RV L
5
6
7
8
P C 52 P C 1 84 P C4 8 PC 4 9
P D 17
C
3 18 P Q5 1 P C 1 69
5
6
7
8
GN D P GN D 17 4 +
* 1 00 0 p _X 7R _ 06
56 0 u _ 2. 5 V _ 6 . 6 *6 . 6 *5 . 9
0 . 1 u_ 1 6 V _ Y 5 V _ 04
0. 1 u _ 1 6V _ Y 5 V _ 0 4
V DD Q P R 2 05 0 _0 6 P R8 1 0_06 PQ 5 0
C S _ GN D
M D U 26 5 44 +
* 5 60 u _ 2 . 5V _6 . 3 *6
4 16 5V
1
2
3
P R 2 03 *0 _ 0 6 P R 83 6 . 1 9K _ 1 % _ 0 6
5V MO D E CS
1
2
3
*M D U 26 5 4 P R7 3
C S O D 14 0 S H
A
P R 2 02 *0 _ 0 6 P C 70 0 . 1 u _ 10 V _ X 7 R _ 0 4 15
5 P V CC 5 14 P R8 9 2 .2 _ 0 4
V T T RE F V CC 5
*5 . 1 _0 6
PC 7 6 P C8 0 P R9 1
P R2 0 6 0_06 6 13 P GO OD _ 61 6 3
5V C O MP P G OO D 3 .3 V 0_06
1 u _ 1 0V _ Y 5 V _ 0 6
1u _ 1 0 V _ Y 5V _0 6
P R2 0 8
P R1 9 3 * 2 2_ 0 4 8 11
V T T_ M E M V D DQ S NS S 5
*1 0 0 0 p_ 5 0 V _ X 7 R _ 0 4
PC7 5
Sheet 33 of 43 P R9 2
D
9 10 1 0 0 K_ 0 4
V D DQ S E T S 3
*1 0 _0 6
P Q5 7
VD DQ SET
SU SB G
Power 1.5V/0.75V/
GN D
D D R 1 . 5 V _ P W R GD [1 5 ]
*M T N 7 0 0 2Z H S 3
NC
NC
S
P C7 9
* 10 0 0 p _5 0 V _ X 7 R _ 0 4
1.8VS
12
25
P R1 0 1
5V
* 10 K _ 1 % _ 04
P R1 1 8 4 7 K _ 04 PR 9 8 1 0 K _ 1 % _0 6
5V
PR 9 9 1 0K _ 1 % _ 0 6
D
P C8 4
D
P Q2 3
P R1 1 7 10 0 K _ 0 4 G MT N 7 0 0 2 Z H S 3 PQ 2 4 * 0 . 1u _ 1 6 V _ Y 5 V _ 0 4
G
S
1
P R1 0 3 1 0 0K _ 0 4 V T TE N * MT N 70 0 2 Z H S 3
5V
S
P Q2 2 P J 12
G *4 0 m i l
[ 1 5 , 27 ] S U S C #
D
P C8 2 MT N 7 0 0 2 Z H S 3
[ 3 0 , 3 1 ] D D _ ON #
2
S
PQ 1 9
S US B G 0. 1 u _ 1 6V _ Y 5 V _0 4
M T N 7 0 0 2Z H S 3
1. 5V _CTRL1 1. 5_ CTRL0 V olta ge
1 1 1 .55 V
1 0 1 .60 V
0 1 1 .65 V
0 0 1 .70 V
3 .3 V
3 .3 V
5V
P R1 1 0 10 K _ 0 4 P C 91 1.8VS
2A 5
PU 5
6
1 u_ 1 0 V _ Y 5 V _ 0 6
V1 .8 1 .8 V S
1 . 8 V S _ P W R GD
9
7
V IN
V IN
V C NT L
4
3A 1
PJ 7
2
[ 3 , 1 5 ] 1 . 8 V S _ P W R GD P OK V O UT
3
1 0 u _6 . 3 V _ X 5 R _ 0 6
* OP E N _ 3A
10 u _ 6. 3V _ X 5 R _0 6
0 . 1 u_ 1 6 V _ Y 5 V _ 04
P R1 0 5 1 0 0K _0 4 E N1 .8 V S 8 V O UT P R7 8
5V EN
1 . 27 K _ 1 % _ 04
1 2
GN D V FB [ 6 , 1 8, 1 9 ] 1 .8 VS
[ 1 1 , 3 0, 3 1 , 3 2 , 3 4, 3 5 , 3 6 , 3 7, 3 8 ] VIN
D
P C9 0 P C6 6 [ 2 0 , 2 3 , 2 6, 3 0 , 3 1 , 3 4, 3 5 ] 5V
P Q 15 AX6 615ESA
SU SB G [ 2 , 3 , 8 , 11 , 1 3 , 1 4, 15 , 1 7 , 1 8, 19 , 2 0 , 2 2, 2 3 , 2 6 , 2 8, 3 0 , 3 1 , 3 4, 3 5 ] 3 .3 V
PC 8 5 PC 8 3 11/0 9
[ 3 , 6 , 3 1, 34 ] S U S B M TN 7 00 2 Z H S 3 8 2p _ 5 0V _N P O _0 4 [ 3 , 6 , 8 , 9 , 1 0, 2 0 , 2 6 , 2 8, 3 1 ] 1 .5 V
0 . 1u _ 1 6 V _Y 5V _0 4
[ 9, 1 0 ] V T T _ ME M
S
1 0 u_ 6 . 3 V _ X 5 R _ 0 6
0 . 1 u _1 6 V _ Y 5 V _ 0 4
PC 5 9
P R7 9
PC6 7
P C 57
GS7113 1K _ 1 % _ 0 4
6-02-07113-320
AX6610
6-02-06610-320
B - 34 Power 1.5V/0.75V/1.8VS
Schematic Diagrams
Power 1.05VS
5V
VI N
A
5V
0.1u_50V_Y5V_06
4.7u_25V_X5R_08
0. 1u_50V_Y5V_06
4.7u_25V_X5R_08
PD10
PR1 08
1.05VS_EN RB0540S2
C
100K_04
PR94 8.2K_1%_04
PQ17 11/03
5
6
7
8
[3,6, 31,33] SUSB G PU6
SC412A / uP6127 PQ53
S
MTN70 02ZHS3 PC88 4 ME4894-G
PC45
PC50
1.05VS
PC190
PC187
1
2
3
*0. 1u_16V_Y5V_04
PC77
0. 1u_16V_Y5V_04
13
14
15
16
560u_2. 5V_6. 6*6. 6*5. 9

560u_2.5V_6.6*6.6*5.9
PL8 11/03 V1. 05 PJ17 1.05VS
N. C
PR107 10K_04 1. 0UH_ 11.5*10.2*3.0 *OPEN-12mm
16A
N.C
DH
3. 3V
ILIM
PC1890.1u_16V_Y5V_04
12 1 1 2 1 2
EN LX
11 2
*1000p_X7R_06
[ 15] 1.05VS_PWRGD 1.0 5VS_PWRGD 11/05 PC53
PGD BST
PD18
PQ55 PQ54
C
5
6
7
8
5
6
7
8
10 3
VOUT VCC
PD3 +
R182
9 4 4 4
FB DL *28mil_0 6
CSOD140SH
+
RTN
GND
1
2
3
1
2
3
N.C
N.C
17
*SK34SA
*ME4626-G ME4626-G
A
PC183
PAD
PC182
PR74
*5.1_06
PC73
1u_10V_Y5V_06
PJ9
PR95 PR88 PC81

1 2
Sheet 34 of 43
*40mil
PR104 *9 0.9K_0 4
0_04 40 .2K_1%_04 4 7p_50V_NPO_04
PR87 0_04
Power 1.05VS
5V
VCCIO_SENSE [5]
PC87 PC86 PR96 PR85 0_04
0.01u_1 6V_X7R_04 20p_ 50V_NPO_04 10 0K_1%_04
1.05VS_VTT
5V 5V
1. 05VS 1.05VS_VTT
PJ16
*OPEN_ 5A PR55 PR56
2 1 10/1
100K_04 100K_04
0.8 5V_ON [ 35]

1 0A
D
NM OS PQ68
MTN7002ZHS3 PC31
PQ74 G
SYS1 5V P12 03BV 0. 1u_16V_Y5V_04
S
8 10 /1
1
7 3 PR229
6 2 B PQ10 PJ3
[2,3 ,5,18,1 9,20,36] 1.05 VS_ VTT
R420 5 1 C399 C405 2N3904 *1mm
R123
2
E
100K_04
0.1u_16V_Y5V_04
*10u_10V_Y5V_08
1M_04 *100_04
4
C414
3
2200p_50V_X7R_04 PQ75B Q19
D
D
5 MTDN7 002ZHS6R MTN7002ZHS3
G G
S
S
3.3V R573 10K_ 04

6
D
PQ75A
2 G
MTDN70 02ZHS6R S 1. 05VS_VTT_EN [ 15]
1 ON
[13,14, 15,19,2 0] 1. 05VS
[6,3 5] 0. 85VS
[ 3,9,10, 11,12,13 ,14,15, 16,17,18, 19,20,2 3,24,25, 27,28,29, 30,31,3 6] 3. 3VS
[2,3,8 ,11,13, 14,15,17, 18,19,2 0,22,23, 26,28,30, 31,33,3 5] 3. 3V
[20, 23,26,30, 31,33,3 5] 5V
[1 1,30,31, 32,33,35, 36,37,3 8] VIN
[31,3 2] SYS15V
Power 1.05VS B - 35
Schematic Diagrams
Power 0.85VS
3. 3V
PC129
0.022u_16V_X7R_04 PR159
10K_04
0.9V 0.8V 0.725V 0.675V

0.85VS_PWRGD [15]
VCCSA_VID0 0 0 1 1 VIN
PR137 VIN
VCCSA_VID1 0 1 0 1
0_04
0. 1u_50V_Y5V_06
4. 7u_25V_X5R_08
4. 7u_25V_X5R_08
0. 1u_50V_Y5V_06
0. 1u_50V_Y5V_06
0. 1u_50V_Y5V_06
0.1u_50V_Y5V_06
5V
PR33 PR147
9.3K_1%_04 9.3K_1%_04
A
1 1/0 4 PR34 PR146 PR148 PD1
FOR EMI
PC34
PC155
PC153
PC154
PC197
PC47
PC173
100_04 RB0540S2
12K_1%_04 10K_1%_04
C
PR35 PR145
POK
1
2
10K_1%_04 10K_1%_04
PQ36A
PU9
PC140 PD1503YVS
5
4
3
2
1
Sheet 35 of 43 PR36 PR144 uP6122 8
UG
0. 1u_16V_Y5V_04
EAP
POK
BOOT
SS
PL4 6A V0.85 PJ5 0.85VS
7
21
Power 0.85VS 15K_1%_04 10K_1%_04
6
7 SET3
SET2
GND
PHASE
LG
20
19
1. 0UH_6.8*7.3*3.5
1 2
*OPEN-5mm
1 2
8 18
9 SET1 VCC 17
PR151
SET0 RT
EN/PSM
10 16 PC168 PC40
COMP
FB CSP +
PR173
PR62 PR64
VID0
VID1
CSN
PC27
1K_1%_04 0_04 0_04
CSP
5
6
220u_6. 3V_6.3*6.3*4.2
0.1u_16V_Y5V_04
11
12
13
14
15
PR150 PC124 PR157
3
1u_10V_Y5V_06
100_04
CSN
33K_1%_04
PC131
22_04 0.01u_16V_X7R_04 PQ36B
4
PC25 PD1503YVS PR63 1 1/0 5
12K_1%_04
47p_50V_NPO_04 PC41
0.01u_50V_X7R_04
PR155 *0_04 PR158
PC42
0. 1u_25V_X7R_06
*0.1u_16V_Y5V_04
100K_1%_04 CSP
CSN
0.85V_ON [34]
PR65 1. 3K_1%_04
[ 6] VCCSA_VI D0
[ 6] VCCSA_VI D1 PR149
VCCSA_SENSE [6]
0_ 04
5V [20,23,26, 30,31,33,34]
0. 85VS [6]
VI N [11,30,31, 32,33,34,36,37, 38]
3.3V [2,3, 8,11,13,14,15, 17,18,19,20,22, 23,26,28,30,31, 33,34]
B - 36 Power 0.85VS
Schematic Diagrams
Power V-Core1
P R2 2 PC 1 1
1.05VS_VTT
1 0 _ 04 6 80 p _ 5 0V _ X 7 R _ 0 4
VCORE_1 P R2 0 P R 1 9 1 . 2 1 K _ 1 %_ 0 4
B~ 4 35 0
T RBST
5 4 . 9 _ 1% _ 0 4
2 4. 9K _ 1 % _ 04 PUT COLSE
PR 1 5 P R1 0 PR 1 2 PC 7
RT 4
TO VCORE
1 3 0 _1 % _ 0 4 * 7 5_ 0 4 5 6 0 0 p_ 5 0 V _ X 7R _ 04 1 2
A_G ND Phase 1
[ 5 ] H _ C P U_ S V I D D A T H_ CP U_ S V ID DA T 1 00 K _ N T C _ 0 6_ B Inductor
[ 5 ] H _ C P U_ S V I D C L K H_ CP U_ S V ID CL K P R1 3 1 P C1 1 3 PC 1 2 Qua d 4 5W C PU
VID 1= 0. 9V
DIFFO UT
[ 5 ] H _ C P U_ S V I D A L R T # H_ CP U_ S V ID A L RT # 1 0 0 _1 % _ 0 4 1 0 0p _ 5 0V _N P O _0 4 22 p _ 50 V _ N P O_ 0 4 P R 1 41 13 7 K _ 1 % _0 6
P R2 7 7 5 K _ 1 %_ 0 4 C S P 1 [ 3 7]
Ic cMa x = 94 A
FB
P R1 3 0 1 K_ 0 4 P R2 1 P C 13 P R 1 33
TS ENSE 4 . 0 2K _1 % _ 0 4 33 0 0 P _ 50 V _ X 7 R _ 0 4 1 6 5 K _ 1 %_ 0 6
PR 3 1 13 7 K _ 1 % _0 6
R_LL= 1 .9m ohm
10/29
P R 18 9 10 0 _ 04 P R 28 1 2 . 1K _1 % _ 0 4 P C 15 1 20 0 P C S P 3 [ 3 7] OC P~ 12 0A
P R 12 8 0 _0 4 V S S _ S E N S E _ 6 1 31 P C 14 2 70 p _ 5 0V _X 7 R _ 0 4
[ 5 ] V C OR E _ V S S _ S E N S E
P C5 CSS UM
R T3
PC 8
PR1 8 7
P R 1 42 1 0 _ 04
CS N1 [3 7 ]
0 . 1u _ 1 0 V _ X 7 R _ 0 4
1 0 00 p _ 5 0V _X 7 R _ 0 4
C SC OM P
P R 12 4 0 _0 4 VR 1_C SRE F
B~ 3 96 4 [ 5 ] V C OR E _ V C C _ S E N S E
T RBS T
CO M P
IM ON
1 0 0K _N T C _0 6 _ B
C S N3 [3 7 ]
IL IM
VCORE P R1 8 8 1 0 0_ 0 4 PR 9 * 1 5m i l _ 06 PR 3 2 1 0 _ 04
8 . 25 K _ 1 % _ 04
CS N3 [3 7 ]
2
V C C _ S E N S E _6 1 3 1
PC 2 0 P C2 2 0 . 0 4 7u _ 1 0 V _X 7 R _0 4
3.3 VS
PUT COLSE A_G ND 1 0 0 0p _ 5 0V _X 7 R _0 4
TO VCORE PR 4 2 5. 49 K _ 1 % _ 04
53
52
50
49
48
47
45
44
43
42
41
40
51
46
A _G ND PU 1 C SP3 [3 7 ]
A_GN D
HOT SPOT A_GN D
C SCO M P
EP AD
FB
C OM P
D R O OP
D I F F OU T
TR BST
IO UT
CS R E F
N C2
NC 1
IL IM
CSSU M
VSN
P R 16 PR 1 1
P R1 5 3 0_ 0 4 C S N1 [3 7 ]
1 39 C S N 2 _5 V S
[ 3 ] H _ P RO CH OT #
P R 2 30 0_04
1 0 K _ 04 1 0 K _0 4
2
3
TSEN SE VSP
T S E NS E
V R H OT #
N C P 6 13 1 S
CS N2
C SP2
CS N3
38
37 CSN 3
5VS P C2 3 0 . 0 4 7u _ 1 0 V _X 7 R _0 4 Sheet 36 of 43
H_C PU_SVID DA T 4 36 CSP P3
H_C PU_SVID CLK
H_C PU_SVID ALRT#
VR_R DY
5
6
7
SDI O
SCL K
AL E RT #
C SP3
CS N1
C SP1
35
34
33
CSN 1
CSP P1
DR ON
P R4 3 5. 49 K _ 1 % _ 04
C SP1 [3 7 ] Power V-Core1
[1 5 ] D E L AY _ P W RG D 8 VR_ R DY D R ON 32 D R ON [3 7 ]
PR 8 0 _ 04 VR_R DY A
V R_ ON V R _ O N_ E N A B L E _ 61 3 1 9 VR_ R DY A P W M1 / A D D R 31 V R1 _ P W M 3 V R 1 _ P W M 1 [ 3 7]
10 ENA B L E P W M 3 / V B O OT 30 V R 1 _ P W M 3 [ 3 7]
6131_VCC P W M 2_ 6 1 3 1 P R 39 0_04
5VS VCC P W M 2/ I S H E D 5VS
P R 1 25 2 . 2 _0 6 A_GN D P R1 4 1 0K _0 4 R O S C 1 1 29 I MA X _ 6 1 31 P R1 5 6
VIN P R 17 V RM P _ VIN 1 2 RO S C IM A X 28 VR1_PWM A
VRM P PW M A /IM AX A V R 1_ P W MA [ 3 7 ]
D IF F OU T A
TS E NS E A 1 3 27 V B O OT A
C S C OM P A
1 K _ 1 % _ 04 P R 41 P R1 5 2 1 0K _0 4
5VS
D R O OP A
CSS UM A
T S E NS E A V B OO T A
TR BSTA
* 0 _0 4 PR 3 8
CO M PA
IO UT A
VSN A
IL IM A
C SPA
CS NA
TSEN SEA PC 3 PC 6 P R4 0 P R 1 54 1 0K _0 4
VSPA
FBA
P R1 8 4 1 . 2 K _ 1% _ 0 4
1 u_ 6 . 3 V _ X 5R _ 0 4 0 . 0 1u _ 5 0 V _ X7 R _0 4 10 K _ 0 4 2 0 . 5 K _ 1% _ 1 / 1 6W _0 4
*1 4 K _ 1 % _0 4 OPTION: A_GN D
14
16
17
18
19
21
22
23
24
25
26
1
15
20
DISALBE
1
P J1 4 P R3 7 A_GN D PJ 1 3 P R1 4 3
V SNA_ 6 1 3 1
V S P A _6 1 3 1
P C 1 14 V_GT A_GN D *6 m i l
R T1
*6 m li 1 13 K _ 1 % _ 04
IC C_M AX _2 1h
2
A_GN D A_GN D 11 3 K _ 1 % _0 4
IM ON A
1
2
= R*10 uA*25 6A/ 2V
0 . 1 u _1 0 V _ X 7 R _ 0 4
P R 1 69
IL IM A
P C2 1 A_GN D 20100805
B ~3 9 64 1 0 00 p _ 50 V _ X 7 R _ 0 4
A _G ND
C SNA A_GN D
1 0 0 K _ N T C _ 06 _ B
2
I MO NA I MO N C SPPA
8 . 2 5 K _1 % _ 0 4
P C 19
0 . 0 2 2 u_ 1 6 V _ X 7R _ 04 C S NA [ 3 7]
CSS UM A P R1 3 5
C S P A [ 37 ]
P R 1 40 P C1 1 7 P R1 3 4 P C1 1 8 CSC OM PA PC 1 6 47 0 p _ 50 V _ X 7 R _ 0 4 1 1 5 K _ 1 %_ 0 6 P R1 3 9
2 4 K _ 1 %_ 0 4 2 4 . 3 K _ 1% _ 0 4 7 . 5 K _ 1 %_ 0 4 C S PA [3 7 ]
A_GN D 0 . 1 u _1 0 V _ X 5 R _ 0 4 P R1 3 2
0. 1 u _ 1 0V _X 5 R _ 0 4 1 5K _ 1 % _ 0 4
CO MPA PC 1 7 27 0 P _ 5 0V _X 7 R _0 4
PUT COLSE DIF FOU TA
A_G ND A_GN D
TO V_GT A _G ND A _G ND P R2 4 PR 2 6
HOT SPOT P C1 0 P R 25 7 5 K _ 1 % _0 4 1 6 5K _1 % _ 0 6
P R 1 91 1 0 0_ 0 4 6 8 P _ 5 0V _N P O_ 0 4 1 0 _0 4
RT 2
P R2 3 1 2 Q ua d VCC AXG
P R 12 7 0 _0 4 1 K_ 0 4 V ID1 = 1. 15 V
[ 6 ] V S S _ GT _ S E N S E
FBA PC1 1 5 10 0 K _ N T C _ 06 _ B B~ 4 35 0 I cc Ma x =2 6A
P C9
P R 12 6 0 _0 4 10 0 0 p _5 0 V _ X 7 R _ 0 4
1 0 0p _ 5 0 V _ N P O _ 04 R _LL= 3. 9m ohm
[ 6 ] V C C _ G T _S E N S E
P C 11 6 PUT COLSE O CP~ 3 1A
P R 1 29 3 . 0 1 K _ 1 %_ 0 4 3 3 00 p _ 5 0V _X 7 R _ 0 4
P R 1 90 1 0 0_ 0 4 TO V_GT
V_GT Inductor
PR 6 * 1 0K _0 4 V R _ ON
3 . 3V S
1 2
P R3
PJ 2 *6 m i l 6
* 1 00 K _ 0 4 D
P Q6 9 A PR 5
G 2
S * 10 K _ 0 4
3 1 * MT D N 7 00 2 Z H S 6 R P R7 *1 0 m il _ 0 4
V R _O N
1
D
P Q6 9 B PJ 1 [ 1 1 , 1 5, 27 ] A LL _ S Y S _P W R G D
G 5
[ 27 ] V C O R E _ ON *6 m i l
S [ 1 1 , 12 , 1 9 , 2 0 , 25 , 2 9 , 3 0 , 31 , 3 7 ] 5 V S
4
2
*M T D N 7 00 2 Z H S 6R
[ 3 , 9 , 1 0, 1 1 , 1 2 , 1 3, 1 4 , 1 5 , 1 6, 1 7 , 1 8 , 1 9, 2 0 , 2 3 , 2 4, 2 5 , 2 7 , 28 , 2 9 , 3 0 , 31 ] 3 . 3 V S
[ 3 7 ] V _ GT
[ 5 , 37 ] V CO RE
PC 1
[ 1 3 , 1 4 , 15 , 1 9 , 2 0 , 34 ] 1 . 0 5 V S
[ 1 1 , 3 0 , 3 1, 3 2 , 3 3 , 34 , 3 5 , 3 7 , 38 ] V I N
*0 . 1 u _ 16 V _ Y 5V _0 4 [ 2, 3 , 5 , 1 8 , 1 9, 2 0 , 3 4 ] 1 . 0 5V S _V TT
Power V-Core1 B - 37
Schematic Diagrams
Power V-Core2
VIN
VCORE_2 P C2 2 3
+
P C1 3 3
+
P C 15 2 P C1 4 9 PC1 6 1
* 4. 7 u _ 25 V _ X 5 R _ 0 8
1 5 u_ 2 5 V _ 6. 3 *4 . 4
*4 . 7 u_ 2 5 V _ X 5R _ 08
0 . 1 u _5 0 V _ Y 5 V _0 6
*3 3 0 u F _2 5 V
P R1 36 P C 11 9
PQ 2 9 P Q3 9
M D U 26 5 7 *M D U 26 5 7
D
2 . 2 _ 06 0 . 2 2 u _1 0 V _ X7 R _0 6
P U8 N C P 5 91 1 G G
11/03
25A
S
1 V R E G_ S W 1 _ H G PL 6
BS T HG 8 0 . 3 6u H _1 2 . 9 *1 4 *3 . 8
2 7 V R E G_ S W 1 _ OU T 1 2 VC ORE
[ 3 6 ] V R 1_ P W M 1 PW M SW V CO RE
PQ 3 8 PQ 4 6 P Q2 8
P R 1 38 3 M D U 26 5 4 M D U 26 5 4 *M D U 26 5 4 P C 36
[ 3 6 ] D R ON EN GN D 6
D
4 9. 9 _ 1 %_ 0 4
C
4 V R E G_ S W 1 _ L G * 10 0 0 p_ X 7 R_ 0 6
5VS V CC LG 5 G G G P D 15
P AD
2 . 2 u _6 . 3 V _ X 5 R _ 0 6
PR 6 9 *1 5 m il _ 06 C SN1 [3 6 ]
S
9 S K 34 S A
P R 57
A
* 5. 1 _ 0 6 PR 6 7 *1 5 m il _ 06
C S P 1 [ 36 ]
P C 1 25
PC1 3 0 P C1 2 0 P C1 2 1 P C 1 22
+
50A
* 4. 7 u _ 25 V _ X 5 R _ 0 8
* 4. 7 u _ 25 V _ X 5 R _ 0 8
1 5 u_ 2 5 V _ 6. 3 * 4. 4
0 . 1 u _5 0 V _ Y 5 V _0 6
VIN [5 ,3 6 ] VCO RE
P R2 9 P C 18
P Q4 0 P Q3 0
MD U 2 6 57 *M D U 26 5 7
D
2 . 2 _ 06 0 . 2 2 u _1 0 V _ X7 R _0 6 +P C 17 6 +P C 17 2 +P C 17 8 +P C 1 74 +P C 1 75 +P C 1 70 +P C 1 77 +P C 1 71
Sheet 37 of 43 G G
* 33 0 U _ 2 . 5 V _ D 2
* 33 0 U _ 2 . 5 V _ D 2
* 3 30 U _ 2 . 5 V _ D 2
P U2 N C P 5 91 1
5 6 0u _ 2 . 5V _ 6 . 6 *6 . 6 *5 . 9
5 6 0u _ 2 . 5V _6 . 6 *6 . 6 *5 . 9
5 6 0u _ 2 . 5V _6 . 6 *6 . 6 *5 . 9
5 6 0u _ 2 . 5 V _6 . 6 *6 . 6 *5 . 9
5 6 0u _ 2 . 5 V _6 . 6 *6 . 6 *5 . 9
S
S
1 V R E G_ S W 3 _ H G PL 5
HG 8
Power V-Core2 [ 3 6 ] V R 1_ P W M 3
2
BS T
PW M SW
7 VR EG_SW3_OU T
P Q4 5 PQ 4 1 P Q3 1
0 . 3 6u H _1 2 . 9 *1 4 *3 . 8
1 2 VC ORE 25A V C OR E
PR 3 0 3 MD U 2 6 54 M D U 26 5 4 *M D U 26 5 4 P C 43
GN D 6
D
[ 3 6 ] D R ON 4 9. 9 _ 1 %_ 0 4 EN
4 VR EG_SW3_LG * 10 0 0 p_ X 7 R_ 0 6
5VS LG 5
C
V CC G G G
2 . 2u _ 6 . 3 V _X 5 R _0 6
P AD P D1 1 PR 7 0 *1 5 m il _ 06
P R 66 CS N 3 [3 6 ]
S
9
SK3 4 SA
A
* 5. 1 _ 0 6 PR 6 8 *1 5 m il _ 06
CS P 3 [3 6 ]
PC 2 4
P C 12 3
+
P C 12 7 P C 12 8 P C1 2 6
VGFX_CORE
15 u _ 25 V _ 6 . 3 *4 . 4
*4 . 7 u_ 2 5 V _X 5R _ 08
*4 . 7 u_ 2 5 V _ X 5R _ 08
0. 1u _ 5 0V _ Y 5 V _ 0 6
PR 5 2 P C3 0 VIN
V_GT
P Q3 3
*M D U 2 6 5 7 PQ 3 2
D
2 . 2 _ 06 0 . 2 2 u_ 1 0 V _ X7 R _0 6 M D U 26 5 7 P R6 0 *1 5 m il _ 0 6
D
G
P U3 N C P 5 91 1 G
S
VGFX_CORE
S
1 8 VR EG_SWA_H G PL 3
[ 3 6 ] V R 1_ P W M A
2
BS T
PW M
HG
SW
7 VR EG_SWA
11/04 0 . 3 6u H _1 0 *1 0 *3 . 5
1 2 VGFX_CO RE 25A
P Q4 4 PQ 4 3
PR 5 4 3 *M D U 2 6 5 4 M D U 26 5 4 P C 37
PD 2
[ 3 6 ] D R ON GN D 6
C
4 9. 9 _ 1 %_ 0 4 EN +P C 1 47 +P C 16 4
4 5 VR EG_SWA_LG *1 0 0 0p _ X 7R _ 06
5VS VCC LG 11/0 9 G G
3 30 u F _ 2 . 5V _9 m _ 6. 3 * 6
* 3 30 u _ 2. 5 V _ 9 m _6 . 3 *6
2 . 2 u _6 . 3 V _ X 5 R _ 0 6
P AD PR5 9 * 15 m i l_ 0 6 CS NA [3 6 ]
CS OD1 4 0 S H
9 P R 61
A
*5 . 1 _ 06
PR5 8 * 15 m i l_ 0 6
P C3 8
C S P A [ 3 6]
V C OR E [ 5 , 36 ]
V _ GT [ 3 6 ]
V G F X_ C OR E [ 6 ]
[ 1 1, 3 0 , 3 1, 3 2 , 3 3 , 34 , 3 5 , 36 , 3 8 ] V I N
[ 1 1, 1 2 , 1 9, 2 0 , 2 5 , 29 , 3 0 , 31 , 3 6 ] 5 V S
B - 38 Power V-Core2
Schematic Diagrams
Charger, DC In
CHARGER VA
# Cha rge Current 3.0A
# Cha rge Volt age 12.6V
P Q3 7
4
VIN ME P 4 4 3 5Q 8 # Tot al Power 60W
1 5
2 6
JA C K 1 3 7
50 9 3 2-0 0 3 01 -0 0 1 VA PQ 2 5 8
11/0 4
M E P 4 43 5 Q8 P Q3 5 A
PL 1 H C B 45 3 2 K -80 0 _ 18 8 P R4 A P 6 9 01 G S M P L2 P R 1 75 V_ BAT
1 11/05
7 3 0 . 0 2 _1 % _ 32 2 4. 7 U H _ 6. 8 * 7. 3 *3 . 5 0 . 0 2 _1 % _ 32
2 6 2 1 7
G ND 1 5 1
P C1 08 P C1 0 7 P C 10 9 P R1 8 6
G ND 2
0_04
11/03
0 _ 04
0 . 1 u _5 0 V _ Y 5 V _0 6
0 . 1 u_ 5 0 V _Y 5V _ 0 6
4 . 7 u _2 5 V _ X 5R _ 08
4. 7u _ 25 V _ X 5 R _ 0 8
0 . 1 u_ 5 0 V _Y 5 V _ 0 6
0 . 1 u_ 5 0V _Y 5 V _ 0 6
5
6
4 . 7 u _2 5 V _ X 5R _ 08
4 . 7 u_ 2 5 V _X 5R _0 8
4 . 7 u_ 2 5 V _X 5 R _0 8
4 . 7 u_ 2 5V _X 5 R _0 8
4 . 7u _ 2 5V _ X 5 R _ 0 8
4 . 7 u_ 2 5 V _X 5 R _0 8
P R 1 20 1 30 K _ 1 %_ 0 4 R 6 09
0 . 1u _ 5 0V _ Y 5 V _ 06
*0 . 3 3 u_ 5 0 V _ 08
4
8
20 0 K _ 1% _ 0 4
0 . 1 u _5 0 V _ Y 5 V _0 6
P R 12 1
*5 . 1_ 1 % _0 6
1 0 K _ 1 %_ 0 4 3
P R1 8 5 P R1 8 0 P Q 35 B C 5 88
4
A P 6 9 0 1G S M
P C 11 2
PR 1
PR 2
PC 3 5
PC 4
1 0K _ 1 % _0 4 0 _0 4
PC3 3
P C 18 1
P C 1 58
P C 13 8
P C 13 9
P C 15 9
P C1 5 7
P C 15 1
P C 1 34
*1 00 0 p _5 0 V _ X7 R _0 4
11/05
V_ BAT
10 0 K _ 1 %_ 0 4
P C 16 0 0 . 1 u_ 5 0V _Y 5V _0 6
* 0 . 1u _ 5 0V _ Y 5 V _ 0 6
*0 . 1 u _5 0 V _ Y 5 V _0 6
P C 13 7 P C 1 41 PC1 4 6 P C 1 43
*0 _0 4
P D1 2
1 u _ 25 V _ 0 8 PR1 6 4
0 . 1 u_ 5 0 V _Y 5 V _0 6 0 . 1 u _5 0 V _ Y 5 V _ 06 0 . 1 u _5 0 V _ Y 5 V _ 06 C A PIN 25th
0_ 0 4
PR1 2 2
R B 05 4 0 S 2 FOR2S CONNECT TO GND
FOR3S CONNECT N.C. V DD 3
P C 16 6
P C 1 65
V IN
FOR4S CONNECT TO VREF PIN
Sheet 38 of 43
PR1 7 2
C E L LS P R4 7 * 0_ 0 4 C
VA
P C3 9
0 . 1 u _5 0 V _ Y 5 V _ 06
PC2 8
0 . 1u _ 5 0V _ Y 5V _ 0 6
P C 44
0 . 1 u_ 5 0 V _Y 5 V _0 6
P C1 5 6
0 . 1u _ 5 0V _Y 5V _0 6
S M C_ B A T
D 6
AC
A Charger, DC In
32
30
28
26
VA
31
29
27
25
P U1 0 B A V 99 R E C T I F I E R
C
P GN D
CB
LX
VB
C E L LS
C T L2
OU T -1
O U T -2
1 24 P C1 3 2 0 . 1u _ 5 0V _Y 5V _0 6 S M D_ B A T AC
2 VC C VI N 23 CT L 1 A
3 -I N C 1 C TL 1 22
V DD 3 D 7
4 + INC 1 GN D 21 B A V 99 R E C T I F I E R
5 A C IN VR EF 20 C
TRERMAL PAD
6 A C OK RT 19 B A T_ D E T AC
P R1 8 2 7 -I N E 3 C S 18 V O L T_ S E L P R 17 6 A
CO M P 2
0 . 1 u _5 0 V _ Y 5 V _0 6
OU T C 2
C OM P 3
OUT C 1
8 AD J 1 A DJ 3 17
+ IN C2
A DJ 2
S G ND 6 D 9
-I N E 1
-I N C 2
0 . 1 u_ 5 0V _Y 5 V _ 0 6
10 K _ 0 4 C OM P 1 BAT T 33 4 9 . 9K _1 % _ 04 B A V 99 R E C T I F I E R
3 9. 2 K _ 1 %_ 0 4
[ 32 ] U S B _ A C _ I N S GN D
P R 18 1 MB 3 9 A 13 2 C
A C _ I N # [ 2 6 , 2 7]
11
13
15
AC
9
10
12
14
16
S GN D 6 B A T_ V O LT
1 0 K _1 % _ 04
C
T OTAL 1 0K _1 % _ 04 PC1 4 2 CHARGE A

PR1 8 4
C A B P Q4 2 1 0 0 p_ 5 0V _N P O_ 0 4 P R1 7 1 P R 17 0 D 8
VA POWER 1 K _ 1% _ 0 4 CURRENT B A V 99 R E C T I F I E R
PD1 3 PC1 6 3 D T C1 1 4E U A ADJ 1 K _ 1% _ 0 4 ADJ
UD Z 1 6 B
E
*0 . 1 u _5 0 V _ Y 5 V _ 06 P C 16 2 P C1 4 5 * 22 p _5 0 V _ N P O _0 4
P C 13 5
P C 1 36
PR1 6 2
PC1 4 4
0 . 0 1u _ 50 V _ X 7 R _ 04 1 0 0 0p _ 50 V _ X 7 R_ 04 P R 1 7 4 P R 16 7
2 0 K _1 % _ 04
V _B A T
P R1 8 3
2 2 K _1 % _ 04 S G ND6 S GN D 6 S GN D 6 2 2 K _1 % _ 04
S GN D 6 PC1 4 8
P Q8 PR 5 1 1 0 0 0p _ 50 V _ X 7 R_ 04 P R 1 7 7
A O3 4 0 9 3 0 0K _1 % _ 04
V _B A T S D B A T _ V OL T _ R S GN D 6
10 K _ 1 %_ 0 4 S G ND 6
P C1 5 0
G
PR4 9 11/05 0. 1 u _ 50 V _ Y 5 V _ 0 6
PR5 3 P C3 2
0.5V/1AT O TA L _ C U R P R2 3 5
[ 2 7 ] T OT A L _C U R
2 0 0K _ 0 4 60 . 4 K _ 1% _ 0 4 0 . 1u _ 5 0V _Y 5V _0 6 PI N17t h CONNECT
PR 4 8 4 7 0K _ 0 4
0.5V/1A C UR _ SE NS E TO BAT CONN. W250HU
0_04
P R 16 8
5
1 0 2K _ 1 % _0 4 F CM 10 0 5K F -12 1 T 03 1 2 PL 1 1 S M C_ BA T _ R
C E L LS C E P R1 6 1 [2 7 ] S MC _B AT F CM 10 0 5K F -12 1 T 03 1 2 PL 1 2 S M D_ BA T _ R 4
[2 7 ] S MD _B AT 3
D
PQ 6 V O LT _ S E L F CM 10 0 5K F -12 1 T 03 1 2 PL 1 3 B A T_ D E T_ R
[ 2 7] B A T_ D ET F CM 10 0 5K F -12 1 T 03 1 2 PL 1 4 B A T_ V O LT _ R 2
G VDD 3 V D D3 [2 7 ] B A T _V OL T 1
PQ 4
D
V DD 3 M T N 7 00 2 Z H S 3 D T A 1 14 E U A 6 PR1 7 8 2M _1 % _ 0 4 J BATTA1
11/0 4
S
D P R4 4 P R 16 3 *B T D -05 T C 1 B
P Q7 1 A 1 7. 4 K _ 1 % _0 4 G
P R5 0 P R1 6 0 G
2
MT D N 7 00 2 Z H S106 R0 K _ 04 7 6 . 8K _1 % _ 04
V C H G -S E L [ 2 7] W240HU
S
S P Q2 6
1 5
10 0 K _ 04 1 0K _ 0 4 MT N7 0 0 2Z H S 3
P Q 7 0B
C T L1 4
D
M T D N 7 0 0 2Z H S 6 R 3 6 3
2
D D P Q3 4
P Q 7 0A 3 G M T N7 0 02 Z H S 3 1
5 2 J BATTA2
G G M TD N7 0 0 2Z H S 6 R D P R 1 79 *2 8 mi l _ 06
[ 2 7 ] C H G_ E N 6-21-D34B0-105
S
S S P C2 6 P R4 6 B T D-0 5 TI 1 G
4 1 5
1
[ 2 7] C E L L_ C ON TR OL G
0 . 0 1u _ 5 0V _X 7 R _0 4
P J4 S P Q 7 1B 1M _ 04 S G ND 6
4
*O P E N -1 m m P R4 5
M T D N7 0 0 2Z H S 6 R
2
1M _0 4
V D D3 [ 1 3, 2 2 , 2 4, 2 7 , 3 1, 3 2 ]
S GN D 6 VA [3 1 ]
V I N [ 11 , 3 0 , 3 1, 3 2 , 3 3, 3 4 , 3 5, 3 6 , 3 7]
S GN D 6
Charger, DC In B - 39
Schematic Diagrams
Click Board
CLICK BOARD
CLED_ACI N CLED_BAT_CHG
CLED_PWR CLED_BAT_FULL
CR1 CR2 CR3 CR4

CC1 CC2 CC3
0.1u_16V_Y5V_04 *0. 1u_16V_Y5V_04 *0.1u_16V_Y5V_04 *220 _04 *220_04 P OWER ON *220_04 *220_04
C5VS C5VS CVDD3 BAT LED
3
1 L ED
CD27 CD26
2
SG
CGND CGND CGND
SG
Y
Y
CJ_TP1 CJ_TP2 CJ_TP3 *KPB-3025YSGC *KPB-3025YSGC
1 1 1
4
CTP_DATA CTP_CLK CLED_PWR 11/ 04 11/04
2 CTP_CLK 2 CTP_DATA 2 CLED_ACIN
3 3 CTPBUTTON_L 3 CLED_BAT_FULL
4 4 CTPBUTTON_R 4 CLED_BAT_CHG
85201-04051 5 5
6 6
Sheet 39 of 43 CGND 85201-06051 *85201-06051 CGND CGND CGND CGND
Click Board 6-20-94A50-104

6-20-94AA0-104
CGND CGND 6-52-55002-042
6-52-55002-04E
6-52-55002-042
6-52-55002-04E
6-20-94A70-104 6-21-91A00-106 6-21-91A00-106
6-21-91A20-106 6-21-91A20-106
CSW1~4
2 4
1 3
LIF T RIG HT LIFT RIGH T
KEY KE Y KEY KEY
CSW1 CSW2 CSW3 CSW4
TJG-533-S-T/R TJG-533-S-T/R *TJG-533-S-T/ R *TJG-533-S-T/ R
1 2 1 2 1 2 1 2
3 4 CTPBUTTON_L 3 4 CTPBUTTON_R 3 4 CTPBUTTON_L 3 4 CTPBUTTON_R
5
6
5
6
5
6
5
6
CGND CGND CGND CGND
6-53-3050B-042 6-53-3050B-042 6-53-3050B-042 6-53-3050B-042
CH3 CH1 CH4 CH2 CH5 CH6

2 9 2 9 2 9 2 9 C95D95 HO-165X94_5NP
3 8 3 8 3 8 3 8
4 1 7 4 1 7 4 1 7 4 1 7
5 6 5 6 5 6 5 6
MTH237D91 MTH237D91 MTH237D91 MTH237D91
CGND CGND CGND CGND CGND CGND CGND CGND
B - 40 Click Board
Schematic Diagrams
Audio Board/USB
USB PORT
A _ U S B V CC A L5 A _U S B V C C 2
H C B 1 6 08 K F -1 2 1T 2 5 60 mil
A _U S B V C C
AU 1 +A C 1 A C7
A_ 5 V 5 6 50 mils
F L G# V O UT 1
1 00 u _ 6. 3 V _ B _ A 0. 1 u _ 16 V _ Y 5 V _ 04
5 0mi ls 2 7
V I N 1 V O UT 2
A C5 A C6 A J _ US B 1
A C9 3 8 A R 10 *1 0m i l _0 4 1
V I N 2 V O UT 3 V+
0. 1 u _ 16 V _ Y 5 V _ 04 0. 1 u _ 16 V _ Y 5 V _ 04 A L 61 A GN D
1 0u _ 1 0V _ Y 5V _ 0 8 4 1 A U S B _ P N2 4 3 A U S B _ P N2 _ R 2
E N# G ND DA T A _ L
R T9 7 1 5B G S AU SB_ PP2 1 2 A U S B _ P P 2 _R 3
DA T A _ H
A GN D A G ND A GN D A G N D A G ND *A W C M2 0 12 F 2 S -1 61 T 0 3
4
G ND 2
G ND 4
6-02-09715-920
GN D1
GN D3
GN D
A R 11 *1 0m i l _0 4
U S 04 0 3 6B C A 0 81
PIN SWAP
G ND1
GN D2
G ND3
GND 4
6-21-B49C0-104
6-21-B49B0-104
A GN D
TO M/B AUDIO JACK
Sheet 40 of 43
5 A J_ M I C 1
A MI C 1 -R
A MI C _S E N S E
AL 4 F C M1 0 05 K F -1 2 1T 0 3
4
3 R Audio Board/USB
A MI C 1 -L AL 6 F C M1 0 05 K F -1 2 1T 0 3 2
6 L
1
AC 1 0 A C4 2 S J -T3 5 1 -S 2 3
A_ 5 V A J _ A U D I O1
1 0 0p _ 5 0V _ N P O_ 0 4 1 00 p _ 50 V _ N P O _0 4
MIC IN 6-20-B2800-106
A M I C 1 -R 1
A M I C 1 -L 2
3
BLACK
4
AH E A D P H ON E -R A H P _ S E NSE A _A U D G
AH E A D P H ON E -L 5
AM IC_ S E N S E 6 A S P K _H P # 5 A J_ H P 1
AS P K _H P # 7 4
AH P _ S E NS E 8 A H E A D P H O N E -R 3
A R3 68 _ 0 4 A L2 F C M1 0 05 K F -1 2 1 T0 3 R
AU S B _ P N2 9
AU SB_ PP2 10 A H E A D P H O N E -L 2
A R5 68 _ 0 4 A L3 F C M1 0 05 K F -1 2 1 T0 3
11 6 L
A S P K OU TR + 12 1
A S P K OU TR - 13 A R9 AR8 A C3 AC 2 2 S J -T3 5 1 -S 2 3
14
8 72 1 3 -14 0 0 G *1 K _ 1% _ 0 4 *1 K _ 1 %_ 0 4 10 0 p _5 0 V _ N P O_ 0 4 10 0 p_ 5 0 V _N P O_ 0 4
A _A U D G A G N D HEA DPHONE
6-20-53A00-114 BLACK 6-20-B2800-106
A _A U D G
AL 7
A C1 4 0 . 1 u_ 1 6V _Y 5V _ 0 4 F C M 1 00 5 K F -1 21 T 0 3
AS P K O UT R+ 1 2
A C1 5 0 . 1 u_ 1 6V _Y 5V _ 0 4
A C1 3 0 . 1 u_ 1 6V _Y 5V _ 0 4 AL 8 A C1 1 A J_ S P K R 1
F C M 1 00 5 K F -1 21 T 0 3 1 00 0 p _5 0 V _ X7 R _0 4 A S P K OU T R+ _R J_SPK1
A C1 6 0 . 1 u_ 1 6V _Y 5V _ 0 4 A S P K OU TR - 1 2 A S P K OU T R-_ R 1 2 1
2
8 5 20 4 -0 20 0 1
A C8 A C1 7 P C B F o o t p rin t = 8 52 0 4 -02 R
A GN D A _A U D G 18 0 p_ 5 0 V _N P O_ 0 4 18 0 p _5 0 V _ N P O_ 0 4
6-20-43150-102
6-20-43110-102
A _A UD G
AH 1 A H3
C 5 9D 59 C5 9 D5 9 AH 2 AH4
2 9 2 9
3 8 3 8
4 1 7 4 1 7
5 6 5 6
M TH 2 76 D 1 1 1 MT H 2 7 6 D 1 11
A GN D A GN D A G ND A G ND
Audio Board/USB B - 41
Schematic Diagrams
Power Switch & LID Board

POWER SW & LED & HOT KEY
S _3 . 3 V S S _ 3 .3V
POWER
SWITCH LID SWITCH IC S D2
S _ 3. 3V S S _ 3 . 3V LED
C
SR 2 *B A V 9 9 RE C TIF I E R
S _ 3. 3 V S S _ 3 .3V S _ 3. 3V
SJ _ SW 1 2 2 0 _0 4
2 0mi l SR 1 1 00 K _ 1 %_ 0 4 AC
1 SJ _ SW 2
2
3
S M _B T N #
1
20 mi l 20 mil 2 0m il SU 1
S W E B _W W W # 1 2 S L I D _S W #
4 S W E B _E M A I L # 2 S M _B T N# S C6 V CC OU T
5 3
G ND
S L ID_ S W # SW EB_ W W W #
A
6 4
A
S W E B _ E M A IL# 0.1 u _ 16 V _ Y 5 V _ 0 4 S C2 SC 1
7 SAP_ O N S M GN D 5 S L I D_ S W # MH 2 48 -A L F A -E S O
8 6
3
S D3 SD 1 0 .1u _ 1 0V _ X 7 R_ 04 * 10 0 p_ 5 0 V _N P O_ 0 4
9 S M GN D 7 S A P _ ON S M GN D
S _ V IN * HT -1 50 NB -DT S M GN D S MG ND
10 8 HT -1 50 N B -DT
S M GND S M GN D
C
* 50 5 0 0-0 1 0 41 -0 0 1L 8 8 48 6 -0 80 1 6-52-56001-023
Sheet 41 of 43 6-20-94K10-108
6-52-56001-028
6-52-56000-020
6-52-56001-023
6-52-56001-028
S M GND
SU1, SU2
1 0 pin & 8 pi n co- la y 6-52-56001-022 6-52-56000-020 6-02-00248-LC2
Power Switch & LID S MGN D S M GND
6-52-56001-022 6-02-00268-LC1 3
Board 1 2
FOR E5128Q FOR E4120Q/E5120Q
6-53-3150B-245 6-53-3150B-245 6-53-3150B-245 S_ VIN 6-53-3150B-245

HOT KEY 6-53-3050B-241
6-53-3050B-240
6-53-3050B-241
6-53-3050B-240
6-53-3050B-241
6-53-3050B-240
6-53-3050B-241
6-53-3050B-240
POWER BUTTON WEB_WWW# WEB_EMAIL# S R3
AP_KEY#
SPW R _ SW 1 SW W W _ SW 1 S M A I L _S W 1 *1 0 0 K _1 % _ 04 SAP_ SW 1
T J G-5 33 -S -T / R T JG -5 33 -S -T / R 11/04 T J G-5 3 3-S -T/ R T J G-5 33 -S -T /R
1 2 S M_ B T N# 1 2 SW EB_ W W W # 1 2 SW EB_ EM AIL # 1 2 SAP_ O N
3 4 3 4 3 4 3 4
SC 4 SC 3 SC 5 S R5
5
6
5
6
5
6
5
6
PSW1~8 S R4 *4 7 K _ 04
0 .1 u_ 1 6V _Y 5V _ 0 4 0 .1 u _1 6 V _ Y 5 V _0 4 0_ 0 4 0 . 1 u_ 1 6 V _Y 5 V _0 4
3 1
4 2
S MGN D S M GN D S M GND S MGN D S M GN D S M GN D S M GN D

S MG ND
S MGN D
FOR E4120Q/E5120Q
POWER BUTTON
SPW R _ SW 2 S M H1 S M H3 S M H4
* TJ G-5 3 3 -S -T/ R S MH 2 S M H5 2 9 2 9 2 9
1 2 S M_ B T N# H7 _ 0 D2 _3 H 7_ 0 D2 _ 3 3 8 3 8 3 8
3 4 4 1 7 4 1 7 4 1 7
5 6 5 6 5 6
5
6
PSW1~8 MT H 23 7 D8 7 M TH 23 7 D8 7 M TH 2 37 D1 1 8
3 1 S MGN D S MG ND S MG ND S MG ND
4 2
S MGN D
6-53-3150B-245 S M GND S M GN D
6-53-3050B-240
6-53-3050B-241
FOR E5128Q
B - 42 Power Switch & LID Board
Schematic Diagrams
External ODD Board

ODD BOARD FOR E5120Q
QJ _O D D2 Q J _O D D1
S1 S1
S2 Q J _SATA_ TXP1 S2
S3 Q J _SATA_ TXN 1 S3
S4 S4
S5 Q J _SATA_ RXN 1 S5
S6 Q J _SATA_ RXP1 S6
S7 S7
QG N D Q GN D
P1
P2
P3
Q _5 VS
Q J _O DD _ DETEC T#
Q _5 VS
P1
P2
P3
Sheet 42 of 43
P4
P5
P6
Q J _SATA_ OD D _D A# P4
P5
P6
External ODD
1- 16 2 -1 00 5 62 2 4 20 01 - 1 Board
PI N PIN
G ND 1 ~2 =W G N D QG N D Q GN D G ND 1 ~3 =Q G ND
6-2 1-1401 0-013

6 -21-13 A00-013 6-2 1-1402 0-013
6-2 1-1403 0-013
Q _5 VS
QC 2 QC 1
0 . 1u _1 6 V_Y 5 V_0 4 0 . 1u _1 6 V_Y 5 V_0 4
Q GN D
QH 1 Q H4 QH 3 QH 2
C2 3 7D 91 C 23 7D 9 1 C6 7D 6 7 C6 7D 6 7
Q G ND Q G ND
External ODD Board B - 43
Schematic Diagrams
Power Sequence
W240HU/W250HUQ-D02 POWER ON SEQUENCE
DD_ ON
768.6us
3. 3V
1.58ms
5V
101.82ms
R SMRS T#
55.18ms 157.83ms (RSMRST# to PWR_BTN#)
PW R_BT N# 202.08ms
118ms
SUS C#
417.1us
1. 5V
123.76us
DD R1.5V _PWR GD
37.14us (SUSC# to SUSB#)

SUS B#
2.91ms
V TT_M EM
Sheet 43 of 43 1.5 VS
385.7us
Power Sequence 3.3 VS

592.6us
757.3us
5V S
1.216ms
1.05 VS
1.216ms
1 .05VS _PWR GD
4.133ms
1.8 VS
1.317ms
1.8VS _PWR GD
1.317ms
1. 05VS_ VTT_ EN
1.05ms
1.05 VS_V TT
1.988ms
0.85 VS
2.816ms
0 .85VS _PWR GD
2.816ms
AL L_SYS _PWR GD
331.52ms
P M_PCH _PWR OK
333.44ms
PM _DRAM _PWR GD
333.44ms
V DDPWR GOOD _R
336.15ms
H_CP UPWR GD
722.9us
VCO RE
1.22ms
DELAY _PWR GD
1.22ms
SYS _PWR OK
1.896ms
PL T_RS T#
1.896ms
B UF_CP U_RS T#
B - 44 Power Sequence

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Schematic Diagrams

System Block Diagram

B - 2 System Block Diagram

CPU 1/7 (DMI, PEG, FDI)

PCI EXPRESS* - GRAPHICS

CAD NOTE: DP_COMPIO and ICOMPO signals

[3 ,8 , 11 ,1 3 , 1 4, 15 , 1 7 ,1 8, 1 9 ,2 0 ,22 ,2 3 ,2 6 ,28 ,3 0 ,3 1,3 3 ,3 4 ,3 5] 3.3 V

CPU 1/7 (DMI, PEG, FDI) B - 3

CPU 2/7 (CLK, MISC, JTAG)

PU/PD for JTAG signals

JTAG & BPM

CAD Note: Capacitor Q8

B - 4 CPU 2/7 (CLK, MISC, JTAG)

CPU 3/7 (DDR3)

DDR SYSTEM MEMORY B

M_A_DQ33 AG5 SA_DQ[32] SA_ODT[3] M_B_DQ33 AM 6 SB_DQ[32] SB_ODT[3]

PZ98827-364B- 01F PZ98827-364B-01F

CPU 3/7 (DDR3) B - 5

CPU 4/7 (Power)

PEG AND DDR

B - 6 CPU 4/7 (Power)

CPU 5/7 (Graphics Power)

Sandy Bridge Processor 5/7 ( GRAPHICS POWER )

All VAXG = 33A R 11 9

DDR3 -1.5V RAILS

CPU 5/7 (Graphics Power) B - 7

CPU 6/7 (GND)

Sandy Bridge Processor 6/7 ( GND )

PZ9882 7-364 B- 01F PZ98827- 364B-01 F

B - 8 CPU 6/7 (GND)

CPU 7/7 (RESERVED)

Sandy Bridge Processor 7/7

0:Enabled; An external Display Port device is

PEG DEFER TRAINING J20 D R A M R S T _ C N TR L

CPU 7/7 (RESERVED) B - 9

SO-DIMM A CHANGE TO STANDARD

PANEL CONNECTOR 30Pin & 40 Pin Co-layout--LED

FOR INTEL GRAPHIC

System Power Management

Digital Display Interface

Boot BIOS Strap

AH 1 2 TP1 2 R SVD 1 2 AV3 1 8

11/ 01 R 43 9 *0 _ 0 4 3.14V 3.3V 3.47V

CougarPoint power supply range CougarPoint - M (POWER) Vo lt age R ai l Vol ta ge S0 I cc ma x Cur re nt ( A)

Clock and Miscellaneous

BB38 VSS [179] VS S[279] M38 AD 10 VS S[19] VSS [98] A M36

New Card, Mini PCIE

MINI CARD WLAN 20 mil

New Card, Mini PCIE B - 23

CCD, 3G, TPM

CCD, 3G, TPM

B - 24 CCD, 3G, TPM

Card Reader/LAN JMC251C

*10 u_ 6. 3V _ X5R _06 *0. 1 u_ 16V _ Y 5V _0 4 *0. 1 u_ 16 V_ Y 5V _0 4 0. 1 u_ 16 V_ Y 5V _0 4

Card Reader/LAN JMC251C B - 25

LAN (JMC251C), SATA HDD, ODD

GIGA LAN (JMC251C) 4

SATA HDD SATA ODD

B - 26 LAN (JMC251C), SATA HDD, ODD

USB 3.0 NEC, USB Charger

USB 3.0 NEC, USB Charger B - 27

Audio Codec ALC269

10 u_ 6. 3V _ X5R _06 0. 1 u_ 16V _ Y 5V _0 4 *0. 1 u_ 16 V_ Y 5V _0 4 0. 1 u_ 16 V_ Y 5V _0 4

560u_2. 5V_6. 66. 65. 9