SREENIVASA INSTITUTE OF TECHNOLOGY AND MANAGEMENT STUDIES

(AUTONOMOUS): CHITTOOR
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

III Year B.Tech I semester L T P C

0 0 3 2
16ECE315 DIGITAL DESIGN THROUGH VERILOG HDL
Course Objectives:
 The course intends to provide an overview of the principles, language constructs and
programming fundamentals of Verilog HDL.
 To design the digital systems using Gate level, Data flow, Switch level and Behavioral modeling
styles.
 To understand the concepts of User Defined Primitives.
 To get the knowledge on Task, Functions, Compiler Directives and Delay models.

UNIT-1: Overview of Verilog HDL, Hierarchical modeling concepts, Levels of Design Description,
Programming Language Interface (PLI), Basic concepts, Lexical Conventions, Data types, modules and
ports, Operands & Operator types.
.
UNIT-2:
Gate Level Modeling: Gate types, Basic gates and Tri state gates, Array of instances, Design examples,
Gate delays, Design of flip flops with gate primitives.
Dataflow Modeling: Introduction, Continuous Assignment, Delays, Design Examples – 4 to 1 MUX , 4
bit adder.

UNIT III: Behavioral Modeling: Introduction, Initial Construct, Always Construct, Procedural
assignments - Blocking and Non-Blocking Assignments, Timing control, Conditional statement,Case
statements, loops, sequential and parallel blocks, Procedural Continuous assignments, assign – deassign,
force – release. Design examples – 4x1 multiplexer, 4 bit counter.

UNIT IV:
Switch Level Modeling: Basic Transistor Switches, CMOS Switches, Bi-directional Gates, Power and
ground, Resistive switches, Delay specifications,Examples of switch level modeling.
User Defined Primitives: UDP basics, Combinational UDP, Sequential UDP.

UNIT V: System Tasks, Functions and Compiler Directives: Differences between Tasks & Functions,
Disable Statements, Named Events, Hierarchical path name, Delays - Types of Delay models, Path delay
modeling, Compiler Directives. Advanced Design examples using Verilog HDL – Up-Down Counter,
ALU, Barrel Shifter, Floating Point Encoder.

Course Outcomes:
 Ability to design combinational and sequential systems using Verilog HDL through various level
of modeling.
 An ability to generate and utilize UDPs in designing digital systems.
 Gain the knowledge on Task, Functions, Compiler Directives and use them in designing digital
systems using Verilog HDL.

TEXT BOOKS:
1. Verilog HDL, Samir Palnitkar, 2nd Ed., Pearson Education, 2009.
2. Design Through Verilog HDL, T.R.Padmanabhan, B.Bala Tripura Sundari , Wiley Interscience,
2009.

REFERENCE BOOKS:
1. Verilog HDL Primer, J.Bhasker, 3rd Ed., B.S.Publications, 2008.
2. Verilog Digital System Design, Zainalabdien Navabi, 2nd Edition. McGraw Hill, 2005.
3. Digital Design Principles and Practices , 3rd Ed., 2005, John F. Wakerly, PHI/ Pearson Education
Asia, New Delhi.
4. Fundamentals of Logic Design with Verilog Design– Stephen. Brown and Zvonko Vranesic,
TMH, 2nd Edition 2010.
5. Advanced Digital Logic Design using Verilog, State Machine & Synthesis for FPGA – Sunggu
Lee, Cengage Learning , 2012.