Bandgap 1

EE6378 Power Management Circuits
Lecture 4: Voltage
g References
I t
Instructor:
t Prof.
P f Hoi
H i Lee
L
Mixed Signal & Power IC Laboratory

Mixed-Signal
Department of Electrical Engineering
The University of Texas at Dallas
Introduction
Here, we will learn to build a reference voltage to provide a stable
and accurate supply voltage. The voltage reference is an
electronic circuit to provide an accurate and stable DC voltage
that is very insensitive to the change in supply voltage and
temperature
How accurate is a voltage reference? E.g. Weston cell is an

electrochemical device which provides a reproducible voltage of
1.018636 V at 20oC with a small temperature coefficient of 40
ppm/oC. For integrated circuit implementation, active solid-state
de ices can achie
devices achievee a tempco of 1 4 ppm/oC if appropriate
1-4
compensation technique is employed
Note
• To minimize error due to self-heating, voltage reference usually
operates with modest current (e.g. < 1mA)
• Tempco
p = temperature
p coefficient,, usually
y expressed
p pp oC
in ppm/
o -6 o
(parts per million/ C or 10 / C
EE6378 Lecture 4 © 2009 H. Lee pg. 2

Overview
Performance Requirements
Zener Diode Voltage Reference
Bandgap Voltage References
Bandgap Voltage References Implemented in
CMOS technologies
Performance Parameters (1)
The primary requirements of a voltage reference are accuracy and

stability. Some qualitative parameters are:
Load Regulation = ΔVo/ΔIo (usually expressed in mV/mA or mV/A) or

Load Regulation = 100(ΔVo/ΔIo) (in %/mA or %/A)
Line Regulation = ΔVo/ΔVin (usually expressed in mV/V) or

Line Regulation = 100(ΔVo/ΔVin) (in %/V)
Power Supply Rejection Ratio (PSRR) is a measure of the ripple in the

reference voltage due to the ripples in the supply voltage
Vri
PSRR = 20 log10 (in dB)
Vro

Example of line regulation / supply-voltage dependence at VDD = 3.3, 4.15

and 5V (step size of 0.85V)
VDD=5V
VDD=4.15V
VDD=3.3V
Line regulation at T = 27o C is

Vref (VDD = 5V ) − Vref (VDD = 3.3V ) 1.201 − 1.176
= = 14.7mV / V
5 − 3.3 5 − 3.3
The maximum (Vref(max)) and minimum (Vref(min)) reference voltages are

1.1761V and 1.1731V, respectively. The reference voltage at T = 27oC
(Vref) is
i 11.1761V. The ttempco iin ppm//oC can b
1761V Th be ffound
dbby
Vref (max) − Vref (min) 106 1.1761 − 1.1731 106

Tempco = × = × = 25.5 ppm /O C
Vref (Tmax − Tmin ) 1.1761 (100 − 0)

Overview
CMOS technologies
Review on Zener Diode Voltage Reference
The Zener diode described in Lecture 2 can be considered as a

voltage reference. Since the breakdown voltage due to Zener
breakdown mechanism has a negative temperature coefficient, and
the breakdown voltage due to the avalanche multiplication has a
positive coefficient, the reference voltage is somewhat independent
of the change of temperature
rz Rs Rs r z
Vo = Vin + VZK − IL
Rs + r z Rs + r z Rs + r z
ΔVo rz
Line Regulation = =
ΔVin Rs + rz
ΔVo Rs r z
Load Regulation = =-
ΔI L Rs + r z

Improved Zener Diode Reference (1)
In the case of Zener diode, the output voltage Vo heavily depends on

the load current IL, which in most cases are not good. It would be
better if we could shield the Vz from the influence of the load. This
can be done with the help of an op amp as shown below. This
method refers to self regulation which shifts the burden of line and
load regulations from the diode to the op amp
Improved Zener Diode Reference (2)

By
B iinspection,
ti
R2 24k
Vo = (1 + )Vz = (1 + )6.2 = 10V .
R1 39k
The output voltage is also adjustable
via R2 Vo = (1 +
R2
)Vz = (1 +
24k
)6.2 = 10V .
The load current IL is supplied
pp from the R1 39k
opamp such that the current flowing

through the Zener diode is almost
constant at
V − Vz 10.0 − 6.2
Iz = o = = 1.15mA.
R3 3.3k
Since the diode current is independent
p
of the load current, the diode voltage is
insensitive to the load
R3 can be raised to avoid unnecessary
power wastage and self-heating
self heating effects

Load Regulation (1)
The load regulation is directly related to the output
impedance. To find Ro, we suppress the input source
Vz and apply the test-voltage technique. By voltage
divider formula:
R1 // rin
vN = v
R1 // rin + R2
Summing currents at the output node

v − v − Av N − v
i+ N + =0
R2 ro
Eliminating vN and solving for the Ro=v/I, we obtain

ro
Ro =
1 + [( A + ro / R1 + ro / rin ) /(1 + R2 / R1 + R2 / rin )]
ro R1
≈ where b =
1 + Ab R1 + R2
Load Regulation (2)
Typically rin is in the MΩ range or

greater, R1 and R2 are in kΩ range
and ro is on the order of 102 Ω. The
t
terms ro/R1, ro/r
/ in, and
d R2/r
/ in can thus
th
be ignored to yield Ro≈ro/(1+Ab)
The load regulation Ro≈rro/(1+Ab)

which is much smaller than the Zener
diode voltage reference without
p p
opamp
Since ro and A are frequency

dependent, so are the load
regulation. In general, load regulation
tends to degrade with frequency

Thermal Stability (1)
Thermal stability is one of the most demanding performance
requirement of voltage references due to the fact that semiconductor
components are strongly influenced by temperature
The forward-bias
for ard bias voltage
oltage VD and ccurrent
rrent ID of a silicon pn jjunction,
nction
which forms the basis of the diodes and BJTs, are related as
VD=VTln(ID/IS), where VT is the thermal voltage and IS is the saturation
current. Their expressions
p are
VT = kT / q and IS = BT 3 exp( −VG 0 / VT )
where
k=1.381×10-23 is Boltzmann’s constant
q=1.602 ×10-23 C is the electron charge
T is the absolute temperature
p
B is a proportionality constant
VG0 = 1.205V is the bandgap voltage for silicon
Thermal Stability (2)
The temperature coefficient (TC) of the thermal voltage:

∂VT k
TC(VT ) = = = 0.0862mV/ oC
∂T q
ID V
∂[ln ] ∂(3 lnT − G 0 )
∂VT I IS V VT V − VD 3k
TC(VD ) = ln( D ) + VT = D − VT = -(( G 0 + )
∂T IS ∂T T ∂T T q
Assume VD=650mV at 25oC, we get TC(VD) ≈ -2.1mV/oC.
TC(VT) have a positive tempco and TC(VD) have a negative tempco,

so these two equations form the basis of two common approaches to
thermal stabilization,, namely,
y, thermal compensated
p Zener diode
references and bandgap references

Thermally Compensated Zener Diode Reference
Idea of thermally compensated Zener diode is to connect a forward-

biased diode in series with a Zener diode having an equal but
opposing tempco as shown below
Since TC(Vz) is a function of Vz and Iz. We can fine tune Iz to drive

the tempco
p of the composite
p device to zero. In this case,, a 7.5mA is
used to give a reference voltage of Vz = 5.5+0.7 = 6.2V with tempco
ranging from 100ppm/oC to 5ppm/oC
Overview
CMOS technologies

Bandgap Voltage Reference (1)
Since the best breakdown voltages of the Zener diode references
range from 6 to 7V, they usually require supply voltages on the order
of 10V to operate. This can be a drawback in systems powered from
l
lower supplies,
li suchh as 5V.
V Thi
This lilimitation
i i iis overcome b
by b
bandgap
d
voltage references, so called because their output is determined
primarily by the bandgap voltage of silicon VG0 = 1.205V
Bandgap Voltage Reference (2)
Addition of the voltage drop VBE of a base-emitter

junction, which has a negative tempco, to a voltage
proportional to the thermal voltage VT, which has a
positive
iti ttempco, tto generate
t a reference
f voltage,
lt which
hi h
is independent of temperature

Fundamentals
As TC(VBE) ≈ -2.1mV/°C and TC(VT) = 0.0086mV/°C, then zero tempco is

achieved at a particular temperature (e.g. T=300K):
VBG = VBE + KVT

i.e. TC (VBG ) |300K = TC (VBE ) + K ⋅ TC (VT ) = 0
− TC (VBE ) 2.1
⇒ K= = = 24.4
TC (VT ) 0.086
If for a particular transistor with certain bias current such that VBE =
650mV, then
VBG = VBE + KVT = 0.65 + 24.4(0.0259) = 1.28 V.

Note that VT = kT/q ∝ T, i.e. VT is proportional to absolute temperature.
We call VT a Proportional To Absolute Temperature voltage, or in short,
PTAT voltage
Bandgap Voltage Reference Circuit (1)
From the figure, the emitter area of Q1 is n

times as large as the emitter area of Q2,
then Is1/Is2 = n
By op amp action with identical collector
resistances, the collector currents are also I C 2 I S1
identical, i.e. IC1 = IC2. Ignore the base IR3 = VBE 2 − VBE1 = VT ln( ) = VT ln(n)
I C1 I S 1
currents we have KVT = R4(IC1+IC2) = 2R4I
currents,
I I
IR3 = VBE 2 − VBE1 = VT ln( C 2 S1 ) = VT ln(n)
IC1IS1
Combine two equations give
2R4 VT R
K= = 2 4 ln(n)
VT R3 R3
R
⇒ VBG = VBE 2 + KVT = VBE 2 + (2 4 ln n)VT
R3

Bandgap Voltage Reference Circuit (2)
From
F the
th previous
i di
discussion,
i ffor a zero
tempco voltage reference VBG, K ≈ 24,
with n = 4, then
R4 K 24.4
= = ≈ 8.8
R3 2 ln 2 2 ln 4
Note that I = VTln(n)/R3 ∝ VT, I is a

PTAT current
Brokaw Cell
Brokaw cell is commonly used bandgap-cell

realization
li ti circuit
i it and
d iis shown
h iin th
the fi
figure
The function of op amp is replaced by Q3,

Q4 and Q5. Q3 and Q4 form a current mirror
to enforce the collector currents of Q1 and
Q2 are identical
The emitter follower Q5 raises the reference

voltage to Vref = (1+R1/R2)VBG

Stability of a Bandgap Reference
In a bandgap reference, there exists 2

feedback loops, 1 positive loop and 1
negative loop.
For the negative loop (the outer loop),

R2 + 1 / g m1
Negative Loop Gain = A( s )
R1 + R2 + 1 / g m1
R2 + 1/ gm1
Negati e Loop Gain =
Negative A(s )
R1 + R2 + 1/ gm1
For the positive loop (the inner loop),

1/ gm1
Positive Loop Gain = A(s )
R1 + 1/ gm1
For stability, we must have a negative

loop gain magnitude > positive loop
gain magnitude. This is true as
((a+c)/(b+c))>(a/b) for b>a
Stability of Simple Brokaw Cell (1)
If we neglect R3, then clearly Q1 and Q2 form a differential pair with

p
positive and negative
g terminals tied together
g
Above is the way to break the loop for measuring loop gain. The
circuit should have a DC closed loop and AC open loop. The DC
closed loop p is for biasing
g and the AC loopp is to measure loop
pggain

Stability of Simple Brokaw Cell (2)
With the presence of R3, the positive loop looks like an amplifier with
degenerated emitter ⇒ the gain is smaller than that with R3.
Therefore, negative loop gain magnitude > positive loop gain
magnitude, i.e. stability requirement is satisfied
Cc is the compensation capacitor. Here, dominant pole
compensation is employed
Overview
CMOS technologies

CMOS Bandgap References (1)
CMOS is the dominant technology for both digital and

analog circuit design nowadays
Independent bipolar transistors are not available in
CMOS technology
CMOS voltage reference, however, can be achieved by
making use of the concept of voltage reference. These
CMOS circuits rely on using well transistors.
transistors These
devices are vertical bipolar transistors that use wells
as their bases and the substrate as their collectors
These vertical bipolar well transistors have reasonable current gain

(≈ 25), but very high series base resistance (≈ 1kΩ/ ) due to the fact
that the base contact is far away from the base
The maximum collector current is thus limited to less than 0.1mA to
minimize errors due to the base resistance

Two possible implementations:
For
F example,
l ini th
the n-wellll CMOS implementation,
i l t ti what
h t is
i VBG off the
th
reference circuit?
VBG = VEB 2 + VR 2
Assume the op amp has very large gain
and very small input currents such that its
input terminals are at the same voltage,
then VR 3 = VEB 2 − VEB1 = ΔVEB
VR 3 = VEB 2 − VEB1 = ΔVEB
Since the current through R1 is the same

as in R3
VR1 VR 3 R1 R
= or VR1 = VR 3 = 1 ΔVEB
R1 R3 R3 R3
R1
VBG = VEB 2 + ΔVEB
R3

CMOS Voltage References (5)
In CMOS realization, the bipolar

transistors are often taken the same
size, and different current densities
(IC/IS) are realized by taking R1 greater
than R2, which causes I2 to be greater
than I1:
I2 R1
VR1 = VR 2 ⇒ I1R1 = I2R2 or =
I1 R2
kT I2
ΔVEB = VEB 2 − VEB1 = ln( )
q I1
R1 kT R R R
⇒ VBG = VEB 2 + ln( 1 ) with K = 1 ln( 1 )
R3 q R2 R3 R2
Example
Find the resistances of a bandgap voltage reference based on the

CMOS n-well process where I1 = 5μA, I2 = 40μA and VEB = 0.65V at
T = 300K.
300 Assume VBG = 1.24V
12
Ans. R1 = 118kΩ, R2 = 14.8kΩ and R3 = 10.1kΩ

Other CMOS References
Current mirror enforces equal

currents at M1, M2 and M3
Voltage clamping by M4 and M5
to enforce V1=V2
PTAT loop formed by Q1, Q2 and

R1
I = VT ln(N ) / R1
R2
Vref = VEB 3 + ln(N ) ⋅ VT
R1
Cascode current mirror or other
forms for better current matching
at different supply voltages
Current Mirror with Op Amp
In CMOS reference using

current mirror with op amp,
an op amp is used to
enforce the drain voltage of
M1 the same as of M2. This
allows a better current
matching of drain currents of
M1 and M2

Error Sources in Voltage-Reference Design
Current mirror
Voltage-clamping
Voltage clamping circuit
BJT emitter area ratio (BJT matching)
Resistor ratio (resistor matching)
Base current
Base resistance
Systematic offset at different supply voltages
Random offset of devices
Temperature gradient within a chip
Design Considerations: BJTs
Closely packed common-centroid layout

Large
L Nddoes not provide
id significant
i ifi change
h d
due to the
h llogarithm
ih
relation
Generally, N=8 is chosen based on chip area consideration

Design Considerations: Resistors
Matching is important to
obtain an accurate resistance
ratio
Square-like common-centroid
layout
Typical Low-Voltage Implementation
Error-amplifier current mirror

enforces VA = VB
Min VDD = VREF + |Vov,M2|
Offset voltage → error
Offset voltage = function of VTH,

mobility and transistor size →
temperature dependent
Use simple
p amplifier
p
Reduce both systematic and

random offset

Offset Voltage Consideration
VT ln(N ) + VOFF
I=
R1
R2
⇒ Vref = VEB 2 + ( )[VT ⋅ ln(N ) + VOFF ]
R1
A larger
l N iis used
d tto minimize
i i i
the required R2/R1, and the
effect of the amplifier offset
I
Increase chip
hi area
Base Resistance Consideration
Large base resistance of

parasitic vertical BJT
Diode-connected BJT ≠ VEB
As mentioned before, I <

0.1mA
Not due to low-power

design, but due to reduce
voltage across RB
On layout, more N-well

contacts to reduce RB

Base Current Compensation
β is small in CMOS technology
IC ≠ IE and IC is a function of β
Introduced β in IC causes extra

errors and temperature
dependence
Base current compensation by a

dummy transistor Q1D
IE of Q1 = I + I/β
IC of Q1 = I
Q1D must match with Q1
Resistor Trimming
Resistor
R i ratio
i can b
be fi
fine-tuned
dbby
using a series of resistor network
associated with fuse
By burning the fuse, the resistor

value can be adjusted to fine-tune
th reference
the f voltage
lt and
d the
th
temperature with zero tempco to a
particular value

Buffered Voltage Reference
Series
Series-shunt
shunt feedback
High output current to drive resistive load
Low output resistance
Isolation to reduce cross-talk through reference circuit
Current Source Generated by a Voltage

Reference
Series-series feedback
I = VREF/R
VMIN = Vov + VREF

CMOS Bandgap Reference with Sub-1-V
Operation (1)
R3 R
VREF = ( )(VEB 2 + ( 2 )ln(N ) ⋅VT )
R2 R1
R1, R2 & R3 of same material
Good matching R1 and R2 for

optimizing tempco
Good matching R2 and R3 for

adjusting
dj ti theth value
l off VREF
M1, M2 & M3 of equal W, L
VREF ≈ 0.5-0.7 V for matching VDS of

M1-M3 at different VDD
CMOS Bandgap Reference with Sub-1-V

Operation (2)
Native NMOST : VTHN = 0.2V

0 2V
Not available in standard

CMOS technologies

Low-Voltage Design Problem of Error Amplifier
Worst case (smallest) VEB at

maximum operational Worst case (largest) VEB and
temperature | THP| at minimum temperature
|V p
VEB > VTHN + 2Vov VEB < VDD - |Vthp| - 2|Vov|
Low-VTHN (<0.4V) technology VDD(min) = VEB + |VTHP| + 2Vov
B d effect
Body ff t increases
i VTHN
References
H. Banba, et. al. “A CMOS bandgap reference circuit with sub-1-V

operation,” IEEE Journal of Solid-State Circuits, vol. 34, pp. 670-
674, May 1999.
K. N. Leung, et. al. “A sub-1-V 15-ppm/°C CMOS bandgap voltage
reference without requiring low threshold voltage device,” IEEE
Journal of Solid-State Circuits, vol. 37, pp. 526-530, Apr. 2002.
P. K. T. Mok, et. al. “Design considerations of recent advanced low-
voltage low-temperature-coefficient CMOS bandgap voltage
reference,” IEEE Custom Integrated Circuits Conference, Sep. 2004,
pp. 635-642.

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EE6378 Power Management Circuits

Mixed Signal & Power IC Laboratory

 How accurate is a voltage reference? E.g. Weston cell is an

EE6378 Lecture 4 © 2009 H. Lee pg. 2

EE6378 Lecture 4 © 2009 H. Lee pg. 3

Performance Parameters (1)

The primary requirements of a voltage reference are accuracy and

 Load Regulation = ΔVo/ΔIo (usually expressed in mV/mA or mV/A) or

 Line Regulation = ΔVo/ΔVin (usually expressed in mV/V) or

 Power Supply Rejection Ratio (PSRR) is a measure of the ripple in the

EE6378 Lecture 4 © 2009 H. Lee pg. 4

Example of line regulation / supply-voltage dependence at VDD = 3.3, 4.15

Line regulation at T = 27o C is

EE6378 Lecture 4 © 2009 H. Lee pg. 5

Performance Parameters (3)

The maximum (Vref(max)) and minimum (Vref(min)) reference voltages are

Vref (max) − Vref (min) 106 1.1761 − 1.1731 106

EE6378 Lecture 4 © 2009 H. Lee pg. 6

EE6378 Lecture 4 © 2009 H. Lee pg. 7

Review on Zener Diode Voltage Reference

 The Zener diode described in Lecture 2 can be considered as a

EE6378 Lecture 4 © 2009 H. Lee pg. 8

 In the case of Zener diode, the output voltage Vo heavily depends on

EE6378 Lecture 4 © 2009 H. Lee pg. 9

Improved Zener Diode Reference (2)

opamp such that the current flowing

EE6378 Lecture 4 © 2009 H. Lee pg. 10

 Summing currents at the output node

 Eliminating vN and solving for the Ro=v/I, we obtain

EE6378 Lecture 4 © 2009 H. Lee pg. 11

Load Regulation (2)

 Typically rin is in the MΩ range or

 The load regulation Ro≈rro/(1+Ab)

 Since ro and A are frequency

EE6378 Lecture 4 © 2009 H. Lee pg. 12

VT = kT / q and IS = BT 3 exp( −VG 0 / VT )

EE6378 Lecture 4 © 2009 H. Lee pg. 13

Thermal Stability (2)

 The temperature coefficient (TC) of the thermal voltage:

Assume VD=650mV at 25oC, we get TC(VD) ≈ -2.1mV/oC.

 TC(VT) have a positive tempco and TC(VD) have a negative tempco,

EE6378 Lecture 4 © 2009 H. Lee pg. 14

 Idea of thermally compensated Zener diode is to connect a forward-

 Since TC(Vz) is a function of Vz and Iz. We can fine tune Iz to drive

EE6378 Lecture 4 © 2009 H. Lee pg. 15

EE6378 Lecture 4 © 2009 H. Lee pg. 16

EE6378 Lecture 4 © 2009 H. Lee pg. 17

Bandgap Voltage Reference (2)

 Addition of the voltage drop VBE of a base-emitter

EE6378 Lecture 4 © 2009 H. Lee pg. 18

 As TC(VBE) ≈ -2.1mV/°C and TC(VT) = 0.0086mV/°C, then zero tempco is

VBG = VBE + KVT

VBG = VBE + KVT = 0.65 + 24.4(0.0259) = 1.28 V.

EE6378 Lecture 4 © 2009 H. Lee pg. 19

Bandgap Voltage Reference Circuit (1)

 From the figure, the emitter area of Q1 is n

Combine two equations give

EE6378 Lecture 4 © 2009 H. Lee pg. 20

 Note that I = VTln(n)/R3 ∝ VT, I is a

EE6378 Lecture 4 © 2009 H. Lee pg. 21

 Brokaw cell is commonly used bandgap-cell

 The function of op amp is replaced by Q3,

 The emitter follower Q5 raises the reference

How accurate is a voltage reference? E.g. Weston cell is an

Load Regulation = ΔVo/ΔIo (usually expressed in mV/mA or mV/A) or

Line Regulation = ΔVo/ΔVin (usually expressed in mV/V) or

Power Supply Rejection Ratio (PSRR) is a measure of the ripple in the

The Zener diode described in Lecture 2 can be considered as a

In the case of Zener diode, the output voltage Vo heavily depends on

Summing currents at the output node

Eliminating vN and solving for the Ro=v/I, we obtain

Typically rin is in the MΩ range or

The load regulation Ro≈rro/(1+Ab)

Since ro and A are frequency

The temperature coefficient (TC) of the thermal voltage:

TC(VT) have a positive tempco and TC(VD) have a negative tempco,

Idea of thermally compensated Zener diode is to connect a forward-

Since TC(Vz) is a function of Vz and Iz. We can fine tune Iz to drive

Addition of the voltage drop VBE of a base-emitter

As TC(VBE) ≈ -2.1mV/°C and TC(VT) = 0.0086mV/°C, then zero tempco is

From the figure, the emitter area of Q1 is n

Note that I = VTln(n)/R3 ∝ VT, I is a

Brokaw cell is commonly used bandgap-cell

The function of op amp is replaced by Q3,

The emitter follower Q5 raises the reference

In a bandgap reference, there exists 2

For the negative loop (the outer loop),

For the positive loop (the inner loop),

For stability, we must have a negative

If we neglect R3, then clearly Q1 and Q2 form a differential pair with

CMOS is the dominant technology for both digital and

These vertical bipolar well transistors have reasonable current gain

Since the current through R1 is the same

In CMOS realization, the bipolar

Find the resistances of a bandgap voltage reference based on the

Ans. R1 = 118kΩ, R2 = 14.8kΩ and R3 = 10.1kΩ

Current mirror enforces equal

PTAT loop formed by Q1, Q2 and

In CMOS reference using

Closely packed common-centroid layout

Error-amplifier current mirror

Min VDD = VREF + |Vov,M2|

Offset voltage → error

Offset voltage = function of VTH,

Reduce both systematic and

Large base resistance of

Diode-connected BJT ≠ VEB

As mentioned before, I <

Not due to low-power

On layout, more N-well

Introduced β in IC causes extra

Base current compensation by a

Q1D must match with Q1

By burning the fuse, the resistor

High output current to drive resistive load

Low output resistance

Isolation to reduce cross-talk through reference circuit

VMIN = Vov + VREF

R1, R2 & R3 of same material

Good matching R1 and R2 for

Good matching R2 and R3 for

M1, M2 & M3 of equal W, L