Last (family) name: _________________________

First (given) name: _________________________

Student I.D. #: _____________________________

Circle section: Lipasti Kim

Department of Electrical and Computer Engineering

University of Wisconsin - Madison

ECE/CS 352 Digital System Fundamentals

Final Exam Solution

Thursday, May 15, 5:05 PM – 7:05 PM

1. (10 points) Review problems: Standard and Canonical Forms

Assume the following boolean equation. No partial credit will be given.

F(A,B,C) = (AC + B)(A+C) + BC (A+B)

(a) (2 points) Express F in canonical sum-of- minterms form.

Answer: F(A,B,C) = ? m(1,2,4,5,6,7)

(b) (2 points) Express F in canonical product-of- maxterms form.

Answer: F(A,B,C) = ? M(2, 3)

(c) (3 points) Express F in minimized sum-of-products form.

Answer: F(A,B,C) = A + ~BC + B~C

(d) (3 points) express F in minimized product-of-sums form.

Answer: F(A,B,C) = (~A + ~B + ~C)( A + ~B + ~C)

ECE/CS 352 Final Exa m May 15, 2002 1

2. (15 points) Review Problems: Complement representation and arithmetic
(a) (5 points) Find the radix complement and diminished radix complement of the following
hexadecimal number (assume radix r=16, number of digits n = 4). No partial credit will
be given.

(B2A7)16

Answer:
Radix complement: (4D59)16

Diminished radix complement: (4D58)16

(b) (10 points) Add the following 6-digit signed binary numbers, using 1’s complement
representation on the left, then using two’s complement on the right. You must show all
your work, including all arithmetic operations and carries using the space provided.
Indicate whether overflow occurred, and how you determined this condition.

Answer:
(5 points) (5 points)
1’s Complement 2’s Complement

0 0 1 1 1 0 1 0 1 1 1 1 0
1 0 0 0 0 1 1 0 0 1 1 1
+ 0 1 0 1 1 1 + 1 0 1 0 1 1
1 1 1 0 0 0 0 1 0 0 1 0

Overflow: No, sign Overflow: Yes, c5 !=

bits differ c6

ECE/CS 352 Final Exam May 15, 2002 2

3. (25 points) Datapath and Algorithmic State Machine Design (ASM)
(a) (5 points) Describe briefly what functionality the following ASM and data path provide.
Assume the shift register always shifts in zeroes.

____This circuit counts the number of “1” bits in register R, and stores the

____total in register S_____________________________________

(b) (15 points) Provide a one-hot implementation of this ASM in the space to the right.
Minimize your implementation wherever possible.

In (8b)
“0”
RShift
R (8b shift reg) Load
4b Parallel Adder Cin

AllZero
S (4b register) Clear

Init
G
DQ

0 1
G
Clear, Load
AllZero
S? 0, R? In DQ
RShift

AddShift
S? S + R0
R? sr R

Done
0 4b
AllZero

Done =1

ECE/CS 352 Final Exam May 15, 2002 3

 (c) (10 points) Design a fully synchronous circuit to implement the 4-bit parallel adder and
4bit S register in the datapath of the previous problem (shown shaded below). Your
design should include the minimum number of gates, and should be optimized for the
inputs shown in the datapath. Show your work in the space below. You must use the 4
synchronous-reset T flip- flops provided and can use and, or, xor, and inverter gates only.
In (8b)
“0”
RShift
R (8b shift reg) Load
4b Parallel Adder Cin

AllZero
S (4b register) Clear

Cin T Q T Q T Q T Q

~Q ~Q ~Q ~Q
reset reset reset reset
Clear

CLK

ECE/CS 352 Final Exam May 15, 2002 4

4. (20 points) Timing Analysis
Given the following timing parameters, and assuming a fully synchronous design using a
clock signal with 50% duty cycle and negligible clock skew, answer the following questions.
Assume that the propagation delay through the ALU is the longest combinational delay path
in your design. No partial credit will be allotted for this problem.

Delay component Value Explanation

FFsetup 100ps Setup time for pipeline flip- flops
FFdelay 40ps Delay through pipeline flip-flops
Lsetup 75ps Setup time for pipeline master-slave latch
Ldelay 25ps Delay through pipeline master-slave latch
tPHL 15ps High-to-Low propagation delay through single
NAND gate
tPLH 12ps Low-to-High propagation delay through single
NAND gate
ALUdelay 300ps Propagation delay through ALU

(a) (5 points) Assume you are using pipeline flip- flops in your design. What is minimum
clock period of your design?

Minimum clock period 40 + 300 + 100 = 430ps

(b) (5 points) How many levels of NAND gates can you have in other combinational paths in
your flip-flop-based design without increasing the minimum clock period?

Levels of NAND gates 430 ps / 15ps = 28 levels

(c) (5 points) Assume you are using master-slave pipeline latches instead of flip- flops in
your design. What is the minimum clock period of your design?

Minimum clock period (25 + 300 + 75) / .5 = 800ps

(d) (5 points) How many levels of NAND gates can you have in other combinational paths in
your latch-based design without increasing the minimum clock period?

Levels of NAND gates 400 ps / 15 ps = 26 levels

ECE/CS 352 Final Exam May 15, 2002 5

5. (10 points) ALU Design

S0

Full Adder

X
Ai Sum Fi
S1 Y
Cout Ci+1

Ci Cin
Bi
S1
S0

The schematic shown above is an ALU bit slice which can perform both arithmetic and logic
operations by choosing appropriate control signals C0 , S0 and S1 where C0 is a Ci for the least
significant bit. . Let A = An−1 …A1 A0 and B = Bn−1 …B1 B0 are two operands and F =
Fn−1 …F1F0 is the output. Complete the function table below for output F. For each function,
clearly indicate whether the function is an arithmetic operation (A) or a logical operation (L).

Answer: When you analyze the ALU, you will notice that above ALU is applying Function
X(S1 , S0 , Ai, Bi) = S 0 ⋅ Ai + S 0 ⋅ Ai to Input X and Y(S1 , S0 , Ai, Bi) = S1 ⋅ Bi + S1 ⋅ Bi to Input Y
of F.A. If you create a truth table of four input variables, (S1 , S0 , Ai, Bi), and two output
functions X(S1 , S0 , Ai, Bi) and Y(S1 , S0 , Ai, Bi), then you will see that we are applying Ai Bi ,
Ai Bi , Ai Bi , and Ai Bi to input X Y for S1 S0 equal to 00, 01, 10, and 11, respectively. For
Cin of F.A, we apply 0 (logic operation) when S1 S0 equal to 00, and Ci for all other values of
S1 S0 (arithmetic operation for 01, 10, and 11).

S1 S0 C0 = 0 C0 = 1
(L)
0 0 Unused -Do not complete
Ai ⊕ Bi
(A) (A)
0 1 Ai + Bi =Ai- Bi in 1’s Ai + Bi +1=Ai- Bi in 2’s
complement arithmetic complement arithmetic
(A) (A)
1 0 Ai + Bi =Bi- Ai in 1’s Ai + Bi +1=Bi- Ai in 2’s
complement arithmetic complement arithmetic

ECE/CS 352 Final Exam May 15, 2002 6

 (A) (A)
1 1 Ai+Bi Ai+Bi+1

ECE/CS 352 Final Exam May 15, 2002 7

6. (20 points) Programmable Devices and Hazard.
Following is a programmed Programmable Logic Array implementing three functions
F(A, B, C), G(A, B, C) and H(A, B, C). For the remaining of this problem, we will focus only on
F(A, B, C). Warning: NO partial credit may be given for this problem.

F G H
(a) (6 points) Find the sum of product expressions for Function F, G and H.

Answer:

F(A, B, C) = B ⋅ C + B ⋅ C + A ⋅ B ⋅ C

G(A, B, C) = A ⋅ B + A ⋅ C

H(A, B, C) = A ⋅ C + B ⋅ C + A ⋅ B ⋅ C

ECE/CS 352 Final Exam May 15, 2002 8

 (b) (4 points) Draw a Karnaugh map corresponding to the Function F(A, B, C) and identify
all SICS-1 ((single input change static-1) logic hazard(s).

A\BC 00 01 11 10
1 1
0 1 0
1
1 1 0 0

There are three pairs of hazards for ABC={000? 001}, {000? 010}, {100? 110}

(c) (4 points) Find two different sets of product terms that can be added to Function F(A, B,
C) to eliminate all SICS-1 logic hazard(s). Each set should only contain product term(s)
that contributes to eliminate SICS-1 logic hazard(s).

Set 1 = { A⋅B, C }

Set 2 = { A ⋅ B , A⋅ C , A⋅ C }

(d) ( 4 points) Modify the PLA in the previous page to eliminate the SICS-1 logic hazard of
Function F(A,B,C) using one of the set you have found in Part (c). You may use one or
more unprogrammed AND gates, but you are to minimize programming of unused AND
gates whenever possible.

Even though Set 1 has fewer number of terms, Set 1 will require adding a new term to
PLA which implies we need to program one of unused AND gate. However upon a close
inspection, you can see all product terms in Set 2 are already programmed and being used
by other functions. If we use Set 2, there is NO need to use unprogrammed AND gates.
Thus we choose Set 2 to minimize unnecessary logics.

ECE/CS 352 Final Exam May 15, 2002 9

 (e) (4 points) Implement the Function F(A,B,C) on the PAL shown below using minimum
logic. Your implementation should eliminate all SICS-1 logic hazard in Function
F(A,B,C).

ECE/CS 352 Final Exam May 15, 2002 10

7. (10 points) Circuit Analysis
Simulate the behavior of the following circuit by drawing the waveforms for A and B below.
Assume the NOR gates have negligible delay.

Negative edge-triggered D flip- flop

ECE/CS 352 Final Exam May 15, 2002 11

 Flip-Flop Excitation Tables

JK Flip-Flop SR Flip-Flop
Q(t) Q(t+1) J K Q(t) Q(t+1) S R
0 0 0 X 0 0 0 X
0 1 1 X 0 1 1 0
1 0 X 1 1 0 0 1
1 1 X 0 1 1 X 0

D Flip-Flop T Flip-Flop
Q(t) Q(t+1) D Q(t) Q(t+1) T
0 0 0 0 0 0
0 1 1 0 1 1
1 0 0 1 0 1
1 1 1 1 1 0

Basic Identities of Boolean Algebra

1. X + 0 = X 2. X⋅ 1 = X
3. X + 1 = 1 4. X⋅ 0 = 0
5. X + X = X 6. X ⋅ X = X
7. X + X =1 8. X⋅ X = 0
9. X =X
10. X + Y = Y + X 11. X ⋅ Y = Y ⋅ X Commutative Law
12. X + (Y + Z) = (X + Y) + Z 13. X (YZ) = (XY) Z Associative Law
14. X(Y + Z) = XY + XZ 15. X + YZ = (X + Y)(X + Z) Distributive Law
16. X + Y = X ⋅Y 17. X ⋅ Y =X +Y DeMorgan’s Law

Useful Boolean Identities

18. X + XY = X 19. X + XY = X + Y
20. XY + X Y = X 21. XY + X Z + YZ = XY + X Z
22. ( X + Y )( X + Y ) = X ⋅ Y + X ⋅ Y 23. ( X + Y )( X + Y ) = X

Exclusive-Or Identities

24. X ⊕ 0 = X 25. X ⊕ 1 = X
26. X ⊕ X = 0 27. X ⊕ X = 1
28. X ⊕ Y = X ⊕ Y 29. X ⊕ Y = X ⊕ Y
30. X ⊕ Y = Y ⊕ X
31. (X ⊕ Y ) ⊕ Y = X ⊕ (Y ⊕ Z) = X ⊕ Y ⊕ ZX

ECE/CS 352 Final Exam May 15, 2002 12