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Third Semester
(Regulation 2008)
1. Draw the logic diagram for the Boolean expression ((A + B) C )′D using
NAND gates.
10. What are the steps for design of asynchronous sequential circuit?
PART B — (5 × 16 = 80 Marks)
11. (a) Simplify the following Boolean expression using Quine McCluskey
method :
Or
(b) (i) Implement Boolean expression for EXOR gate using NAND and
NOR gates. (8)
12. (a) (i) Explain the gray code to binary converter with the necessary
diagram. (10)
Or
(b) With neat diagram explain BCD subtractor using 9’s and 10’s
complement method. (16)
13. (a) Explain with necessary diagram a BCD to 7 segment display decoder.
(16)
Or
(b) (i) Write the comparison between PROM, PLA, PAL. (6)
14. (a) Design and implement a Mod-5 synchronous counter using JK flip-flop.
Draw the timing diagram also. (16)
Or
2 T 3027
15. (a) (i) Design a comparator. (6)
(ii) Design a non sequential ripple counter which will go through the
states 3, 4, 5, 7, 8, 9, 10, 3, 4 .................. draw bush diagram also.
(10)
Or
(b) (i) Design a parity checker. (6)
(ii) Design a sequential circuit with JK flip-flop. (10)
0|1
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3 T 3027