َْ

ِ
ْ‫ ًِْ
َو رْ ُز‬
ِ ْ‫ب زد‬
 ‫َر‬
My Lord! Advance me in Knowledge and true understanding

MICROPROCESSOR BASED SYSTEM

Lecture1
Dr. Shahrul Naim Sidek
snaim@iiu.edu.my
SECTION 1.1-1.4

Concept of microprocessor based system

• Microprocessor in mechatronics systems
• Function as embedded controller

• Devicesthat uses microprocessors

Evolution / Overview Different Types µP

How does microprocessor evolved, through the years

1st gen. - ENIAC (Electronics Numerical Integrator and Computer)
- made from vacuum tubes

2nd gen. – with the invention of transistors

3rd gen. – with the invention of IC, LSI
4th gen. – developed using VLSI technology
5th gen. -- ??
Evolution / Overview Different Types µP
Evolution / Overview Different Types µP
Apple 68000-8
8 MHz
64-pin side-brazed ceramic DIP (dual in-line package)

This 68000 microprocessor was not manufactured by Apple, but it was

put into separate "Apple" category due to very unusual Apple copyright
on the CPU. The CPU was manufactured by Hitachi as their 68000
processors have similar packaging and chip markings.

Motorola XC68000L (SN807)

64-pin side-brazed ceramic DIP

Rare engineering sample of Motorola 68000 processor. First engineering

samples of 68000 were marked with serial numbers. This specific chip
was manufactured in October 1979 and has serial number 807.

http://www.cpu-world.com/CPUs/68000/
Functional Description : Block Diagram
I/O devices
Interrupt
Parallel I/O Serial I/O Communicates the
Circuitry
CPU with the real
System world (e.g. parallel,
bus serial)
System buses
Timing CPU Memory A collection of wires
that allow access to
the circuitry around
Memory the CPU (Data, add &
ctrl signals)
Stores the instructions and data comprising the program
to be executed. (ROM, RAM – static, dynamic, NVM) Commonly made
available to outside
CPU world for sys
Interprets and executes program instructions in sequence expansion
Functional Description: Memory
Memory By Access Types

Registers: small storage internal to the CPU

Cache: Tightly linked to the CPU – specialized buffer storage
Main memory: Connected to system buses
Secondary memory: On-line (i.e., cd) Fast &
Archival: Off-line Registers
Expensive

Semiconductor Cache

Main

Secondary
Magnetic /
Optic Cheap &
Archival
Slow
Functional Description: Memory (cont)
Memory By Access Technology

Semiconductor
•Random Access Memory (RAM)
•Volatile/non-volatile, Read and write
•Read Only Memory (ROM)
•Non-volatile, Can only be read

Magnetic memory MEMORY ACCESS

•Disk, Tape TECH vs TYPE RAM ROM DISK Tape Optical
Registers X
Optical Cache X
•CD-ROM
Main Memory X X Virtual
Secondary
Memory X X
Archival Storage X X
Functional Description: CPU
Arithmetic-Logic Unit (ALU) Registers – store data
Performs computations Data/Address Registers
Control Unit Instruction Register
Determines the operation to be performed by Program Counter
instruction
Status Register
Coordinates various part of CPU

D0
IR
Ctrl Unit
D7 PC

A0 ALU
SR / CCR

A7
Data bus
Add bus
Functional Description: I/O Device
Mass-Storage Devices
•Hold large quantities of information that cannot fit into the computer’s
•main memory
•Disks, tapes, CD-ROMs
Human Interface Devices
•Input: keyboard, mouse, ...
•Output: displays, printers, ...
Control/Monitor Devices
•Control devices are actuators (outputs)
•Monitor devices are sensors (inputs)
Functional Description: System Bus
Address Bus
•Carries the location of a memory cell
•Uni-directional (always supplied by the CPU)
•Determines maximum amount of memory available to CPU
Data bus
•Carries data between CPU and memory or I/O devices
•Bi-directional
•Determines the width of the architecture (i.e. 16-bit system)
Control Signal / Bus
•Carries timing signals (and more) to synchronize CPU to external circuitry
•Highly dependent on the specific CPU
Functional Description: Timing and
Interrupt Circuitry

- Crystal of piezoelectric material vibrates when

given current

- Interrupt circuitry differs based on applications

Functional Description: Microproc. Opr.

Reset Power on / Reset signal received

1. CPU output inst. add onto add. bus

FETCH 2. Read inst. pattern from memory onto data bus
3. Increment inst. pointer (prog. counter)
Repeat till off /
halted

1. Determine what type of instruction was

DECODE
fetched

1. If necessary, read data from memory

EXECUTE 2. Execute instruction

3. If necessary, write results to memory
Functional Description: OPCode Fetch
Study Questions – Chapter 1
No. 1-19