Combinational Circuit

Design-2
 BCD-to-Excess-3 Code converter
• BCD is a code for the decimal digits 0-9
• Excess-3 is also a code for the decimal digits

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 Specification of BCD-to-Excess3
• Inputs: a BCD input, A,B,C,D with A as the
most significant bit and D as the least
significant bit.
• Outputs: an Excess-3 output W,X,Y,Z that
corresponds to the BCD input.
• Internal operation – circuit to do the
conversion in combinational logic.

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Formulation of BCD-to-Excess-3
• Excess-3 code is easily formed by adding a
binary 3 to the BCD digit.
• There are 16 possible inputs for both BCD and
Excess-3.
• It can be assumed that only valid BCD inputs
will appear so the six combinations can be
treated as don’t cares.

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Optimization – BCD-to-Excess-3
• Lay out K-maps for each output, W X Y Z

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 Expressions for W X Y Z
• W(A,B,C,D) = Σm(5,6,7,8,9)
+d(10,11,12,13,14,15)
• X(A,B,C,D) = Σm(1,2,3,4,9)
+d(10,11,12,13,14,15)
• Y(A,B,C,D) = Σm(0,3,4,7,8)
+d(10,11,12,13,14,15)
• Z(A,B,C,D) = Σm(0,2,4,6,8)
+d(10,11,12,13,14,15)

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 Minimize K-Maps
• W minimization

W = A + BC + BD

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 Minimize K-Maps
• X minimization

X = BC’D’+B’C+B’D

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 Minimize K-Maps
• Y minimization

Y = CD + C’D’

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 Minimize K-Maps
• Z minimization

Z = D’

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Two level circuit implementation
• Final Boolean Expressions
– W = A + BC + BD = A + B(C+D)
– X = B’C + B’D + BC’D’ = B’(C+D) + BC’D’
– Y = CD + C’D’
– Z = D’
• Factoring out (C+D) = T
• Then T’ = (C+D)’ = C’D’ (De Morgans)
– W = A + BT
– X = B’T + BT’
– Y = CD + T’
– Z = D’

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 Create the digital circuit
• Implementing
the second set of
equations where
T=C+D results in
a lower gate
count.

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 Create the digital circuit
W = A + BC + BD = A + B(C+D)

X = B’C + B’D + BC’D’ = B’(C+D) + BC’D’

Y = CD + C’D’

Z = D’

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 BCD-to-Seven-Segment Decoder
• Specification
– Digital readouts on many digital products often
use LED seven-segment displays.
– Each digit is created by lighting the appropriate
segments. The segments are labeled a,b,c,d,e,f,g
– The decoder takes a BCD input and outputs the
correct code for the seven-segment display.

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 Specification
• Input: A 4-bit binary value that is a BCD coded
input.
• Outputs: 7 bits, a through g for each of the
segments of the display.
• Operation: Decode the input to activate the
correct segments.

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 Formulation
• Construct a truth table

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 Optimization
• Create a K-map for each output and get
– A = A’C+A’BD+B’C’D’+AB’C’
– B = A’B’+A’C’D’+A’CD+AB’C’
– C = A’B+A’D+B’C’D’+AB’C’
– D = A’CD’+A’B’C+B’C’D’+AB’C’+A’BC’D
– E = A’CD’+B’C’D’
– F = A’BC’+A’C’D’+A’BD’+AB’C’
– G = A’CD’+A’B’C+A’BC’+AB’C’

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 Note on implementation
• Direct implementation would require 27 AND
gates and 7 OR gates.
• By sharing terms, implementation can lead to
a circuit with 14 less gates.

• Normally, a decoder has less number of

outputs than inputs.

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 4-bit Equality Checker
• Specification
– Input: Two vectors, A(3:0) and B(3:0) each being
4-bits. The MSB bits : A(3) and B(3).
– Output: N which has a value of 0 when A=B and 1
if A≠B.
– Operation: Combinational logic to compare the 4
bits of A with the 4 bits of B to produce N

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 4-bit Equality Checker
• Formulation
– For each bit position Ai will be compared with Bi
and if they are equal, N = 0, otherwise, N = 1.
– Thus, if any bit position indicates a 1 then the
values are different. These 1st level comparator
outputs can then be Ored together.
– The ORed output is inverted to produce a 1 when
they are equal.

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 4-bit Equality Checker
• Optimization
• Done by implementing
two separate blocks.
• 1st the unit MX
compares two bit and
outputs a 0 if they are
equal, i.e., an XOR
operation.
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4-bit Equality Checker

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 The second unit
• The ME unit takes the MX outputs and
generates a 1 (E = 1) when all the inputs are 0,
i.e., a NOR operation.
• E = (N0+N1+N2+N3)’

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 Magnitude Comparator
compares two digital or binary numbers
(consider A and B) and determines their relative
magnitudes (whether one number is equal, less
than or greater than the other digital number)

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 2-BIT COMPARATOR
For a 2-bit comparator, we have four inputs A1A0
and B1B0 and three outputs
E (is 1 if two numbers are equal)
G (is 1 when A > B) and
L (is 1 when A < B)

E= A’1A’0B’1B’0 + A’1A0B’1B0 + A1A0B1B0 + A1A’0B1B’0

E=(( A0 ⊕ B0) + ( A1 ⊕ B1))’

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 2-BIT COMPARATOR
G = A1B’1 + A0B’1B’0 + A1A0B’0
L= A’1B1 + A’1A’0B0 + A’0B1B0

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 4-BIT COMPARATOR
The procedure for binary numbers with more than 2 bits can
also be found in the similar way. Figure shows the 4-bit
magnitude comparator.

Input: A=A3A2A1A0
B=B3B2B1B0

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4-BIT COMPARATOR

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4-BIT COMPARATOR

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 Applications of Comparators
• These are used in the address decoding circuitry in computers and
microprocessor based devices to select a specific input/output device for
the storage of data.

• These are used in control applications in which the binary numbers

representing physical variables such as temperature, position, etc. are
compared with a reference value. Then the outputs from the comparator
are used to drive the actuators so as to make the physical variables closest
to the set or reference value.

• Process controllers

• Servo-motor control

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 ENCODERS
An encoder is a circuit that performs the
inverse operation of a decoder. An encoder has
2n (or less) input lines and n output lines

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 Octal-Binary Encoder
It has eight inputs, one for each of the octal digits, and
three outputs that generate the corresponding binary number

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 Limitations of Octal-Binary Encoder
• For 8 bits input, there can be 28 possible combinations, out of
which only 8 are used using 3 output lines.
• an output with all 0’s is generated when all the inputs are
zero. This output is the same as when D0 is equal to 1. The
discrepancy can be resolved by providing one additional line
known as Enable.
When Enable = 0, an output with all 0’s is generated when all
the inputs are zero.
When Enable = 1, an output with all 0’s is generated when
D0 is equal to one.
Thus, Enable line helps to ensure whether D0 is activated or
not when output is zero.

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 Limitations of Octal-Binary Encoder
• only one input can be active at any given time. If two inputs
are active simultaneously, the output produces an undefined
combination.
For example, if D3 and D6 are 1 simultaneously, the output of the
encoder will be 111 (Y2 =Y1=Y0 = 1). This does not represent
either binary 3 or binary 6. To resolve this problem, encoder
circuits must establish an input priority to ensure that only one
input is encoded.

If we establish a higher priority for inputs with higher subscript

number and if both D3 and D6 are 1 at the same time, the output
will be 110 because D6has higher priority than D3.

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Priority Encoder

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 Activity
Formulate the logic expressions for the 8 x 3
priority encoder.

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