Superlattices and Microstructures 122 (2018) 165–170

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Superlattices and Microstructures

journal homepage: www.elsevier.com/locate/superlattices

Effect of P+ shielding region on single event burnout of 4HeSiC

T
trench gate MOSFET
Liu Yan-juan, Wang Ying∗, Yu Cheng-hao, Luo Xin, Cao Fei
Key Laboratory of RF Circuits and Systems, Ministry of Education, Hangzhou Dianzi University, 310018 Hangzhou, China

A R T IC LE I N F O ABS TRA CT

Keywords: In this work, numerical simulation methods have been applied to a 4HeSiC trench-gate MOSFET
4HeSiC device structure to investigate its susceptibility to single event burnout. With SILVACO ATLAS, the high-
Trench MOSFET k shielded trench-gate MOSFET and high-k trench-gate MOSFET are investigated to prove that P
P+ shielding region + shielding region under the trench bottom could provide a leaking path of hole current and
improve the device's tolerance to single-event burnout. The simulation results show that the
using of P+ shielding region makes the burnout threshold voltage change from 360 V in high-k
trench-gate MOSFET to 470 V in high-k shielded trench-gate MOSFET, about 30.6% improve-
ment in the performance of SEB.

1. Introduction

Silicon carbide is a promising material for high-power, high-frequency, and high-temperature applications due to its physical
properties and electrical properties [1,2]. Compared with silicon, the SiC material is considered as an intrinsically radiation-hard
material because of its higher displacement energy and wider band gap and larger electron-hole pair generation energy than silicon
[3]. However, SiC devices are also sensitive to the radiation effects.
Recently, researchers have shown interest in the radiation effects on 4HeSiC material devices. Some work have been done to
study the single event effect on some 4HeSiC devices, which do not depend on a gate oxide as a controlling element, mainly including
schottky barrier diodes (SBDs), JBS diodes, JFETs and MESFETs [4–10]. These failures are due to single event effects that are due to
heavy ion induced ionization track leading to a strong increase in temperature, and not due to displacement damage, which refers to
subsequent damage in device characteristics after lattice atoms knocked out of their locations and displacement damage is not a
transient effect. However, few investigations of the SEB in SiC power MOSFETs have been reported [11–14]. In our study, detailed
two-dimensional simulations of the single event burnout are performed to study the SEB failure occurred in 4HeSiC power trench
gate MOSFETs.
In trench gate 4HeSiC MOSFET devices, the electric field at the corner of the trench bottom limits device's blocking voltage. In
order to prevent gate oxide at the corner of the trench bottom premature breakdown affecting our study on single event burnout,
high-k dielectric material [15–18] is used instead of the silicon oxide. The P+ shielding region beneath the trench bottom is a main
technology to prevent the gate oxide premature breakdown and improve its blocking capability. Firstly, the structure shown in Fig. 1
(a) is proved that it has lower specific on-resistant than the conventional P+ shielded trench gate MOSFET which the current process
technology can be used to manufacture this as shown in our previous work [19]. Moreover, high-k gate dielectric replacing SiO2 is
current research focus and the high-k trench gate MOSFET may become a main semiconductor device in the future. So, in this letter,

∗
Corresponding author.
E-mail address: wangying7711@yahoo.com (W. Ying).

https://doi.org/10.1016/j.spmi.2018.08.011
Received 29 May 2018; Received in revised form 5 August 2018; Accepted 5 August 2018
Available online 06 August 2018
0749-6036/ © 2018 Elsevier Ltd. All rights reserved.
L. Yan-juan et al. Superlattices and Microstructures 122 (2018) 165–170

Fig. 1. Cross-sectional schematic of a half-cell (a) STG-MOSFET structure (b) TG-MOSFET structure.

high-k P+ shielded trench-gate power MOSFET (STG-MOSFET) and the high-k trench-gate power MOSFET (TG-MOSFET) are studied
to indicate that the P+ shielding region could improve the device's tolerance to SEB through providing a path for the leaking out of
the hole current.

2. Descriptions of device structure and simulation

Fig. 1 shows a schematic diagram of a half-cell of high-k P+ shielded trench-gate MOSFET structure and high-k trench-gate
MOSFET structure, and the two structures have the same parameters except the presence of P+ shielding region and n-type region.
The thickness of the gate oxide is 50 nm, and the permittivity of the gate oxide is set to 25. And the n + source thickness is 0.2 μm,
the p-body thickness is 0.6 μm. The thickness of P+ shielding is 0.2 μm, and the thickness of n-type region is 0.1 μm. The doping of
n + source and n + substrate is 1.0 × 1019 cm−3, the doping of p-body is 2.0 × 1017 cm−3, the doping of n-drift is 4.0 × 1015 cm−3,
the doping of p + shielding is 1.0 × 1019 cm−3, the doping of n-type region is 6.0 × 1016 cm−3. The doping of n buffer is
3.0 × 1017 cm−3.
In this letter, we investigate the performance of the 4HeSiC trench-gate MOSFET with ATLAS device simulator using 2-D nu-
merical simulations [20]. In the simulation, the following models are used. The mobility models include Caughey Thomas Analytic
model (ANALYTIC) and velocity dependent mobility model (CVT), which include the effects of phonon scattering and ionized im-
purity scattering. Due to existence of the heavily doped regions, band-gap narrowing model (BGN) is also used. Recombination
models Shockley-Read-Hall (SRH) and Auger recombination. Incomplete ionization model is also utilized. Moreover, Selberherr
model is utilized for the blocking characteristics simulation.
The simulation of silicon carbide is assumed a defect free material. With regard to the SiC/SiO2 interface, a fixed interface state
density of 1 × 1012 cm−2•eV−1 is assumed. And parameter values for the physical properties of 4HeSiC are adjusted specifically for
this material during the simulation. And these parameters mainly include the energy band gap, thermal conductivity, relative per-
mittivity, effective density of states for electron and hole, electron and hole bulk mobility, and the avalanche ionization coefficients.
Moreover, the material parameters of 4HeSiC are shown in Table 1.

3. Analyzation of the simulation results

In this section, we demonstrate that STG-MOSFET is less sensitive to SEB than TG-MOSFET, and STG-MOSFET has larger SEB

Table 1
Material parameters for the simulations.
Material Parameters Value Meaning

Eg300 3.26 eV the value of band-gap of the material at 300 K

Permittivity 9.66 dielectric permittivity of the material
Edb 0.1 eV donor energy level
Gcb 2 the conduction-band degeneracy factor
Eab 0.2 eV acceptor energy level
Gvb 4 the valence-band degeneracy factor
Taun0 1 μs SRH lifetime for electrons
Taup0 1 μs SRH lifetime for holes
Nsrhn 3 × 1017 cm−3 the SRH concentration parameter for electron
Nsrhp 3 × 1017 cm−3 the SRH concentration parameter for holes

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Fig. 2. Blocking performance in two structures.

threshold voltage, mainly due to the existence of thr P+ shielding region in STG-MOSFET, which can provide an extra leaking path of
hole current.

3.1. Blocking characteristics

Fig. 2 shows the breakdown performance of two structure when the gate electrode and source electrode is shortened. The blocking
voltages of the STG-MOSFET and TGMOSFET are 1440 V and 1435 V, respectively, indicating that the blocking ability of the two
structures is almost identical. This is because that the two structures utilize the same high-k dielectric, leading to the device's
breakdown due to breakdown of 4HeSiC material, and they have same N-drift region parameters, resulting in the almost identical
breakdown voltage.

3.2. Single-event burnout characteristics

There is a parasitic bipolar transistor inherent to the 4HeSiC trench-gate MOSFET, which n + source, p-body and n + drain act
like the emitter, the base and the collector, respectively (shown in Fig. 1). So the failure mechanism of SEB in 4HeSiC trench-gate
MOSFET is considered as the second breakdown mechanism of the parasitic bipolar transistor, similar to the silicon power MOSFET
[21].
We simulate an ionizing impact within a structure by a function allowing electron-hole pair generation in a specific area of the
structure. The spatial and temporal Gaussian functions are used to describe the created electron-hole pairs along the ion's track.
Considering that the linear energy transfer (LET) is unchanged in a certain range, we choose LET which is constant along the ionizing
track so as to facilitate the study and the result interpretation [20]. The track radius ω0 is 0.05 μm. The strike has a delay time T0 of
4.0 ps and the Gaussian profile has a characteristic time Tc of 2.0 ps. The passage of a heavy ion is through the entire structure. And
the temperature is 300 K, unchanged during simulations. LET is set to 0.1 pC/μm or 18 MeV-cm2/mg, and the ion's track is presented
in Fig. 1.
We simulate the changing of drain current versus time after a single heavy ion strikes the device. The SEB performances of two
structures are shown in Fig. 3, depicting that the STG-MOSFET fails at Vds = 470 V and TG-MOSFET fails at Vds = 360 V. The SEB
threshold voltage improves by 30.6% due to the effect of the P+ shielding region. Fig. 4 gives the holes concentration distribution in
two structures at t = 10 ps ((a), (b)) and at t = 10 ns ((c), (d)) after the ion strikes the structures under Vds = 360 V. The

Fig. 3. Drain current versus time for (a) STG-MOSFET (b) TG-MOSFET after ion's strike (LET = 0.1 pC/μm, T = 300 K).

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Fig. 4. Distribution of the hole concentration (a) STG-MOSFET (b) TG-MOSFET at t = 10 ps (c) STG-MOSFET (d) TG-MOSFET at t = 10 ns after ion's
strike under Vds = 360 V (LET = 0.1 pC/μm, T = 300 K).

distributions of the holes concentration demonstrate that the P+ shielding region grounded to source can provides a path to make the
hole to leak out. This could be further proved by the distribution of the current flowlines, shown in Fig. 5. Due to the effect of the P+
shielding region on the leaking of the hole current, larger applied drain bias is required for the occurrence of burnout in STG-MOSFET
structure. So the employing of P+ shielding region can reduce the device's susceptibility to SEB.

4. Conclusions

The single-event burnout performance of 4HeSiC trench gate MOSFET device is investigated with 2D device simulator, ATLAS.
Simulation results demonstrate that the P+ shielding region could provide a path to make the holes current to leak out and improve
the device's SEB burnout voltage threshold. The high-k shielded trench-gate MOSFET is burnout at 470 V, whereas the burnout
voltage of the high-k trench-gate MOSFET is 360 V, indicating about 30.6% improvement in the device's susceptibility to SEB. From
two aspects, the holes concentration distribution and current flowlines distribution, the effect of P+ shielding region on SEB tol-
erance can be demonstrated.

Acknowledgements

This work was supported in part by the National Natural Science Foundation of China (No. 61774052) and in part by the Excellent
Youth Foundation of Zhejiang Province of China (No. LR17F040001).

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Fig. 5. Distribution of the current flowlines (a) STG-MOSFET (b) TG-MOSFET at t = 10 ps (c) STG-MOSFET (d) TG-MOSFET at t = 10 ns after ion's
strike under Vds = 360 V (LET = 0.1 pC/μm, T = 300 K).

Appendix A. Supplementary data

Supplementary data related to this article can be found at https://doi.org/10.1016/j.spmi.2018.08.011.

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