Linear IC Applications Lab Manual (16EC301A)

B.Tech III – I Semester

Department of Electronics and Communication Engineering

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Objectives

Students should be able to:

 Deal with any ICs.

 Design amplifiers, signal generators, filters, data converters, circuits dealing
with mathematical operations, etc using operational amplifiers for the given
specifications.
 Design different clock signal generators using 555 timers for given
specifications.

Outcomes

With the knowledge of various ICs:

 They can develop solutions for any practical problems through projects.
 They can understand the use of ICs in different domains.

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 LIST OF EXPERIMENTS

1. Op-Amp as non-inverting amplifier (LM 741).

2. Op-Amp as adder and subtractor (LM 741).
3. Op-Amp as Differentiator (LM 741).
4. Function Generator using 741 Op-Amp.
5. Active Filters –HPF (first order).
6. IC 555 Timer as Astable Multivibrator.
7. IC 741 Op-Amp as D/A Converter.
8. Regulator experiments need to be added (78XX /79XX series).
9. PLL Experiments (565 series).
10. VCO experiments (566 series).

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 1. OP-AMP AS NON-INVERTING AMPLIFIER ( IC 741)

Aim: To design a non-inverting amplifier with a gain of 3.2 using Op-Amp LM/NE/μA741.
Verify the results of both software and hardware.
Apparatus:
1. PC with multisim software
2. Function generator /Audio oscillator
3. D.S.O
4. Bread board
5. DC±12V (or)±15V fixed regulated power supply
6. Op-Amp LM/NE/μA741
7. Resistors
8. Connecting wires

Circuit Diagram:

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Theory:
Op-Amp Non inverting amplifier is shown in Figure-1. The voltage at node A will be Vi as we
know that both inverting and non-inverting terminals are at same potential.
Applying KCL at node A
Vi Vo  Vi

Ri Rf

1 1  Vo
 Vi   

 Ri R f  R f
 R f  Ri  Vo
 Vi  
 R
 Ri .R f  f

 Rf 
 Vo  1  .Vi
 Ri 

Vo Rf
 Gain= = 1
Vi Ri

Rf
That is gain of non-inverting amplifier = 1  . There is no phase difference between input and
Ri
output. This configuration is used to design an amplifier by using Op-Amp when the required
Rf
gain is positive. Suppose the required gain is 10 then 1  =10. This implies Rf=9Ri. By
Ri
assuming Ri with a random value, say 10KΩ then Rf should be 90KΩ.

Design calculations:

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Model Waveforms: The model waveforms of Op-Amp Non inverting amplifier is shown in
Figure. It can be observed that there is no phase difference between input and output. The
amplitude of output is directly proportional to the input and gain.

Procedure:

In both software and hardware

1. Make connections as per the circuit diagram.
2. Set the input voltage at 200mV and take the corresponding output value.
3. Calculate the gain for both software and hardware results.
4. Compare them with the theoretical results.

Precautions:

1. Take care of +VCC and –VEE values. They should not exceed +15 volts and -15volts
respectively.
2. Be clear with pin numbers.

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Result:

Theoretical Practical
Software Hardware
Gain
Output

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VFSTR University
 2. OP-AMP AS ADDER AND SUBTRACTOR

Aim: To verify Op-Amp LM/NE/μA741as adder and subtractor with the help of both software
and hardware.

Apparatus:
1. PC with multisim software
2. Function generator /Audio oscillator
3. D.S.O
4. Bread board
5. DC±12V (or)±15V fixed regulated power supply
6. Op-Amp LM/NE/μA741
7. Resistors: 100KΩ3 No.s
10KΩ4 No.s
8. Connecting wires.

Circuit Diagrams:
(a) Adder

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 (b) Subtractor

Theory:
The Op-Amp adder circuit shown is connected in inverting configuration. So, there will be a
phase difference of 1800 between input and output. The potential at node A will be ‘0volts’ as it
is at virtual ground.
Applying KCL at node A
V A  V1 V A  V2 V A  Vo
  =0
Ri1 Ri 2 Rf

VA=0 as it is at virtual ground

Let Ri1 = Ri2 = Rf= R Then
V0 = - (V1+V2)

The Op-Amp subtractor circuit is shown.

Let R1 = R2 = R3 = Rf = R
As no current flows through Op-Amp, both R2 and R3 are in series. So,
VA=V2/2.
Applying KCL at inverting input,
V A  V1 V A  Vo
 0
R R

V2 V2
 V1  V0
 2  2 0
R R

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  V2  2V1  V2  2V0  0

 V0  V2  V1

Theoretical Calculations:
Adder output = -(300mV+200mV)
=-500mV
Subtractor output = 300mV – 200mV
=100mV

Procedure:

In both software and hardware

1. Make connections as per the circuit diagram.
2. Set the input voltages at V1= 200mV & V2= 300mV and take the corresponding
output values for both circuits in hardware and software.
3. Compare them with the theoretical results.

Precautions:

1. Take care of +VCC and –VEE values. They should not exceed +15 volts and -15volts
respectively.
2. Be clear with pin numbers.

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Model Graph:

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Result:

Adder

Subtractor

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Model review Questions:
1. Draw the transfer characteristics of opamp.
2. Explain the ideal characteristics of opamp.
3. Explain slew rate. Write the slew rate Equation.
4. Explain CMRR and how will it be improved?
5. Explain opamp offset parameters.
6. Draw the circuit of a log amplifier.
7. A triangular wave can be generated by differentiating a square wave. [True/False]
8. Indicate how two analog voltages are multiplied using log-antilog amplifiers.
9. Schmitt trigger is a comparator with positive feedback. [True/False]
10. Draw the schematic symbol for multiplier.
11. The RC phase shift and Wien bridge are the most commonly used sine wave oscillators
for audio frequencies. [True/False]
12. Draw the circuit for practical differentiator.
13. Give the expression for frequency of oscillation of RC-phase shift oscillator.
14. What is the difference between triangular and saw-tooth waveforms.
15. Draw the circuit diagram of analog divider.
16. Schmitt trigger is a comparator with negative feedback. [True/False]
17. Give the expression for frequency of oscillation of Wien-bridge oscillator.
18. Draw the circuit for lossy integrator.
19. Write any 2 applications of log amplifier.
20. Draw the circuit of inverting comparator.
21. What are the other names of Schmitt trigger?
22. What is the difference between Schmitt trigger & Astable multivibrator?
23. What is the other name for monostable multivibrator?
24. Give any 2 applications of Instrumentation Amplifier.
25. Draw the circuit of inverting zero-crossing detector.

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 3. OPAMP AS DIFFERENTIATOR

Aim: To design Op-Amp differentiator circuit for 100Hz signal and realize the same in both
software and hardware.

Apparatus:
1. Function generator
2. D.S.O
3. IC breadboard / trainer unit
4. DC ± 12V (or) ±15V fixed regulated power supply
5. Op-Amp LM/NE/μA741
6. Resistors R=10Ω,100 Ω,1 kΩ, 100 kΩ, 1 MΩ
7. Capacitors C = 0.001μF, 0.01μF, 0.1μF and
8. connecting wires

Circuit Diagram:

Design Steps:

1. Assume op-amp differentiator will differentiate an input signal with fmax = 100Hz.
2. Select fa = fmax = 100Hz = 1/(2πRfCi). Let Ci = 0.1µF and calculate Rf.
3. Now choose fb = 10fa = 1KHz = 1/(2πRiCi). Calculate Ri.

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 4. We know that RfC = RiCi, obtain C.

Theory:

The basic single resistor and single capacitor op-amp differentiator circuit is not widely used to
reform the mathematical function of Differentiation because of the two inherent faults,
“Instability” and “Noise”. So in order to reduce the overall closed-loop gain of the circuit at high
frequencies, an extra resistor, Ri is added to the input. Adding the input resistor Ri limits the
differentiators increase in gain at a ratio of Rƒ/Ri. The circuit now acts like a differentiator
amplifier at low frequencies and an amplifier with resistive feedback at high frequencies giving
much better noise rejection. Additional attenuation of higher frequencies is accomplished by
connecting a capacitor C in parallel with the differentiator feedback resistor, Rƒ.

The high pass filter acts as differentiator only when RC << T, where T is the time period of input
signal and RC is the time constant of the high pass filter.

Procedure:

1. Make the connections as per circuit diagram shown in figure.

2. Ensure that +Vcc and –Vcc supply connections are given properly, to the correct pin
numbers of the IC.
3. First connect the function generator output directly to DSO and adjust the input
frequency, and peak to peak input voltage of the square wave (Vi).
4. Then the function generator is connected to the circuit, on the input side. The output of
the circuit (pin no.6 to ground terminal) is connected to the DSO. Capacitor must be on
the input side. Trace the output wave form and input wave forms to the same scale. The
DSO must be double beam type preferably. Input and output wave forms must be seen
simultaneously.
5. Change the input signal frequency to 200 Hz, 500 Hz,1 kHz, etc.
6. Perform the experiment in both software and hardware.

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Model Waveforms:

Precautions:
1. +Vcc and–Vcc connections must be given correctly to the right pins.
2. Vcc should not exceed the maximum of 15Volts
3. Input voltage Vi should not exceed the maximum value.
4. 741 IC pins must be identified correctly.

Result:

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VFSTR University
Model Review Questions:
1. Explain the drawbacks in ideal integrator and differentiators.
2. Define time constant and explain its significance.
3. Explain peaking process.
4. What is the necessary condition for a good integrator?
5. What is the necessary condition for a good differentiator?

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 4. FUNCTION GENERATOR USING OP-AMP

Aim: To design the function generator using op-amp to generate 1KHz Square Wave, Sinusoidal
Wave and Triangular Wave.

Apparatus:
1. IC breadboard/trainer unit
2. DC ± 12V (or) ±15V fixed regulated power supply
3. D.S.O
4. Op-Amp LM/NE/μA741
5. Resistors: 4.7kΩ, 100kΩ, 1MΩ, 1.98kΩ, 4kΩ
6. Capacitor C =0.01μF and
7. Connecting wires
Circuit Diagram:

Square Wave Generator

Design Equations:

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The oscillation time period (T) for square wave generator is given by

The common practice is to make the R3 equal to R2. Then the equation for the time period can
be simplified as: T = 2.1976R1C

The frequency can be determined by the equation: F = 1/T

Sine Wave Generator

Design Equations:
The oscillation frequency (f) for sine wave generator(Wein Bridge Oscillator) is given by

1
f=
2𝜋𝑅𝐶

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 Triangle Wave Generator

Theory:

In the square wave generator shown in figure, due to the presence of positive feedback it works
in saturation mode. So output is either +Vcc or –Vcc. First letus assume that the output is at
Vcc .R1
+Vcc. Then voltage at the non inverting terminal becomes and capacitor starts charging
R1  R2

Vcc .R1
towards Vcc and the moment when it exceeds then inverting input dominates and
R1  R2

Vcc .R1
output becomes –Vcc. Then voltage at the non inverting terminal becomes - and
R1  R2

Vcc .R1
capacitor starts discharging towards –Vcc and the moment when it just falls below -
R1  R2
then the non inverting terminal dominates and output becomes +Vcc. This cycle repeats and
results in square wave output. This output is given to integrator to get triangular output. Low

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pass filter acts as integrator when RC >> T, where T is the time period of input signal and RC is
the time constant of the low pass filter.

The sine wave generator is wien bridge oscillator. Under bridge balance condition, it generates
oscillations, as it is known that the oscillator produce oscillations only when it meets Barkhausen
criteria of oscillations, i.e

1. A  1

2. Angle( A )=3600

Procedure:

1. Make the connections as per the circuit diagram.

2. Connect the outputs to DSO.
3. Measure the output voltage and frequency of square sine wave.
5. Similarly measure the output voltage and frequency for triangular and sine wave generators.
6. Verify theoretical and practical (software and hardware) frequencies of these three waveforms.

Precautions:

1. Identify the pin configuration of the IC properly.

2. Voltage ratings of the IC must not be exceeded the maximum of 15 Volts.

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Model Waveforms:

Result:

Frequency Theoretical Practical

Software Hardware
Square wave
Triangular Wave
Sine Wave

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Model Viva Questions:

1. Explain the working of the circuits?

2. Design an opamp circuit that generates a square wave of 5KHz frequency.
3. What are the limitations of this circuit for waveform generation?
4. Explain the bark hausan’s principle of oscillators?
5. Draw the circuit of Quadrature oscillator.
6. Draw the circuit of RC phase shift oscillator.
7. Write the output frequency and gain expressions of opamp RC phase shift oscillator.

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 5. FIRST ORDER ACTIVE HIGH PASS FILTER

Aim: To design a first order active high pass filter circuit with cut off frequency of 159 Hz.

Apparatus:

1. IC breadboard/trainer unit
2. DC ± 12V (or) ±15V fixed regulated power supply
3. Signal generator (10 mV peak,1 kHz input signal)
4. D.S.O
5. Op-Amp LM/NE/μA741
6. Resistors: R1=1kΩ,R2 =10 kΩ
7. Capacitor C=1μF and
8. connecting wires
Circuit Diagram:

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Design Equations:
Cut off frequency, fc = 1/2πRC
For a given fc, assume the value of C and calculate the R value.

Theory:
High pass filter is an electronic circuit which will pass all the frequencies from cutoff frequency
and stops all frequencies below cutoff frequency. The circuit diagram is obtained by connecting
a passive high pass filter followed by non-inverting amplifier.
For D.C ( zero frequency) capacitor behaves like open circuit and there will not be any
connection between input and output, which results in zero output. As the frequency is increasing
the capacitive reactance is decreasing, drop across the output is decreasing and hence output is
increasing. After reaching the cutoff frequency the output will reach 70.7% of maximum
possible output. From there after the output and gain will slowly increase as shown in the
frequency response curve.

For a non-inverting amplifier circuit, the magnitude of the voltage gain for the filter is given as a
function of the feedback resistor ( R2 ) divided by its corresponding input resistor ( R1 ) value
and is given as:

Gain for an Active High Pass Filter

f
AF ( )
V fc
Voltage gain(AV)= out 
Vin f
1  ( )2
fc

 Where:
 AF = the Pass band Gain of the filter, ( 1 + R2/R1 )
 ƒ = the Frequency of the Input Signal in Hertz, (Hz)
 ƒc = the Cut-off Frequency in Hertz, (Hz)

Just like the low pass filter, the operation of a high pass active filter can be verified from the
frequency gain equation above as:

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 V out
 1. At very low frequencies, ƒ < ƒc :  AF
Vin

V out A
 2. At the cut-off frequency, ƒ = ƒc :  F  0.707 AF
Vin 2

V out
 3. At very high frequencies, ƒ > ƒc :  AF
Vin

Then, the Active High Pass Filter has a gain AF that increases from 0Hz to the lower cutoff
frequency, ƒC at 20dB/decade as the frequency increases. At ƒC the gain is 0.707*AF, and after ƒC
all frequencies are pass band frequencies so the filter has a constant gain AF with the highest
frequency being determined by the closed loop bandwidth of the op-amp.

When dealing with filter circuits the magnitude of the pass band gain of the circuit is generally
expressed in decibels or dB as a function of the voltage gain, and this is defined as:

Magnitude of Voltage Gain in (dB)

Vout
AV ( dB )  20 log10 ( )
Vin

For a first-order filter the frequency response curve of the filter increases by 20dB/decade or
6dB/octave up to the determined cut-off frequency point which is always at -3dB below the
maximum gain value. As with the previous filter circuits, the lower cut-off or corner frequency
(ƒc) can be found by using the same formula:

1
fC  Hz
2 RC

The corresponding phase angle or phase shift of the output signal is the same as that given for the
passive RC filter and leads that of the input signal. It is equal to +45o at the cut-off frequency ƒc
value and is given as:

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 1
Phase Shift   tan 1 ( )
2 RC

Procedure:

1. Make the connections as per the circuit diagram.

2. Apply the input from the signal generator directly to CRO and adjust the peak to peakvalue of
the input to be 100mV.
3. Switch on the regulated DC supply to the IC. Apply sine wave input to the circuit, observe V0
on CRO.
4. Vary the frequency of the input from 100 Hz onwards, in suitable steps up to 50 KHz or
beyond the cutoff frequency fc.
5. Measure VO and determine the gain AV. Plot a graph of AVvs f.
6. This experiment can be repeated by changing the values of R and C to get different values of
fc.

Tabular Form: (For Hardware)

S.No. Input Voltage (V) Frequency (Hz) Output Voltage (V) Voltage Gain
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.

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Frequency Response:

Precautions:

1. Identify the pin configuration of the IC properly.

2. Voltage ratings of the IC must not be exceeded the maximum of 15Volts.

Result:

Theoretical Practical
Software Hardware
Cutoff
Frequency

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Model Review questions:
1. What are the advantages of active filters?
2. What are the advantages and disadvantages of higher filters?
3. What are the differences between passive and active filters?
4. Compare the frequency responses of LPF & HPF.
5. How do you design higher order filters?
6. Define electronic filter.
7. What is the other name for All pass filter?
8. Draw the circuit diagram of Butterworth narrow band pass filter.
9. What is the relation between roll-off rate & order of the filter?
10. What is sallen-key filter?
11. Design a LPF at a cut-off frequency of 10KHz with a passband gain of 2. Also find the
new value of Resistance R , when the cut-off frequency is changed from 10KHz to
12KHz.
12. Design a 2nd order Butterworth LPF , to have a higher cutoff frequency of 1.5KHz.
13. Design a 1st order Butterworth HPF , to have a lower cutoff frequency of 1.5KHz and a
pass band gain of 1.5.
14. Obtain the value of lower & upper cut off frequency of 2nd order Butterworth HPF.
Given R1= 47KΩ, R2= R3=10KΩ. C2 =C3 = 0.01μF
15. Design a NBPF, for fC= 1KHz, Q= 3 and Af=10. How do you change the center
frequency to 1.2 KHz. Keeping Af and Bandwidth as constant.
16. Design a WBSF to have fH=500Hz and fL=1.5 KHz.
17. find the phase angle if given signal frequency is 2 KHz, R= 10KΩ, C=0.01μF.
18. Design All pass filter with a phase shift of -900 at a frequency of 2KHz.
19. Explain the differences between Butterworth, Chebyshev and cauer filters.
20. Explain the butterworth polynomials.
21. Mention the rate of roll of gain of various ordered filters.

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 6. 555 TIMER IC AS ASTABLE MULTIVIBRATOR

Aim: To design a 555 timer astable multivibrator circuit to generate a clock signal with 61%
duty cycle with a frequency of 1.45 KHz.
Apparatus:

1. IC breadboard
2. 555TimerIC
3. DC variable regulated power supply
4. C.R.O
5. Resistors
6. Capacitor 0.1μF, 0.01μF and connecting wires

Circuit Diagram:

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Design Equation:

The Oscillation frequency is given by

The duty cycle is given by

R A  RB
D%=  100
R A  2 RB
Theory:

Initially switch on the power supply. The flip-flop is RESET (and hence the output of the timer is
low). As a result, the discharge transistor is driven to saturation (as it is connected to Q’). The
capacitor C of the timing circuit is connected at Pin 7 of the IC 555 and will discharge through
the transistor. The output of the timer at this point is low. The voltage across the capacitor is
nothing but the trigger voltage. So while discharging, if the capacitor voltage becomes less than
1/3 VCC, which is the reference voltage to trigger comparator (comparator 2), the output of the
comparator 2 will become high. This will SET the flip-flop and hence the output of the timer at
pin 3 goes to HIGH.

This high output will turn OFF the transistor. As a result, the capacitor C starts charging through
the resistors R1 and R2. Now, the capacitor voltage is same as the threshold voltage (as pin 6 is
connected to the capacitor resistor junction). While charging, the capacitor voltage increases
exponentially towards VCC and the moment it crosses 2/3 VCC, which is the reference voltage to
threshold comparator (comparator 1), its output becomes high.

As a result, the flip-flop is RESET. The output of the timer falls to LOW. This low output will
once again turn on the transistor which provides a discharge path to the capacitor. Hence the
capacitor C will discharge through the resistor R2. And hence the cycle continues.

While charging, the capacitor charges through the resistors R1 and R2. Therefore the charging
time constant is (R1 + R2) C as the total resistance in the charging path is R1 + R2. While
discharging, the capacitor discharges through the resistor R2 only. Hence the discharge time
constant is R2C.

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Procedure:
1. Make the connections as per the circuit diagram.
2. Identify the pins of 555 IC correctly. Ensure that +VCC is applied properly.
3. Connect the output to DSO and observe the output waveforms at pin no.3 and 2 (VO and VC),
to the same time scale on a dual beam/dual trace DSO.
4. Measure voltage and time intervals. Compare theoretical and actual values of software and
software. Sketch the output waveforms.

Model Waveforms:

Precautions:

1. +VCC < 15V must be applied.

2. Identify the pin configuration of the 555 IC properly.

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Result:

Sl.No. RA RB C Theoretical Time Frequency

Period
TON TOFF Theoretical Hardware Software

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Model Review Questions:

1. Why 50% duty cycle can’t be obtained with the above circuit?
2. What are the applications of this circuit?
3. Draw the circuit, to get50%dutycycle?
4. Design an IC555 astable multi that produces a square wave of 5KHz frequency with 60%
Duty cycle.

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 7. IC 741 Op-Amp as D/A Converter

Aim: Verify the functionality of 3-bit DAC.

Apparatus:

1. IC breadboard / trainer unit

2. DC ± 12/15V and +5V fixed regulated power supply
3. Multimeter
4. Op-Amp LM/NE/μA741
5. Resistors R=1kΩ,10 kΩ,100kΩ and connecting wires

Circuit Diagram:

Design Equation:

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Theory:

The R-2R resistor ladder network directly converts a parallel digital symbol/word into an analog
voltage. Each digital input (b0, b1, etc.) adds its own weighted contribution to the analog output.
This network has some unique and interesting properties.

 Easily scalable to any desired number of bits.

 Uses only two values of resistors which make for easy and accurate fabrication and
integration.
 Output impedance is equal to R, regardless of the number of bits, simplifying filtering
and further analog signal processing circuit design.

Procedure:

1. Make the connections as per the circuit diagram shown in figure 15.
2. Give +Vcc and –Vcc supply connections correctly.
3. Apply Vref and change the switch positions as per the following table and note the
corresponding outputs with Multimeter.
4. Verify theoretical and actual voltages, in each case.

Precautions:

1. Identify the pin configuration of the IC properly.

2. Voltage ratings of the IC must not be exceeded the maximum of 15 Volts.

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Tabular Form:

Sl.No. B2 B1 B0 Theoretical Vo Practical Vo

Hardware Software
1 0 0 0
2 0 0 1
3 0 1 0
4 0 1 1
5 1 0 0
6 1 0 1
7 1 1 0
8 1 1 1

Result:

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Model Review Questions:
1. What is the need for data converters?
2. Explain the basic principle of ADC and DAC.
3. Give the specifications of DAC/ADC.
4. Design 4-bit DAC.
5. Explain the transfer characteristics of 4-bit DAC with a neat graph.
6. What are the limitations of binary weighted resistor DAC?
7. What are the limitations of R-2R Ladder DAC? How do you overcome these limitations?
8. List out the types of ADCs.
9. Which is the fastest ADC?
10. Which is the accurate ADC?
11. What is the conversion time of successive approximation ADC?
12. What is the conversion time of Flash ADC?
13. Define resolution? Give the formula for the analog output of DAC in terms of resolution
for the given digital input.

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 8. Voltage Regulator – 78xx/79xx

Aim: To verify the functionality of voltage regulator ICs – 78xx and 79xx series.

Apparatus:

1. 230V-12V Step Down Transformer

2. Bridge Rectifier (or 4 PN Diodes – 1N4007)
3. 1A Fuse
4. 1000μF Capacitor
5. 7805 Voltage Regulator IC
6. 0.22μF Capacitor
7. 0.1μF Capacitor
8. 1N4007 Diode

Circuit Diagram:

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Theory:

The AC power supply from mains first gets converted into and unregulated DC and then into a
constant regulated DC with the help of this circuit. The circuit is made up of transformer, bridge
rectifier made up from diodes, linear voltage regulator 7805 and capacitors.

If you observe, the working of the circuit can be divided into two parts. In the first part, the AC
Mains is converted into unregulated DC and in the second part, this unregulated DC is converted
into regulated 5V DC. So, let us start discussing the working with this in mind.

Initially, a 230V to 12V Step down transformer is taken and its primary is connected to mains
supply. The secondary of the transformer is connected to Bridge rectifier (either a dedicated IC
or a combination of 4 1N4007 Diodes can be used).

A 1A fuse is placed between the transformer and the bridge rectifier. This will limit the current
drawn by the circuit to 1A. The rectified DC from the bridge rectifier is smoothened out with the
help of 1000μF Capacitor.

So, the output across the 1000μF Capacitor is unregulated 12V DC. This is given as an input to
the 7805 Voltage Regulator IC. 7805 IC then converts this to a regulated 5V DC and the output
can be obtained at its output terminals.

The pin description of the 7805 is described in the following table:

PIN PIN DESCRIPTION

NO.
1 INPUT Pin 1 is the INPUT Pin. A positive unregulated voltage is given as
input to this pin.
2 GROUND Pin 2 is the GROUND Pin. It is common to both Input and Output.
3 OUTPUT Pin 3 is the OUTPUT Pin. The output regulated 5V is taken at this
pin of the IC.

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Procedure:

1. Connect the circuit as shown in the circuit diagram.

2. Apply the input to the transformer.
3. Connect IC 7805, 7809, 7909, 7912 alternatively and check output voltages in all cases.
4. Measure the output voltage using multimeter.
5. Note the readings of regulated DC output voltage.

Observations:

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Precautions:

1. The first important point to note is that the input voltage should always be greater than the
output voltage (at least by 2.5V).
2. Identify the pin configuration of the IC properly.

Result:

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 9. Phase-Locked Loop (PLL) – IC 565

Aim: To measure relevant parameters of an IC 565 PLL.

Apparatus:
1. Function generators
2. Oscilloscope
3. Dual DC-power supply
4. LM565 IC
5. Resistors
6. Capacitors
7. Digital voltmeter

Circuit Diagram:

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Theory:
The diagram for a basic phase locked loop shows the three main element of the PLL: phase
detector, voltage controlled oscillator and the loop filter.
In the basic PLL, reference signal and the signal from the voltage controlled oscillator are
connected to the two input ports of the phase detector. The output from the phase detector is
passed to the loop filter and then filtered signal is applied to the voltage controlled oscillator.
The Voltage Controlled Oscillator, VCO, within the PLL produces a signal which enters the
phase detector. Here the phase of the signals from the VCO and the incoming reference signal
are compared and a resulting difference or error voltage is produced. This corresponds to the
phase difference between the two signals.
The error signal from the phase detector passes through a low pass filter which governs many of
the properties of the loop and removes any high frequency elements on the signal. Once through
the filter the error signal is applied to the control terminal of the VCO as its tuning voltage. The
sense of any change in this voltage is such that it tries to reduce the phase difference and hence
the frequency between the two signals. Initially the loop will be out of lock, and the error voltage
will pull the frequency of the VCO towards that of the reference, until it cannot reduce the error
any further and the loop is locked.
When the PLL, phase locked loop, is in lock a steady state error voltage is produced. By using an
amplifier between the phase detector and the VCO, the actual error between the signals can be
reduced to very small levels. However some voltage must always be present at the control
terminal of the VCO as this is what puts onto the correct frequency.
The fact that a steady error voltage is present means that the phase difference between the
reference signal and the VCO is not changing. As the phase between these two signals is not
changing means that the two signals are on exactly the same frequency.

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Procedure:
1. Connect the circuit in Figure (2). Display the signal waveforms @ pins 9 and 4 on
theoscilloscope; the waveform @ pin 4 will be referred to as Vo(t). Use Graph (1) to plotboth
displays. Adjust R1 to set the free-running frequency of the VCO @ 10 kHz.Measure (w.r.t
ground) the dc voltages @ pins 6 and 7; leave the EVM @ pin 7. Notethat when the VCO is
in the free-running mode, both voltages are equal, and are referredto as Vref.
2. Apply a 1V (p-p) sinusoid @ 4 kHz to pin 2; this signal will be referred to as Vi(t). Display
Vi(t) and Vo(t) on the oscilloscope, with Vi(t) as the trig. source. Note that the traceswill
synchronize only when the PLL is in hold-in (tracking) condition. Gradually increase the
input signal frequency, fi, and determine the frequency fc which defines the lower edge of
the capture range [fc¡ is the frequency at which the tracessuddenly synchronize, and remains
in synch with freq. changes]. The PLL is now in hold-in condition. Measure the dc voltage @
pin 7; this voltage will be referred to as VD.
3. Increase further the frequency fi, and for each integer-value (in kHz) setting of fi, measure
the phase angle of Vo(t) w.r.t. Vi(t) and the dc-voltage VD. Find the frequency fH+ w defines
the upper edge of the tracking range. Record in table (1).

4. Gradually decrease the frequency fi, and determine fC+ [the upper edge of the capturerange].
Decrease further fi and measure Vo(t) and VD for each integer-value (in kHz)setting of fi.
Find fH¡ [the lower edge of the tracking range], and record in table (2).

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5. Use Graph (2) to plot [VD - Vref] vs fi, and use Graph (3) to plot [VD - Vref] vs 6 Vo=Vi .
* From the slope of the plot in Graph (2), ¯nd the VCO sensitivity, Ko, as:
Ko= 2π/[slope] rad/sec/V
=
* From the slope of the plot in Graph (3), ¯nd the phase-detector sensitivity, KD, as:
KD = (180/π)[slope] V/rad
=
6. Replace C2 by a 1.0 ¹F capacitor. Find the frequency locations for fC¡, fH¡, fC+ andfH¡.
Record in table (3).

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Result:

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 10.Voltage Controlled Oscillator (VCO) – IC 566

Aim: To observe the operation of IC 566 VCO.

Apparatus:
1. LM566 IC
2. Resistors
3. Capacitors
4. DC power supply
5. CRO
6. Connecting wires

Circuit Diagram:

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Theory:

LM566 is a monolithic voltage controlled oscillator from National semiconductors. It can be

used to generates square and triangle waveforms simultaneously. The frequency of the output
waveform can be adjusted using an external control voltage. The output frequency can be also
programmed using a set of external resistor and capacitor. Typical applications of LM566 IC are
signal generators, FM modulators, FSK modulators, tone generators etc. The LM566 IC can be
operated from a single supply or dual supply. While using single supply, the supply voltage
range is from 10V to 24V. The IC has a very linear modulation characteristics and has excellent
thermal stability. The circuit diagram of a voltage controlled oscillator using LM566 is shown in
the figure

Resistor R1 and capacitor C1 forms the timing components. Capacitor C2 is used to prevent the
parasitic oscillations during VCO switching. Resistor R3 is used to provide the control voltage
Vc. Triangle and square wave outputs are obtained from pins 4 and 3 respectively. The output
frequency of the VCO can be obtained using the following equation:

Fout = 2.4(V+-V5) /(R1C1V+) . Where Fout is the output frequency, R1 and C1 are the timing
components and V+ is the supply voltage.

Procedure:
1. Connect the circuit as shown in the circuit diagram.
2. Apply DC supply to the IC.
3. Connect CRO at the output terminals to observe output waveforms.
4. Vary the values of R1 and C1 and observe different outputs.
5. Note the readings for different cases.

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Observations:

Graph:

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Result:

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