FUNDAMENTALS of I/Os

• What are I/O’s

I/O is the specially designed element which interface to core signal to off
chip environment.

I/O = INPUT OUTPUT

Cell that allows the interface
Core side between the logic Package side
inside the chip and external
system components
 • Why do I/O’s need special attention ? Why are they
important ?
Any input signal which comes from off chip device has to be checked by the
I/O for any discrepancy in its behavior other than the defined for the core
and if it finds any characteristic of the signal which can damage the core, it
either modifies the signal or simply rejects it . It also checks the signal going
from core to the outside world . So I/Os are responsible for proper functioning of
the entire chip. Thus however efficient the core design may be, it is the I/Os
which determine the efficiency of the chip.
It is necessary for the designer to analyze the designed I/O under the
practical conditions to verify the deriving strength of the chip, delay in signal,
power etc as they all are heavily dependent on the I/O irrespective of whether the
core is compliant with the specifications or not. Because even a minor difference
in the performance of the I/O than the desired one can damage the whole circuit
or even can cause problems to the off chip circuit It. It is the responsibility of the
I/O to limit the outgoing signaling in all respect like amplitude, frequency, delay
etc, under the specified one , for proper functioning .

• Types of I/Os & Specific Functions

3 different types of an I/O
_ Input
_ Output
_ Bi-directional

Specific functions:

_ Pull-up, pull-down
_ Hysteresis
_ Analog
_ Supplies

• Types of I/Os

INPUT
These types of I/Os, receive signal from off the chip circuit and feed the core. But
before feeding the core, it brings the signal into the operating limit of the core so
as to make sure that chip works proper.
Input buffers are available with two possible drives towards the core .
Normal drive which is equivalent to an X4 drive in the standard digital
library.These cells are characterized with internal loads up to 80 standard
loads i.e. 0.72pF .
High drive which is equivalent to an X16 drive in the standard digital library.
They are characterized with loads up to 316 standard loads i.e.2.84pF

The I/O receives and adapts the signal for the core

Output
The IO amplifies and adapts the signal from the core to the outside load. These
buffers are used to drive large capacitive loads which arise from long
interconnect lines such as clock distribution networks, high capacitance fan
out and high off chip loads .The drive capability of such a buffer should be
such as to achieve the requisite rise and fall times into a given capacitive load.
Normally the drive capability of I/O buffers is as high as 8 mA . By driving
Capability, it means that the output buffer can source or sink the specified
amount of current in the worst case

Bi-directional

The IO can either be programmed in input or output mode

BiDir, Tri-state (BD in ST). Normal bidirectional buffers are tri-state output buffers
associated with an input buffer. All the characteristics for both the input and
output section must be satisfied by the bidirectional buffer. Also, there are some
bidirectional buffers which have tri-state both input and output section to interface
external and internal buses
.
• NOMENCLATURE OF BUFFERS

A standardized naming convention is adopted for all the types of buffer, so that
even at just looking at the name of a buffer , viewer can have sufficient
information about the buffer .
Abbreviations used for different types of buffers:
IBUF CMOS input buffer .
TLCHT TTL input buffer .
SCHMIT Input buffer with hysteresis .
B Push pull output buffer .
BT Tri-state output buffer .
BI Bidirectional buffer .

Suffix used to indicate the characteristics of buffers :

C CMOS buffer .
T TTL buffer .
R Slew rate control .
AR Active slew rate control .
H High drive input stage .
U Active pull up (Input buffer) .
D Active pull down(Input buffer) .
Q Switch on pull up/down .
P Test pin .
OD Open Drain (Output buffer) .
_FT 5v Tolerant .
S Schmitt trigger on input .
ZI Tristate input stage .
2,4,8 For different driving capability in mA .
 • BASIC BUILDING BLOCKS OF I/Os

• INPUT SECTION
Since this section is directly connected to the core so it has to make sure
that the signal is within the operating limit of the core. As we have different
output stages for different needs ,similarly in input stage section ,we have a
variety of different functionality blocks to fulfill our requirement.

Input with Pull-up and Pull-down

Often the input is put to a particular logic level instead of letting it float.
Either logic low or logic high is connected to the input pin when it is not used.
This is achieved by pull up or pull down circuits .They may have switch to
connect the input to pull up or pull down circuit .The switch versions are useful
for example when IDDQ testing is required since in this case all I/Os can be put
in a zero DC power consumption state. If no signal is present on the bus, a
resistive load pulls up or pulls down the bus.

Input with Hysteresys: Schmitt trigger

Hysteresis is often required in input buffers to decouple the noisy external

signal from the core circuitry of the chip. Generally the circuit is biased at
VDD/2 and therefore if due to introduction of noise in the input signal, the
signal oscillates around VDD/2 , the output of the circuit oscillates between
logic level 1 and logic level 0 .To avoid these unwanted oscillations, basic
principle of different switching thresholds for input signals from low to high
and high to low transitions is employed .Transistors with different threshold
voltages are used and further controlled by body effect .The difference in
switching level for low to high and high to low avoids the conduction of p
and n transistors simultaneously or in the narrow range of input voltage.
Whenever two or more transistors are connected in series, the potential
difference between source and substrate increase as we move away from the
transistor whose substrate and source is tied together .This results in increase
in the width of depletion layer which in turn increase the channel substrate
junction potential .This increases the gate -channel voltage drop . The overall
effect is increase in the threshold voltage. This whole phenomenon is known as
Body effect

1(a) demonstration of noise decoupling with hysteresis

A very prevalent circuit employed for hysteresis is as shown in the figure
1(b).The hysteresis characteristics is shown in figure 1(c).The circuit is a TTL
input buffer and hence switching threshold is to be between 0.8V and 2.0VThe
hysteresis characteristics of figure 1(c) has been tuned for Vilhyst of 0.9 V and
Vihhyst of 1.9 V.
For the dc voltage sweep from low to high at the input ,though M2 turns ON after
Vin > Vtn2 ,M3 does not turn ON as Vt3 (threshold voltage of M3) is shifted due
to body affect.Hence output voltage remains at high level .The source of M3 is
initially at a voltage of VDD -Vt1(body affected).But after Vin> Vtn2,the voltage at
node N1 begins to fall.Here M1 and M2 form an inverter pair,having a feedback
effect with M1 acting as a resistive load.As soon as VGS3 > Vt3(body affected)
,M3 gets ON and output node is immidiately pulled to the ground.Also the drive
strength of nMOS M3 and M2 is more compared to the pMOS M4 and M5.This
explains the sharp transition charactersitics of the circuit.The value of Vihhyst
depends promarily on W/L of M1 and M2 for a given techmology(Vtn
fixed).Kepping M1 fixed ,greater is the W/L of M2 ,faster is the rate at which the
node N1 is pulled down.This pulls up the switching threshold Vihhyst to a lower
value towards left in fig. 1(c).A similar explanation ensues for the input.

Fig. 1(b)) TTL input buffer with hysteresis

going high to low and feedback transistor M4 and M5 forming the inverter pair
with M4 as a resitive load.Here the switching threshold Vilhyst depends primarily
on W/L of M5.The difference in the two logic thresholds is achievede by a
different pMOS and nMOS body affected threshold voltages.
 Fig.1 (c) Hysteresis Characteristics

For low to high sweep of input voltage, the gate voltage of M2 can be considered
to be Vin + Vtp3.As Vin >Vt1 M2 and M1 form an inverter pair and the output
node voltage starts decreasing .When Vin > Vdd -Vtp5 M5 turns ON ,pulls up the
gate of M2 and thereby turns it OFF. With this the out-put is immediately pulled
down by M1 as M2 is totally OFF. The switching threshold Vihhyst depends on
Vtn1 & Vtp5 and W/L of M2 and M1.Similarly when the input is swept from high
to low, as VG2 (Vin + |Vtp3| ) drops below VDD - Vtp5,M2 turns and starts pulling
up the output node. This makes M5 less and less conductive ,further pulling up
the gate of M2,speeding the pulling up action. This is the positive feedback
effect. The switching threshold Vilhyst depends on Vtp3 and W/L of M5 and M3.
A brief comparative study of the two hysteresis circuits shows that the circuit of
figure 8has advantage in saving static power .The circuit of figure () has a
constant static current dissipation through the pair M1 and M2 or through M4 and
M5 in dc high and low levels respectively.
Frequently to reduce the maintenance of library elements input and output
buffers are merged together to get Bidirectional Pad buffers .Such buffers can be
discretionally made to act either as input or as output buffers at any time

CMOS And TTL Buffer

An external signal may be either CMOS or TTL .Normally the design of

input buffers consists of cascaded CMOS inverter chain sufficient to drive
the internal load .A CMOS to CMOS buffer is very simple , having to
inverters cascaded together. Gate lengths of first stage inverter is greater than
the normal gate lengths to prevent early avalanche breakdown with high
input gate voltages .Many times TTL or ECL chip is used , for increasing the
speed or to perform some specific function ,with CMOS .So a circuit is
required to convert TTL logic to CMOS logic at the input section . This
circuit has inverter which has been scaled down to switch between the TTL
logic thresholds .

• OUTPUT SECTION

An output buffer must have sufficient drive capability to achieve adequate

rise and fall times into a given capacitive load .To achieve the specified
functionality of the output buffer, different types of output stages are used at
the output section

Push Pull Stage

A push pull stage consists of p and n transistors at the output pad for
sourcing and sinking respectively , where each of transistors is controlled
through a different chain of tapered inverters fed after buffering .This has two
advantages:
1) No direct gate contacts of the two output driver transistor.
2) Static and short circuit power dissipation can be avoided by bifurcating the
inverter chain in a way such that while sourcing current at the output pad ,
NMOS driver is made off before PMOS is on and vice versa.

Open Drain Output Stage

This has an advantage over the push pull, and that is , it has just one driver
stage. Such configuration avoids gate source-drain capacitance, thus making
it faster than push pull . But this configuration can either sink or source current
at a time, which limits its usage. The output state of the pad can also be driven
to tristate and can be connected to buses where high impedance state is
required for data transfer .
Push Up/down Stage

Often the tristated output is put to a particular logic level instead of letting
the the bus float .Either logic low or high can be made at the output using the
pull up or pull down transistors Normally the NMOS transistor is used for
pull down and PMOS transistor for pull up .But the strength of the transistor
is so chosen that when a logic level appears at the output from core ,it must
overcome the pulling up or pulling down action .

• PREDRIVER

This block is used at the output section of the chip and is connected
between the core and slew rate control block .A predriver consists of
multiplexer, to select the test mode or basic operating mode, series of
inverters to generate two signals NIN and PIN at the output for slew rate
control .The signal at NIN rises faster than PIN while signal at PIN falls
faster than NIN .

• SLEW RATE CONTROL

A fast transition of the signal at the output pad tends to introduce

frequencies in UHF range into the off chip load being fed .Most of the time
it is undesirable and thus appears as noise .The source of this noise is the
inductive voltage which is due to the inductance of the introduced by the
package pins .To reduce this noise , we generally control the switching which
reduces the rate of change of current at the output .Slew rate control circuits
thus artificially limit the rate of current switching thereby limiting the UHF
interference .One way to achieve this is by breaking the output driving
transistors into a series of parallel transistors and switch the stages
sequentially one after the other with some delay .The slew rate control circuit
consists of a series of nand and nor gates which are driven by PIN and NIN
signals respectively .As there is sequential delay in both nand and nor chain,
thus they drive the series of output transistors sequentially. This results in
total controllability over the rate of change of output current and hence slew
rate can be controlled.
Sometimes slew rate gets effected due to change in PVT and even the slew
rate controller cannot do anything as they are hardcoded while fabrication.
So to compensate for the change in slew rate in changing PVT conditions,
codes are fed through a compensation block which generates the code
according to the conditions .Compensation block has only an enable pin and
the output pins . This block senses the change and generates a common code
for all the slew rate controlling devices .
Now a problem arises, generally we have same slew rate for all the I/Os
inside a chip but in some special cases we can require different slew rate for
different I/Os and as there is one or at the most two compensation blocks
inside the chip ,the generated code is same for all the I/Os and hence there
would not be any difference in their slew rate as required .So to over come
this problem, some modification is done at the cell level. The normal
functioning code is noted down for all the slew rate controller and some
circuit is added at that level to generate the required code from the common
code generated by the compensation block for each controller .

• ELECTROSTATIC DISCHARGE

protection is very important to save the chip from unwanted voltages which gets
developed at the pin due to some source coming in contact with the pin . This
large accumulated charges can destroy the transistor , so a mechanism is
needed which can effectively and quickly discharge this unwanted accumulated
charge An input buffer couples the external off chip signal to the core elements
of the chip .Since the external signal can have voltage ranges much beyond the
normal CMOS operating voltages , an input ESD protection is required for
these buffers . non destructive breakdown of diodes is utilized to clamp the
voltage between VDD and VSS .The resistor tends to decrease the current
reaching gate .But this block introduces RC delay ,hence the design has to be
optimized if used in high speed circuits.
 • Power supplies
Power supply is required to bias the circuit and , as the circuit consists of both
the I/O and the core , therefore we have different power supply for these two
The primary goal of having different rails is to minimize the effect of the
noisy output buffers . The power supply for core should be clean i.e. it
should not contain any noise . I/O section is connected to the outside world
where the signal is more prone to get diluted with noise , therefore the
separation for the two power supply is must in those chips where even a slight
amount of noise can degrade the performance of core to a greater extent . In
some chips, where the noise has little or no effect on the performance of
the core, both I/Os and core can have the same power supply . These pads are
basically a sandwich of various metal layers used in the design. The pads consist
of pins and metal connection on all sides to provide the power connection to both
the Core (Internal Library elements) and the I/O elements. The power and ground
bus widths may be calculated using the worst case power dissipation estimate of
a die with the particular packaging style , supplying a stable and good power
supply and electromigration considerations.

• LATCH UP
It is a parasitic effect and results in shorting of the VDD and VSS lines , usually
resulting in chip ,self destruction or at least system failure with the requirement to
power down . In a chip due to presence of both the NMOS and PMOS transistor
on the same substrate , the combination results in a circuit which is composed of
a npn transistor , a pnp transistor and two resistors connected between the
power and the ground rails. PNP transistor is formed by the source of PMOS
acting as emitter , nwell as base and p+ substrate of the NMOS transistor as the
collector similarly NPN is formed by the source of NMOS acting as emitter,
substrate of NMOS as base and nwell as collector . In addition , resistivity of
nwell and substrate results in resistances which connects the base of PNP to
VDDand the base of NPN to ground respectively. This whole thing results in
action similar to a PNPN thyristor which has latching property i.e. as the circuit
behaves like a positive feedback amplifier so after a certain value of applied
voltage , called the trigger point, the circuit snaps and draws a large current while
maintaining a low voltage across the output . This is , in effect ,a short circuit
which can destroy the MOS transistors . Latchup can be triggered by tansient
currents or voltages that may occur internally to a chip during power up or
externally due to voltages or current beyond operating ranges. During normal
circuit operation in internal circuitry this may occur due to supply voltage
taransients , but this unlikely . However , these conditions may occur at the I/O
circuits employed on a CMOS chip , where the internal circuit voltages meet the
external world and large currents can flow.

Prevention
Latchup may be prevented in two basic ways :

1) Latchup resistant CMOS processes

In this method , the substrate is doped with varying degree of doping , bottom is
highly doped whereas the upper portion is lightly doped compared to bottom .
This reduces the parasitic resistances offered by the nwell and the substrate and
hence reduces the gain of the circuit . This shifts the triggering voltage to higher
value than VDD and prevents the Latchup
2) Layout Techniques
In this method , the p+ substrate of NMOS transistor is surrounded by the nwell
of the PMOS transistor which acts as dummy collectors and spoil the gain of
the parasitic transistor by collecting minority carriers and preventing them fro
being injected into the respective bases

Output Pad Buffers

CMOS output pad Buffers are used to drive large capacitive loads which arise
from long global interconnect lines such as clock distribution networks, high
capacitance fan out and high off chip loads. The drive capability of such a buffer
should be such as to achieve the requisite rise and fall times into a given
capacitive load. Normally the drive capability of I/O buffers as high as 24mA [1]
and as low as 0.8mA is available. Convetionally a XmA buffer would mean to
source or sink XmA while fulfilling the worst case CMOS/TTL dc levels at the
output of the sourcing/sinking transistor. The following section would help explain
the meaning of a XmA buffer and gives the analytical design equations for
designing such an output transistor drivers.

Design of a XmA Buffer:

Consider a push pull stage at the output of the buffer where both p and n transistors are
driven by different set of controlled signals through a chain of inverters. The p transistor
would apparently source the current while n would sink the current.
All the simulations are performed at the worst conditions. This considers the inductive
voltage drop in the power pads (due to the packaging lead inductance).Typically a drop
of 0.4 V is used for the equations and eldo simulations here.
 pMOS sourcing current in X mA Buffer

Consider above where p transistor is ON ,sourcing current under worst case TTL and
CMOS dc output levels.The pMOS would be in it’s linear region of operation and the
current equation is given as below in equation in 1(a).

tox is the oxide thickness mp the hole mobility and e the relative permittivity of
the Silicon dioxide. The aspect ratio(W/L)p of the pMOS driver is designed such
that IDS=XmA.Thus for a CMOS output buffer (W/L) of the p driver for a XmA
Buffer is given as in equation in 2 below.
(W/L) = [X . 10 -3]. [( -4.1 + |Vtp| )0.4 - 0.08] -1 . [tox/m e]...................2

With appropriate value of mp vhe hole

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nMOS sinking XmA of current

Similarly the n transistor (above fig) will sink current while meeting CMOS / TTL
output dc conditions. A rise fall time of 12 ns is achieved for the all buffers while
driving a maximum load of X x 25 pf (determined conventionally) under nominal
conditions.

HIERARCHY IN LAYOUTS
In a layout of an I/O, there are two types of cells
1) Base Cell
2) Leaf Cell

Base cell consists of active, poly, and transistor. Usually for one library, all
the I/Os have same base cell irrespective of whether its an input ,output or
bidirectional with few exceptions where some modification at the base level
is necessary to achieve some important characteristic which is otherwise not
possible in the chip. Base cell has defined boundaries within itself for different
blocks which are needed to design a buffer. And in these defined space,
transistors with active and poly for that particular block is present in floating state
i.e. they are not connected together, or some other leaf cell is instantiated .

Leaf Cell can be of two types:

1) One having only the information about the connectivity of transistors with
their pin information at top level or at the instantiated cell level. They have
different metal rails, vias and pins in their cell view .
2) The other type contains active and poly forming the transistor along with
some metal rails used in the cell which is same for all the cells in the library.
These cells are actually instantiated at the base level and can be instantiated
inside other leaf cell or they can instantiate some other leaf cells inside them.
They are generally lower in hierarchy to base cell.
What are we catering to ?
Here in FTM Noida , general purpose I/O s are designed which can be used for a
wide range of applications if they are meeting the required specifications. They
can also be abutted to certain I/O libraries . Also The FTM is involved in
designing some specific I/O to cater other groups and some customers .
Typically I/Os are placed at the periphery of the core logic i.e. on the sides
of the core logic, except on the corners of the cell .They are placed parallel
to one another ( abutted together using filler cells ) and vertical to the enclosure
containing the core . Also corner cells are used. This helps in maintaining the
power ring continuity throughout the cell, which is very important for uniform
distribution of the power to all the I/Os inside the chip .
Uniform distribution of power is necessary , as the I/Os are placed all over the
periphery and due to large distances between the them there is high chance of
the power getting degraded , which means I/Os will get power in a broader range
than the required one.For eg. the actual voltage received by one buffer could be
2V and for another one 2.5V This also helps in ESD protection as it helps in
discharging the accumulated charge during ESD uniformly and quickly.

• P&R cells (fillers and corner cells)

In a packaged chip , all the I/Os are abutted to one another . The metal power
ring continuity is automatically ensured by abutment . But if there is free spaces
between I/Os , filler cells must be used to fill up these empty areas. There are
filler cells with different width which can be used to fill up the of different sizes . It
is advised to start the filler cell placement by the widest cell possible and then
continue with decreasing sizes until the gaps are completely filled .
Filler cells only contain the geometrical information of the metal rings at each
level of metal. As the I/Os are not placed at the corner edges of the cell and
inspite of having filled the gaps between I/Os , complete continuity of metal rings
is not achieved unless and until the corner edges are filled by corner cells . They
also have only the geometrical information of the metal rings . Both filler and
corner cell serves the same purpose but they are placed at different positions in
the packaged chip. So in short the purpose of filler cell and corner cell is to have:

1) Continuity of metal power rings which is responsible for Uniform

Distribution of Power .
2) Electrostatic Discharge protection .
3) Nwell closing to prevent latch up .

• Back End: Layout, Abstract, P&R, Test views

I/Os Abstract View
The layout view of an IO is complex and heavy to handle for P&R tools. For this
reason an abstract views is used. It gives just the information required by the
P&R tools: pin, black box size, routing obstruction

I/Os Layout Frames (1/2) Core Limited Device

In core limited device, the size is determined by the core dimension. The I/O ring
will increase the final size. So, it is necessary to shrink the I/O height as much as
possible, thus increasing the I/O width.

I/Os Layout Frames (2/2) Pad Limited Device

1) In pad limited device, the size is determined by the pad number.
2) The I/O ring contains as much I/Os as possible. So, it is necessary to
shrink the I/O width as much as possible, thus increasing the I/O height.
3)Two different configurations are possible: linear or staggered.
Pad limited configuration: Staggered (H9) & Double Rows (C090)

Efficiency of double rows placement

Double rows principle
– The I/O cells (i.e. pad + I/O core) are placed on the chip periphery in two rows,
forming two concentric I/O rings.
– As the abstract is the same height as the two rows, the cell placement remains
the same as staggered configuration.

Staggered configuration
Drawbacks :
- Thin I/O (difficult to route).
- Different layout from linear configuration
Double rows configuration
Advantages :
- I/O layout identical to linear configuration
Drawbacks :
- Architecture more complex

Pad layout: CUP, BOA, POP & BPOP

H9: Circuit Under Pad (CUP)
– Any I/O device can be placed under the pad.
– M1 _ M(n-2) under the pad are used as supply rails
C090: Bond Over Active (BOA)
– Same as CUP, improved rules for mechanical robustness.
– M1 _ M(n-1) under the pad are used as supply rails
C090: Probe Over Passivation (POP)
– Same as BOA, alucap extended to separate bonding
and probing zones. Probing allowed on alucap extension.
C065: Bond/Probe Over Passivation (BPOP)
– Same as POP except that alucap and copper are
now separated by the dielectric
Flip Chip
-Power and ground bumps in the core part (no I/O cell)
-I/O cell still placed in a peripheral ring, without pad
-I/O output routed to bump via a re-distribution layer
-ESD protection and I/O supply cells located in the I/O ring