SN54HC74, SN74HC74

DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS

WITH CLEAR AND PRESET
SCLS094B – DECEMBER 1982 – REVISED MAY 1997

D Package Options Include Plastic SN54HC74 . . . J OR W PACKAGE

Small-Outline (D), Shrink Small-Outline SN74HC74 . . . D, DB, N, OR PW PACKAGE
(TOP VIEW)
(DB), Thin Shrink Small-Outline (PW), and
Ceramic Flat (W) Packages, Ceramic Chip
1CLR 1 14 VCC
Carriers (FK), and Standard Plastic (N) and
Ceramic (J) 300-mil DIPs 1D 2 13 2CLR
1CLK 3 12 2D
description 1PRE 4 11 2CLK
1Q 5 10 2PRE
The ’HC74 contain two independent D-type 1Q 6 9 2Q
positive-edge-triggered flip-flops. A low level at GND 7 8 2Q
the preset (PRE) or clear (CLR) inputs sets or
resets the outputs regardless of the levels of the
SN54HC74 . . . FK PACKAGE
other inputs. When PRE and CLR are inactive
(TOP VIEW)
(high), data at the data (D) input meeting the setup

1CLR

2CLR
time requirements are transferred to the outputs

VCC
NC
1D
on the positive-going edge of the clock (CLK)
pulse. Clock triggering occurs at a voltage level
3 2 1 20 19
and is not directly related to the rise time of CLK. 1CLK 4 18 2D
Following the hold-time interval, data at the NC 5 17 NC
D input can be changed without affecting the 1PRE 6 16 2CLK
levels at the outputs. NC 7 15 NC
The SN54HC74 is characterized for operation 1Q 8 14 2PRE
9 10 11 12 13
over the full military temperature range –55°C to

1Q

2Q
2Q
NC
GND
125°C. The SN74HC74 is characterized for
operation from –40°C to 85°C.
NC – No internal connection

FUNCTION TABLE
INPUTS OUTPUTS
PRE CLR CLK D Q Q
L H X X H L
H L X X L H
L L X X H† H†
H H ↑ H H L
H H ↑ L L H
H H L X Q0 Q0
† This configuration is unstable; that is, it does not
persist when PRE or CLR returns to its inactive
(high) level.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date. Copyright  1997, Texas Instruments Incorporated
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

SN54HC74, SN74HC74
DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS
WITH CLEAR AND PRESET
SCLS094B – DECEMBER 1982 – REVISED MAY 1997

logic symbol†
4
1PRE S 5
3 1Q
1CLK C1
2
1D 1D 6
1 1Q
1CLR R
10
2PRE 9
11 2Q
2CLK
12
2D 8
13 2Q
2CLR

† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, DB, J, N, PW, and W packages.

logic diagram (positive logic)

PRE

C
CLK C
Q
C TG

C C
C
C

D TG TG
TG

Q
C C
C
CLR

absolute maximum ratings over operating free-air temperature range‡

Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Package thermal impedance, θJA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127°C/W
DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace
length of zero.

2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

 SN54HC74, SN74HC74
DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS
WITH CLEAR AND PRESET
SCLS094B – DECEMBER 1982 – REVISED MAY 1997

recommended operating conditions

SN54HC74 SN74HC74
UNIT
MIN NOM MAX MIN NOM MAX
VCC Supply voltage 2 5 6 2 5 6 V
VCC = 2 V 1.5 1.5
VIH High-level input voltage VCC = 4.5 V 3.15 3.15 V
VCC = 6 V 4.2 4.2
VCC = 2 V 0 0.5 0 0.5
VIL Low-level input voltage VCC = 4.5 V 0 1.35 0 1.35 V
VCC = 6 V 0 1.8 0 1.8
VI Input voltage 0 VCC 0 VCC V
VO Output voltage 0 VCC 0 VCC V
VCC = 2 V 0 1000 0 1000
tt Input transition (rise and fall) time VCC = 4.5 V 0 500 0 500 ns
VCC = 6 V 0 400 0 400
TA Operating free-air temperature –55 125 –40 85 °C

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)
TA = 25°C SN54HC74 SN74HC74
PARAMETER TEST CONDITIONS VCC UNIT
MIN TYP MAX MIN MAX MIN MAX
2V 1.9 1.998 1.9 1.9
IOH = –20 µA 4.5 V 4.4 4.499 4.4 4.4
VOH VI = VIH or VIL 6V 5.9 5.999 5.9 5.9 V
IOH = –4 mA 4.5 V 3.98 4.3 3.7 3.84
IOH = –5.2 mA 6V 5.48 5.8 5.2 5.34
2V 0.002 0.1 0.1 0.1
IOL = 20 µA 4.5 V 0.001 0.1 0.1 0.1
VOL VI = VIH or VIL 6V 0.001 0.1 0.1 0.1 V
IOL = 4 mA 4.5 V 0.17 0.26 0.4 0.33
IOL = 5.2 mA 6V 0.15 0.26 0.4 0.33
II VI = VCC or 0 6V ±0.1 ±100 ±1000 ±1000 nA
ICC VI = VCC or 0, IO = 0 6V 4 80 40 µA
Ci 2 V to 6 V 3 10 10 10 pF

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SN54HC74, SN74HC74
DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS
WITH CLEAR AND PRESET
SCLS094B – DECEMBER 1982 – REVISED MAY 1997

timing requirements over recommended operating free-air temperature range (unless otherwise
noted)
TA = 25°C SN54HC74 SN74HC74
VCC UNIT
MIN MAX MIN MAX MIN MAX
2V 0 6 0 4.2 0 5
fclock Clock frequency 4.5 V 0 31 0 21 0 25 MHz
6V 0 36 0 25 0 29
2V 100 150 125
PRE or CLR low 4.5 V 20 30 25
6V 17 25 21
tw Pulse duration ns
2V 80 120 100
CLK high or low 4.5 V 16 24 20
6V 14 20 17
2V 100 150 125
Data 4.5 V 20 30 25
6V 17 25 21
tsu ↑
Setup time before CLK↑ ns
2V 25 40 30
PRE or CLR inactive 4.5 V 5 8 6
6V 4 7 5
2V 0 0 0
th ↑
Hold time, data after CLK↑ 4.5 V 0 0 0 ns
6V 0 0 0

switching characteristics over recommended operating free-air temperature range, CL = 50 pF

(unless otherwise noted) (see Figure 1)
FROM TO TA = 25°C SN54HC74 SN74HC74
PARAMETER VCC UNIT
(INPUT) (OUTPUT) MIN TYP MAX MIN MAX MIN MAX
2V 6 10 4.2 5
fmax 4.5 V 31 50 21 25 MHz
6V 36 60 25 29
2V 70 230 345 290
PRE or CLR Q or Q 4.5 V 20 46 69 58
6V 15 39 59 49
tpd
d ns
2V 70 175 250 220
CLK Q or Q 4.5 V 20 35 50 44
6V 15 30 42 37
2V 28 75 110 95
tt Q or Q 4.5 V 8 15 22 19 ns
6V 6 13 19 16

operating characteristics, TA = 25°C

PARAMETER TEST CONDITIONS TYP UNIT
Cpd Power dissipation capacitance per flip-flop No load 35 pF

4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

 SN54HC74, SN74HC74
DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS
WITH CLEAR AND PRESET
SCLS094B – DECEMBER 1982 – REVISED MAY 1997

PARAMETER MEASUREMENT INFORMATION

VCC
From Output Test High-Level
Under Test Point 50% 50%
Pulse
0V
CL = 50 pF
tw
(see Note A)
Low-Level VCC
Pulse 50% 50%
LOAD CIRCUIT
0V
VOLTAGE WAVEFORMS
PULSE DURATIONS

VCC VCC
Reference 50% Input 50% 50%
Input
0V 0V
tsu th tPLH tPHL

Data VCC In-Phase VOH

90% 90% 90% 90%
Input 50% 50% Output 50% 50%
10% 10% 0 V 10% 10%
VOL
tr tf
tr tf
tPHL tPLH
VOLTAGE WAVEFORMS VOH
Out-of-Phase 90% 90%
SETUP AND HOLD AND INPUT RISE AND FALL TIMES 50% 50%
Output 10% 10%
VOL
tf tr

VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
NOTES: A. CL includes probe and test-fixture capacitance.
B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns.
C. For clock inputs, fmax is measured when the input duty cycle is 50%.
D. The outputs are measured one at a time with one input transition per measurement.
E. tPLH and tPHL are the same as tpd.

Figure 1. Load Circuit and Voltage Waveforms

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