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XNOR-based double-edge-triggered flip-flop for two-phase pipelines

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DOI: 10.1109/TCSII.2005.855734 · Source: IEEE Xplore

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 An XNOR-based Double-edge-triggered Flip-Flop for Two-phase Pipelines
Ying-Haw SHU, Shing TENQCHEN, Ming-Chang SUN
Department of Electrical Engineering, National Taiwan University
Taipei, Taiwan, R.O.C.
And
Wu-Shiung FENG
Department of Electronics Engineering, Chang Gung University
Taoyuan, Taiwan, R.O.C.
ABSTRACT
Asynchronous modules operating under two-phase micro-
pipeline methodology are faster than those in common four-phase
control schemes because the double-edge-triggered flip-flops in
the two-phase control systems capture data twice within each
clock cycle. This paper proposes a newly designed double-edge-
triggered flip-flop based on an alternative XNOR gate. By
utilizing the sensitivity to the driving capacity of the previous
stage, we use this simplified XNOR gate as a pulse-generator. A
modified transparent latch following the pulse-generator acts as
an XNOR-based double-edge-triggered flip-flop, which is 42%
faster and more reliable than a conventional double-edge-
triggered flip-flop under HSPICE simulation. We also show that
our proposed double-edge-triggered flip-flop is not affected by
input-data logic-levels at various supply voltages. We
implemented the XNOR-based double-edge-triggered flip-flop in
a two-phase-pipeline system, and verified it with HSPICE
simulation in the TSMC 0.25um CMOS process.
Keywords: double edge-triggered flip-flop, two-phase, pipeline,
XNOR.
INSTRUCTION
It is well known [1-3] that over the past two decades,
researches into asynchronous circuits have revealed the
possibility they can accomplish better average-case performance
than other types by removing the unnecessary overhead of the
globally synchronizing clock signal. The non-synchronizing
property of asynchronous circuits presents new attractions as an
alternative to synchronous circuits for certain applications.
Circuit designers may investigate asynchronous solutions for
certain local function blocks in which various computing results
reveal large timing divergences, or, for certain applications in
local pipeline systems where timing considerations are also
severely restricted. The Intel research group experimentally
implemented its asynchronous instruction-length decoder design,
which outperformed the original synchronous circuits in the
Pentium II by threefold, and which is famous in CPU
development history as RAPPID (Revolving Asynchronous
Pentium Processor Instruction Decoder) [1].
The concept of globally asynchronous locally synchronous
(GALS) circuit extends the application of asynchronous circuits
to VLSI systems [2]. Advocators promote implementing an entire
VLSI system with isolated asynchronous modules, which are
self-controlled by local internal clocks, and communicate with
other modules via a data-driven controller. Their asynchronous
handshaking protocol not only keeps system stability robust and
free from clock-skew problems, but also brings many potential
advantages. Since the asynchronous modules are isolated by their
own data-driven controllers with various clock timings, wrapped
79
asynchronous modules may have their own dedicated power
systems and different operating frequencies to reduce excess
power consumption. Furthermore, a wrapped asynchronous
module with its own built-in power system and operating clock
will make IP-reuse easier and more reliable [3].
Pipelined control systems divide tasks into steps to be
performed by sequences of functional units, similar to an
assembly line in a factory. The pipelined system allows all the
separate steps to be processed in parallel. Thus, the pipeline
concept is widely implemented in current VLSI systems to get
greater throughputs, and is the basic concept used in constructing
entire systems of independent asynchronous modules in GALS
applications. Since there is no clock to fire the independent
modules in an asynchronous system, handshaking signals—
“request” and “acknowledge”—are used to indicate when data is
ready and when data is captured. The two common asynchronous
handshaking protocols are shown in Fig. 1.
(a) (b)
Figure 1. Pipelined protocols: (a) two-phase, (b) four-phase.
The two-phase handshaking protocol uses a transition on
the request signal to signify “data ready to send”, as shown in
Figure 1(a). The receiver then uses a transition on the
acknowledge signal to indicate capture completion. “Two-phase”
refers to rising and falling transitions, thus the two-phase
protocol is also called “transition signaling”.
The four-phase handshaking protocol treats only rising
transitions on the request signal as “data ready”, and only rising
transitions on the acknowledge signal as “data captured”. Falling
control signal transitions in the four-phase protocol are used to
pre-charge the computing module, or to indicate that the
asynchronous module ready for the next computation. Normally,
the four-phase protocol is easy to implement in GALS systems or
modular synchronous systems since most latches and decision
cells used in asynchronous systems are level-sensitive, and there
is an extra period to reset/pre-charge modules. Thus, the implied
timing concern in the four-phase protocol is not so severe. By
contrast, the two-phase protocol may be more efficient since it
eliminates the unnecessary control overhead of waiting for signal
transitions on the control bus, particularly for those asynchronous
modules without large timing variations between common and
rare cases. Of course, the key components in two-phase pipeline
systems are the latches and flip-flops, which capture data on
rising and falling control signal transitions.
This paper is organized as follows. In section II, we present
concept and concerns regarding the topic of implementing a
double edge-triggered flip-flop using an alternative XNOR/XOR
gate. Section III discusses those added asynchronous components
used to implement our simulated asynchronous pipelined system.
We provide some simulation results and explanations in section
IV. Section V is our brief conclusion.
XNOR GATE AND DOUBLE-EDGE-
TRIGGERED D FLIP-FLOP
The better performance achieved by two-phase control systems
in simple asynchronous modules is due to their two data-captures
per cycle of control-signal transitions. The direct practical
application is to use a newly defined interface to make a
conventional transparent latch active on the rising and falling
edges of the control signal. That is because conventional
transparent latches are level-sensitive, and such transparent
latches determine their status, opaque (blocking) or transparent
(transmissive), according to the logic state of the control signal.
Therefore, the AMULET group (merged into the advanced
processor technology [APT] group) proposed a two-to-four-
phase interface to enable level-sensitive latches to work in two-
phase control schemes [4]. Of course, another direct approach for
two-phase control systems is to design a truly new double-edge-
triggered D flip-flop (DETDFF) [5-8] in which the D flip-flop
(signal latch) used in a two-phase micro-pipeline scheme is
active during low-to-high and high-to-low transitions on the
control wire. One good demonstration depicted by K. Y. Yun is
the pseudo-static DETDFF [7] constructed from a pair of
complementary edge-triggered flip-flops. Each edge-triggered
flip-flop is made up of three NAND or NOR gates in series. Its
capture mechanism stores the logic state of transferred data in the
previous control state, then captures and passes the stored data to
the output through the last NAND gates at the next control signal
transition. To avoid having the stored data influenced by clock
transitions, a pair of weak inverters maintains the data until the
feedback signal from the new output state arrives. But the
resulting trade-off is slower response times.
Another study also based on storing input data uses the
parasitic capacitance of MOSFETs. Input selection-pairs
controlled by control (clock) signals are constructed from
transmission paths, unlike [7], which used inverters with enable-
switches. The inverters used in this DETDFF are N-type
structures with active P-MOSFET (MOS-style) clocked inverters
[8]; the functional diagram is shown in Fig. 2. There are two
obvious drawbacks in this simpler and faster structure. First, the
width-to-length ratios of N-MOSFETs must be much larger than
those of P-MOSFETs in order to have low enough logic level and
larger enough parasitic capacitance to reliably store data. This
implies that the transistor area of the MOS-style DET-FF cannot
be smaller than those of other solutions despite being constructed
from only 16 transistors. The next is that control signals (clock
and reverse clock) must be flawlessly matched. Otherwise, the
next input data and the slower responding weak inverter may
affect the stored data, and a sudden spike caused by the previous
data may appear in the output.
80
Figure 2. Functional diagram of the MOS-style double-edge-
triggered flip-flop.
We chose to use a pulse generator to trigger a transparent
latch twice per control signal cycle. The pulse generator contains
only two kinds of common logic gates, XNOR and inverter. A
functional diagram of the proposed design is shown in Fig. 3.
Theoretically, the inverter provides a delayed complementary
control signal, and the XNOR logic provides signal pulses on the
rising and falling transitions of the control signal. There are two
practical problems with such a design. The first is that the XNOR
gate is constructed from transmission paths or lots of
conventional gates, that means it must intrinsically have either
greater power dissipation or more propagation delays since the
signals pass through three logic stages. The other problem is due
to the inverter cell shown in Fig. 3. It is usually constructed of
many inverters in odd stages, since those inverters must provide
longer delays to have wide enough pulses for the following
transparent latch to capture data. Therefore, the XNOR may be a
direct solution to making conventional level-sensitive latches fit
two-phase pipelined controllers, but it is seldom discussed in the
past.
Figure 3. Functional diagram of the XNOR-based double-edge-
triggered flip-flop.
The transmission paths, or so-called “capture-pass logics”,
perform the XNOR logic used in our design [9], as shown in Fig.
4. It works well, with greater speed and lower power dissipation
than the conventional capture-pass adders described in [10-11].
There are two inherent problems with this proposed XOR/XNOR
cell. The first problem is its poor driving capacity. Input signals
just pass through transmission paths to the output ports, which
means they must directly drive the input capacitors of the next
stage via the transmission paths. The Mp3 and Mn3 transistors
provide additional current paths for the XOR port when both
inputs are logical-high (A=B=’1’), and for the XNOR port when
both inputs are logical-low (A=B=’0’). However, this transistor
pair also causes the other problem. The logic-state patch may
provide an undesired current path from Vdd to the XNOR, or
from the XOR to ground if an internal latching problem occur
(XNOR=”1”, XOR=”0”). Thus, the promised better performance
only happens in small-scale circuits. In our application, we apply
the sensitivity of the driving capacity to validate variances in the
input clock pair. We give the input inverter of the postponed
clock a longer channel-length, and that allows this proposed
XNOR to generate wide enough pulses at the control signal
transitions, as shown in Fig. 5. Actually, the width-to-length ratio
of the input inverter determines whether our XNOR based
DETDFF can work normally, and how low its supply voltage can
be.
Figure 4. Alternative XOR/XNOR based on the capture pass
(transmission path) concept.
Figure 5. Pulse generator used in XNOR-based DET-FF.
In deciding on whether to get complementary pulses from a
single output of the XNOR gate with an added inverter or from a
pair of differential outputs from XOR and XNOR, we choose the
single output and removed Mn3. Thus, we cut off an undesired
current path, and made the width-to-length ratio of the input
inverter fit our design criterion, as mentioned above. We also
added inverters as output buffers to get better driving capacity.
The remaining issue was the mismatch between the “clk” and the
“Iclk”, since the “Iclk” signal follows the “clk” signal. Noting the
result discussed in [12], we enlarged the width-to-length ratio of
the “Iclk” inverter, which reduced the mismatch between the
clocks due to different driving capacities and different loads.
We also needed a transparent latch with small input capacitance.
The latch used in our proposed DET flip-flop is a common
transparent latch made up of a latching inverter pair and an input
selector (multiplexer), as shown in Fig. 6(a). Normally, the time
required to break the latch status between the inverter pair
dominates the entire transient time of a transparent latch. To
avoid reaction from a weak inverter, the channel resistance of the
input selector must be much smaller than that of the inverter. In
our design, we set the width-to-length ratio of the weak inverter
to one-fifth of the input-selection gates. However, as noted in
[12], the larger gate and diffusion capacitances incurred by
longer channel lengths postpone responses. Thus, we modified
our transparent latch by implementing active loads on the weak
inverter to reduce propagation delays during transitions. This
active-load concept is also discussed in [12-13] as “skinny
current limit”, and “pre-charging method”. That is the pre-
charged active load provides the major channel resistance, and
permits the smallest portion of the original weak inverter to
perform the defined latch function, as shown in Fig. 6(b). We
81
also connected the input line to the Mp1 and Mn2 of the selector
shown in Fig. 6(b) so the Mp1 and Mn2 gate and channel
capacitors are pre-charged prior to the control signal because the
timing requirement of asynchronous logic is that input data be
ready for next stage when the control signal arrives.
(a)
(b)
Figure 6. Transparent latch: (a) functional diagram, (b) transistor-
level.
TWO-PHASE PIPELINE SYSTEM
The simplified system
The two-phase asynchronous control system used in our
simulation was modified from Sutherland’s micro-pipeline,
which is well discussed in [7, 14], and shown in Fig. 7. Only five
logic components are used in this system, C-element, delay
buffer, inverter, XNOR gate, and transparent latch. The XNOR
gate and transparent latch work as double edge-triggered flip-
flops (DET-FF), as discussed above. In our simulation, we treated
the logic cells between stages as a simple signal path, which
means the entire system worked as a simple FIFO (first-in-first-
out) operation. In practical applications, those logic cells may be
asynchronous modules or computing cells.
The transition of the “request” signal from the left stage means
that the left-stage data is ready, and will enable the C-element to
fire the DETDFF to capture the data after the acknowledge signal
from the right C-element arrives. In the meantime, the firing
signal sent from this C-element resets the left-stage C-element to
wait for the next “request” signal. This firing signal is also the
“request” signal for the right C-element after passing the delay
buffer. Obviously, there may be racing problems or
synchronizing failures in such a simple two-phase control system.
If the delay time provided by the delay buffer is not long enough
to allow the logic cells to reflect the new data before enabling the
transparent latch of the next stage, the next stage may capture
unpredictable logic states, even the previous logic state. falling times of a simple inverter. Because the originally
designed width-to-length ratio of the MOS-style DET-FF [8]
could not work normally in our simulative CMOS process, we
doubled the NMOS width-to-length ratio to allow a low enough
logic-low for its weak inverters.

Logic Cell

Figure 8. Delay buffer cell from Fig. 7.

Figure 7. Two-phase pipelined control system used in the
simulation.

Delay buffer and C-element

The delay buffer used in our simulation was a timing X Rising delay of XNOR based ＋ Falling delay of XNOR based
controller that not only determined how much time a single □ Rising delay of conventional ◇ Falling delay of conventional
computing process took, but also whether there was enough time △ Rising delay of MOS-style ﹡ Falling delay of MOS-style
for the logic cells in the asynchronous modules to finish their
computation before the next latch became active. Thus, the
timing requirement of this delay buffer had to satisfy the
equations presented in [7]—in simplified form:
td  tck Q  tlogic  t R A' (1)
where td, tckQ, tlogic, and tRA’ are the response times of
the delay buffer, transparent latch, logic cell, and C-element,
respectively.
The simple signal delay used in our simulation is shown in Fig. 8.
The added capacitor, C1, adjusts the possible delay time, and the
last two inverters in the diagram are used to shape the output
waveform.
The C-element used in this simulation is a symmetric design
discussed in [11, 15]. Most of the C-element is a set of transistors
called a keeper, which provides feedback from the output port to X Power dissipation of XNOR based
lock the output state when the values of the inputs are unmatched. □ Power dissipation of conventional
Of course, such keeper provides an additional current path, which
△ Power dissipation of MOS-style
may conflict with the input signal. In other words, it will take
more time and energy to break the latch status when new
matched signals appear at the inputs. The keeper of the
symmetric C-element used in our simulation provides other
signal paths for inputs only when the logic states of the inputs are
unmatched. When new matched signals appear at the inputs,
those signal paths will be useless. Thus, this symmetric C-
element provides the best power-delay performance. Another
issue concerning C-elements is whether there are inputs that may
change twice in succession, or a JOIN [16] or RENDEZVOUR
[17]. These were not a problem in our simulation system. As (b)
mentioned above, the state period of the system clock must be Figure 9. Simulation results for various W/L ratios: (a)
longer than the computing period of the entire isolated propagation delay, (b) power dissipation.
asynchronous module. Otherwise, the latch may capture the
wrong data and sustain a system failure. Our simulation yielded some attractive phenomena. First,
we found that the response speed of the pseudo-static DET-FF [7]
SIMULATION RESULTS varies in accordance with the input data and control because the
current data may be pre-stored at either the first stage or the
We performed HSPICE simulation using the fast-mode second stage, and timing differences may result from the signal
model of TSMC 0.25um CMOS process. All the N-MOSFETs propagation path length and the cutting-in voltage of the clock
used in this simulation were of the same transistor size, except signal. Furthermore, this pseudo-static DET-FF will take more
for those used in the output inverters and those critical time to transfer the correct signal if the first stage or the second
MOSFETs discussed in Section II. We adjusted the PMOS stage needs to break the locked status of its weak inverters. A
width-to-length ratio to two-and-a-half times the length of the similar weak-inverter postponement problem also happens with
NMOS ratio based on the simulation results for the rising and the MOS-style DET-FF [8]. The only difference between these

82
two phenomena is that channel charge-release plays a major part
in the MOS-style DET-FF since the pre-stored data relies on the
input capacitance of the main inverter. Because we consider the
worst-case control overhead as the timing assessment in an
asynchronous control system, the power-delay performance
shown in Fig. 10(c) is based on the worst case for each DET-FF.
We must especially emphasize that the propagation delay shown
in our simulation results is the time delay from the control signal
transition to the output data signal transition, and “power
dissipation” refers to the power consumption of all control X Power dissipation of XNOR based
circuits, including the input and output buffers, because the □ Power dissipation of conventional
driving current for the transmission paths comes from the output
△ Power dissipation of MOS-style
of the previous stage.

First, we compared the propagation delay of our XNOR-

based DET-FF, for various transistor sizes, with those of two
other DET-FFs. The simulation results shown in Fig. 9 clearly (b)
demonstrate that the MOS-style DET-FF had the best speed
performance for various transistor sizes at a cost of over four
times the power dissipation of the other solutions. This was due
to the active-load drive scheme used, and the current path hidden
in its decision stage. Although the pseudo-static DET-FF has
more transistors, there are more transmission paths and more
transition stages in our XNOR based DET-FF. Thus, we
predicted the conventional DET-FF should be faster at a cost of
more power dissipation and larger size. The simulation results
shown in Fig. 9 reveal that our XNOR-based DET-FF had a 42%
reduction in delay and a 12% expansion in power, compared with
X Power–delay of XNOR based
the pseudo-static DET-FF. That was because not all the
□ Power–delay of conventional
transistors in the pseudo-static DET-FF work at the clock
transition, and the data signal has to pass through 3 switched- △ Power–delay of MOS-style

inverter stages to the final output inverter. Basically, expanding

the transistor size (width) made no evident difference in response
speed for all simulated DET-FF solutions.
We also considered the impact of supply-voltage variations,
and show those simulation results in Fig. 10. All the DET-FF
solutions functioned properly when the supply voltage was
varied from 1.8V to 3.5V, although this 0.25um CMOS model is
at optimum at 2.5V. The MOS-style DET-FF still had the best
speed performance, even though its power dissipation was
frightful when the supply voltage was increased. Our XNOR
based DET-FF still showed a significant reduction in propagation
delay and power dissipation similar to the pseudo-static DET-FF.
Our XNOR-based DET-FF clearly had the best power-delay
performance, as shown in Fig. 10(c).
X Rising delay of XNOR based
＋ Falling delay of XNOR based
□ Rising delay of conventional
◇ Falling delay of conventional
△ Rising delay of MOS-style
﹡ Falling delay of MOS-style
(a)
(c)
Figure 10. Simulation results for various supply voltages: (a)
propagation delay, (b) power dissipation, and (c) power-delay
performance.
In pipelined simulation, we did not insert any asynchronous
modules or computing cells in the “logic cell” between the two
double-edge-triggered D flip-flops. Actually, we directly
connected those DET-DFFs with C-elements, and triggered the
first C-element with a simple clock. Thus, the whole pipelined
system functioned just like an asynchronous FIFO. Also, the
delay-buffers delay times determined the actual propagation
delay between the stages. The waveforms delivered by all the
DET-FF solutions are shown in Fig. 11. Again, the 0.8ns delay
between neighboring stages is due just to the design timing of the
delay-buffer. In a pipelined control system, the propagation delay
of any internal cell is included in the entire control timing, as
discussed in [7]. Thus, the real timing consideration, as shown in
Fig. 11, is the rising/falling time of the output waveform, which
limits the enable timing of the next stage. Some significant
results were found in simulating the pipelined system. First, it is
clear that only our XNOR-based DET-FF had symmetrical
“high” and “low” periods. That was due to the unequal rising and
falling times of the other two solutions. Second, obvious spikes
were found in the output waveform of the MOS-style DET-FF
because the pre-stored data in the parasitic capacitance could be
affected by new data and the unmatched reverse clock. Since it is
almost impossible in real VLSI implementations to have a
perfectly matched clock pair, the reverse clock in our simulated
MOS-style DET-FF was transferred from the C-element enable
signal. And the last is that the MOS-style DET-FF took longer to
pull up the output because of the active P-MOSFET used in the

83
 decision stage. Even the double-size decision-N-MOSFET took a
long time to drop the input of the output stage.
3rd stage of
XNOR based
4th stage of
XNOR based
3rd stage of
conventional
4th stage of
conventional
3rd stage of
MOS-style
4th stage of
MOS-style
Figure 11. Output waveforms from the DET-FFs in pipeline
simulation.
CONCLUSION
The concept of wrapped asynchronous modules opens a new
possibility of using various power systems and operating
frequencies in isolated computing modules in system-on-chip
(SOC) and other single-chip applications. The two-phase
pipelined control system removes the unnecessary overhead of
waiting for signal transitions on the control bus. The key
component in an efficient two-phase pipelined system is a
specified edge-triggered flip-flop that can latch data on the rising
and falling control signal transitions. We have presented a
different approach to implementing XNOR-based double-edge-
triggered flip-flops. We re-used an alternative capture-pass
XOR/XNOR gate, and took advantage of its potential weakness,
sensitivity to the driving capacity of the previous stage, to
generate a pair of stable clock pulses for a simple transparent
latch. Our approach allows use of the good property of level-
sensitive latches from other studies to be reproduced in a two-
phase pipelined control system. Simulation results show that the
proposed XNOR-based double-edge-triggered flip-flop is faster
than the pseudo-static DET-FF and more power saving. Although
the MOS-style DET-FF demonstrated significant speed
performance, the trade-off for the active load and simple latching
mechanism is more power dissipation and a disappointing output
spike. Generally, our proposed XNOR-based DET-FF had stable
performance, even when the system power was reduced to 1.8V,
72% of rated supply voltage. And this reliable performance was
also evident in the two-phase pipelined system simulation.
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