Microprocessor Architecture & Programming 1

Introduction:
A microprocessor is great at solving problems, but if it can’t communicate with the
outside world, it is of little worth. This project report contains a basic method of
communication of microprocessor as related to parallel interfacing. It will be define
later on. We first introduce the basic I/O interfacing having a variety of applications.

Objective:
To make a parallel port interface program to switch LED’s ON/OFF having a
particular time delay by using ULN2803 programmable interface IC.

I/O Interface:
There are three state buffers of basic interface. The basic output device is a set of data
latches. The term IN refers to moving data from I/O device into the microprocessor
and the term OUT refers to moving data out of the microprocessor to the I/O device.
The basic input interface: Three-state buffers are used to construct the 8-bit input port
depicted in figure of parallel port interfacing, the external TTL data (simple toggle
switches in this example) are connected the inputs of the buffers. The outputs of the
buffers connect to the data bus. The exact data bus connections depend on the version
of the microprocessor. For example, the 8088 has data bus connections D7-D0, THE
80486 has D31-D0, and the Pentium-Pentium ІІ have D63-D0.
When the microprocessor executes an IN instruction, the I/O port address is decoded
to generate logic 0. A 0 placed on the output control inputs of the 74ALS244 buffer
causes the data input connections (A) to be connected to the data output (Y)
connections. If a logic 1 is placed on the output controls input of the 74ALS244
buffer, the device enters the three-state high-impedance mode that effectively
disconnects the switches from the data bus.
The basic output interface: The basic output interface receives data from the
microprocessor and must usually hold it for some external device. Its latches or flip-
flops, like the buffers found in the input device, are often built into the I/O device.
When the OUT instructions executes, the data from AL, AX, or EAX are transferred
to the latch via data bus. Here, the D inputs of a 74ALS374 octal latch are connected
to the data bus to capture the output data, and the Q outputs of the latch are attached
to the LED’s, when a Q output becomes logic 0, the LED lights. Each time that the
OUT instruction executes, the SEL signal to the latch activates, capturing the data
output to the latch from any 8-bit section of the data bus. The data are held until the
next OUT instruction executes. Thus, whenever the output instruction is executed in
this circuit, the data from the AL register appear on the LED’s.

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Microprocessor Architecture & Programming 2

Components List:
• ULN2803 programmable interface IC
• DB-25 male Connector
• 8 switchable LED’s
• 8 resistors of 220Ω
• Jumper wires for connections
• war board
• 5-9 volts battery

Circuit diagram:

Parallel Port Interfacing

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Microprocessor Architecture & Programming 3

Procedure:
Make connections of ULN2803 programmable interface IC from pin 1-8 to pin 2-9 of
DB-25 respectively and give a ground connection from pin 18-25 of DB-25 connector
respectively including pin 9 of ULN2803 and keep remaining pins short DB-25, now
connect the LED’s and 220Ω resistors from pin 11-18 respectively, vice versa.
Connect the VCC to pin 10 and get connect to all the outer connections of resistors.
Get the LED’s ON/OFF by giving source of 5-9 volts to make sure that the
connections are right and up to the mark. Connect DB-25 to PC hardware and check
by user’s desired program to switch LED’s ON/OFF by particular time delay.

ULN2803:
The ULN2803APG / AFWG Series are high voltage,
High current Darlington drivers comprised of eight NPN
Darlington pairs.
All units feature integral clamp diodes for switching inductive
Loads.
Applications include relay, hammer, lamp and display (LED)
Drivers.
The suffix (G) appended to the part number represents a Lead
(Pb)-Free product.

Features:
• Output current (single output)500 mA (Max.)
• High sustaining voltage output 50 V (Min.)
• Output clamp diodes
• Inputs compatible with various types of logic.
• Package Type−APG : DIP−18pin
• Package Type−AFWG : SOL−18pin

Maximum Ratings:
The device has several operating modes dependent on the applied voltages to the S1
and S0 pins as shown in Table 1. In all the modes listed the channel multiplexers, D/A
Register, LFO, and the output pulse dividers will always be powered up as long as
there is a voltage source connected to the VDD pin. When only the S0 pin is at a
logic one the pressure measuring circuit in the device is powered up and the pressure
output signal is connected to the sample capacitor through a multiplexer. When the S0
pin returns to the low state the multiplexer will first turn off to store the signal on the
sample capacitor before powering down the measuring circuitry. When only the S1
pin is at a logic one the temperature measuring circuit in the device is powered up and
the temperature output signal is connected to the sample capacitor through a
multiplexer. When the S1 pin returns to the low state the multiplexer will first turn off
to store the signal.

Pin out:

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Microprocessor Architecture & Programming 4

NOTES:A. CL includes probe and jig capacitance.

B. All input pulses are supplied by generators having the following characteristics:
PRR 1 MHz, ZO = 50 Ω, tr
C. The outputs are measured one at a time with one input transition per measurement.
Notes: 1. H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care Z =
HIGH Impedance On = Previous state of flip flops (Qn-1) 2. Unless otherwise noted,
these limits are over the operating free-air temperature range. 3. Unused inputs must
always be connected to an appropriate logic voltage level, preferably either VCC or
ground. 4. TA is the instant on case temperature. 5. Typical values are at
VCC=5.0V, TA=+25˚C ambient. 6. This parameter is specified but not tested. 7. Not
more than one output should be shorted at a time. Duration of short should not exceed
one second. The use of high-speed test apparatus and/or sample and hold techniques
is preferable in order to minimize internal chip heating and more accurately reflect
operational values. Otherwise prolonged shorting of a high output may raise the chip
temperature well above normal and thereby cause invalid readings in other parametric
tests. In any sequence of parameter tests, IOS tests should be performed last.
plex Instruction Set Computer (CISC): compact code, on- chip memory and I/O, and
reduced cost. The CPU uses a three-stage instruction pipeline that allows execution of
up to one instruction per clock cycle, or up to 25 million instructions per second
(MIPS) at a clock rate of 24 MHz.

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