QUESTION BANK & TUTORIAL

CMOS TECHNOLOGY(BETL 710)

UNIT 1

Q1. Design NAND and NOR Gate of three inputs by using NMOS and PMOS.
Q2. Explain VLSI Design flow with neat diagram.
Q3. Describe the concept of Pass transistor and Transmission gates with example.
Q4. Explain basic 10 step process for CMOS fabrication.
Q5. Describe layout design rules.
Q6. Design a multiplexer using CMOS logic.
Q7. Draw stick diagram for CMOS XOR gate and 3 input NOR Gate.
Q8. Design a layout and stick diagram for two input NAND Gate.
Q9. What are various symbols used in stick notation? Draw stick diagram of CMOS inverter?
Q10.Design the static complementary pull-up and pull-down networks for the logic
expression: f( A,B,C,D)=(A+B)(C+D).
Q11. What are lambda- based design rules? Explain design rules for wires and MOS transistors.

UNIT 2

Q1. Draw ideal I-V characteristics of MOS transistor and discuss non ideal I-V effects in detail.
Q2. Explain beta ratio effect? How it affects the noise margin of CMOS inverter?
Q3.Write short note on a) subthreshold conduction, b) junction leakage, c) tunneling.
Q4. Write short note on Channel length modulation and body effect in MOS.
Q5. Explain MOS Capacitance Model with neat diagram.
Q6. Draw the CMOS inverter DC transfer characteristics and explain its operation, clearly
indicating the various regions.

Q7. Design a CMOS inverter for NML=NMH=1.5V. Given, VDD=5V, Vthn=0.6V, Vthp=-
0.6V.

Q8. If VDD=5V, Vthn=0.6V, Vthp=-0.6V, find operating region of PMOS and NMOS in a
CMOS inverter.

UNIT 3

Q1. Explain with neat diagram the photolithographic process used in CMOS Technology.
Q2. Explain well and channel formation in CMOS.
Q3. Explain gate and source/drain formation in CMOS.
Q4. Write short note on a) Passivation
b) Contacts and Metallization.

UNIT 4

Q1. Explain Static and dynamic power dissipation in CMOS circuits and also define different
methods to reduce it?
 Q2. Sketch a 3 input NAND gate with transistor width chosen to achieve effective rise and fall
resistance equal to that of unit inverter.
Q3. Define the linear delay model.

Q4.A ring oscillator is constructed from an odd number of inverters. Estimate the frequency of N
stage ring oscillator.
Q5. Derive the expression for power dissipation in CMOS circuits.
Q6. Write short note on a) Gate transistor sizing
b) VLSI Interconnects.
Q7. Compare static and dynamic power dissipation.
Q8. Explain static and dynamic power reduction.
Q9. Describe Delay estimation in CMOS.
Q10. Describe Elmore Delay Model.

UNIT 5

Q1.Write short note on SRAM and DRAM.

Q2. Explain Programmable Logic Arrays.
Q3. What is content addressable memory? Describe it.

Q4. Write the equations for a full adder in sum of product form. Sketch a 3 input, 2 output PLA
implementation.
Q5. Draw stick diagram of 6T SRAM cell.
Q6. Explain in brief a) Read only memory
b) Programmable ROMs.
Q7. Explain the basic concept of FIFO, LIFO and shift register.