Problems        647

12-17. A small TLB has the following entries for a virtual page number of length
20 bits, a physical page number of 12 bits, and a page offset of 12 bits.

Valid Dirty Tag Data

Bit Bit (Virtual Page (Physical Page
Number) Number)

1 1 01AF4 FFF
0 0 0E45F E03
0 0 0123G 2F8
1 0 01A37 788
1 0 02BC4 48C
0 1 03CA0 657

The page numbers and offset are given in hexadecimal. For each virtual
a­ ddress listed, indicate whether a hit occurs, and if it does, give the physical
address: (a) 02BB4A65, (b) 0E45FB32, (c) 0D34E9DC, and (d) 03CA0788.
12-18. A computer can accommodate a maximum of 384 MB of main memory. It has
a 32-bit word and a 32-bit virtual address and uses 4 KB pages. The TLB
contains only entries that include the Valid, Dirty, and Used bits, the virtual
page number, and the physical page number. Assuming that the TLB is fully
associative and has 32 entries, determine the following:
(a) How many bits of associative memory are required for the TLB?
(b) How many bits of SRAM are required for the TLB?
12-19. Four programs are concurrently executing in a multitasking computer with
virtual memory pages having 4 KB. Each page table entry is 32 bits. What is
the minimum numbers of bytes of main memory occupied by the directory
pages and page tables for the four programs if the numbers of pages per
program, in decimal, are as follows: 3124, 5670, 1205, and 2069?
12-20. *In caches, we use both write-through and write-back as potential writing
approaches. But for virtual memory, only an approach that resembles write-
back is used. Give a sound explanation of why this is so.
12-21. Explain clearly why both the cache memory concept and the virtual memory
concept would be ineffective if locality of reference of memory-addressing
patterns did not hold.