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ECE 410 Homework 1-Solutions Spring 2013

Problem 1 Vo
Find the output voltage, Vo, for the nFET shown to the right for the following cases.
Assume Vg = 2V and Vtn = 0.7V Vg
(a) Vi = 0.5V
Vi
Here Vg-Vi = 1.5 > Vtn, so Vo = Vi = 0.5V
(b) Vi = 1.4V
Here Vg-Vi = 0.6 < Vtn, so Vo = Vg-Vth = 1.3V
(c) Vi = 2.5V
Here Vg-Vi = -0.5 < Vtn, so Vo = Vg – Vtn = 1.3V

Problem 2 Vi
Find the output voltage, Vo, for the pFET shown to the right for the following cases.
Assume Vg = 0V and Vtp = -0.6V Vg
(a) Vi = 0.3V
Vo
Here Vi-Vg = 0.3 < |Vtp|, so Vo = Vg+|Vtp| = 0.6V
(b) Vi = 1.5V
Here Vi-Vg = 1.5 > |Vtp|, so Vo = Vi = 1.5V
(c) Vi = 3V
Here Vi-Vg = 3 > |Vtp|, so Vo = Vi = 3V

Problem 3
Find the midpoint voltage, Vx, and output voltage, Vo, for the chain of two nFET pass transistors
shown below for the following cases. Assume VDD = 1 V and Vtn = 0.5V.
(a) Vi = 0V VDD VDD
Here VDD-Vi = 1 > Vtn, so Vx = Vi = 0V
Vi Vo
and VDD-Vx = 1 > Vtn, so Vo = Vx = 0V
Vx
notice this shows that two series nMOS can pull the
output to ground when the Vi node is at ground (as in a NAND gate).
(b) Vi = 0.4V
Here VDD-Vi = 0.6 > Vtn, so Vx = Vi = 0.4V
and VDD-Vx = 0.6 > Vtn, so Vo = Vx = 0.4V
(c) Vi = 1 V
Here VDD-Vi = 0 < Vtn, so Vx = VDD-Vtn = 0.5V
and VDD-Vx = 0.5 = Vtn, so Vo = Vx = 0.5V

Problem 4
Using fundamental logic properties, prove the following logic relationships
(a) (a+b)(a+c) = a+bc
first expand the term (use the FOIL method of mathematics)
(a+b)(a+c) = aa + ab + ac + bc = a + ab + ac + bc (since a⋅a = a)
= a (1+b) + ac + bc = a + ac + bc (since 1+b = 1 and a⋅1 = a)
= a (1+c) + bc
= a + bc (since 1+c = 1 and a⋅1 = a)

(b) a + a'b = a + b
First the easy way. Since we know from part (a) above that x+yz = (x+y)(x+z)
let x = a, y = a’, and z=b
thus a+a’b = (a+a’)(a+b)
= a+b (since a+a’ = 1)
Or, if we stick with the ‘fundamental properties’ we can follow the steps in
part (a) in reverse
a+a’b = a(1+a’) + a’b = a +aa’ + a’b
= a(1+b) + aa’ + a’b = a + ab +aa’ + a’b
= (a+a’)(a+b) = a+b (because a+a’ = 1 and 1(a+b) = a+b

Problem 5
Construct the CMOS logic gate for the function f = x + ( y + z ). y . Start with the minimum-
transistor nFET network and then apply bubble pushing to construct the pFET network.
First, setup the nMOS equation and reduce it.
Fn = f = x+(y+z).y = x + y.y + zy = x+y+zy=x+(1+z)y
= x + y, which gives the nFET gate logic diagram shown below
Then, apply bubble pushing to create the pFET gate diagram shown below.
Finally, map both gate diagrams to transistors to implement the CMOS
circuit below.

y
x f
y

x y
f
y

Problem 6
Design a CMOS logic gate for the function f = a ⋅ b + a ⋅ c + b ⋅ c using the least number of
transistors.
First, setup the nMOS equation and reduce it.
Fn = ab+ac+bc = a(b+c)+bc
Since we can not reduce this further, this last equation will give the least
number of transistors (5txs).
Next implement this equation in nMOS transistors and complement the
operation to complete the pMOS portion of the circuit. The final result is shown
here.
NOTE: there are correct alternatives to this circuit depending on which
terms you decided to combine when you reduced the equation. Note, however, that
in layouts, it may be better to realize the original equation form (needs 6 txs)
because of symmetry and uniform transistor sizes.

b
a
c

cd b
f

a b

b c cd

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