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Release 13.2 Trace (nt64)

Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.

C:\Xilinx\13.2\ISE_DS\ISE\bin\nt64\unwrapped\trce.exe -intstyle ise -v 3 -s 5

-n 3 -fastpaths -xml exam_top.twx exam_top.ncd -o exam_top.twr exam_top.pcf

Design file: exam_top.ncd

Physical constraint file: exam_top.pcf
Device,package,speed: xc3s50,pq208,-5 (PRODUCTION 1.39 2011-06-20)
Report level: verbose report

Environment Variable Effect

-------------------- ------
NONE No environment variables were set
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INFO:Timing:2698 - No timing constraints found, doing default enumeration.

INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
option. All paths that are not constrained will be reported in the
unconstrained paths section(s) of the report.
INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on
a 50 Ohm transmission line loading model. For the details of this model,
and for more information on accounting for different loading conditions,
please see the device datasheet.
INFO:Timing:3390 - This architecture does not support a default System Jitter
value, please add SYSTEM_JITTER constraint to the UCF to modify the Clock
Uncertainty calculation.
INFO:Timing:3389 - This architecture does not support 'Discrete Jitter' and
'Phase Error' calculations, these terms will be zero in the Clock
Uncertainty calculation. Please make appropriate modification to
SYSTEM_JITTER to account for the unsupported Discrete Jitter and Phase
Error.

Data Sheet report:

-----------------
All values displayed in nanoseconds (ns)

Setup/Hold to clock clk

------------+------------+------------+------------------+--------+
|Max Setup to|Max Hold to | | Clock |
Source | clk (edge) | clk (edge) |Internal Clock(s) | Phase |
------------+------------+------------+------------------+--------+
last_block | 0.128(R)| 0.861(R)|clk_BUFGP | 0.000|
m<0> | 1.126(R)| 0.055(R)|clk_BUFGP | 0.000|
m<1> | 1.481(R)| -0.229(R)|clk_BUFGP | 0.000|
m<2> | 2.083(R)| -0.087(R)|clk_BUFGP | 0.000|
m<3> | 1.524(R)| -0.267(R)|clk_BUFGP | 0.000|
m<4> | 1.938(R)| -0.382(R)|clk_BUFGP | 0.000|
m<5> | 2.428(R)| -0.459(R)|clk_BUFGP | 0.000|
m<6> | 1.651(R)| -0.088(R)|clk_BUFGP | 0.000|
m<7> | 2.865(R)| -0.518(R)|clk_BUFGP | 0.000|
src_ready | 4.292(R)| 0.166(R)|clk_BUFGP | 0.000|
------------+------------+------------+------------------+--------+

Clock clk to Pad

------------+------------+------------------+--------+
 | clk (edge) | | Clock |
Destination | to PAD |Internal Clock(s) | Phase |
------------+------------+------------------+--------+
src_read | 8.684(R)|clk_BUFGP | 0.000|
y<0> | 7.707(R)|clk_BUFGP | 0.000|
y<1> | 7.780(R)|clk_BUFGP | 0.000|
y<2> | 7.804(R)|clk_BUFGP | 0.000|
y<3> | 8.095(R)|clk_BUFGP | 0.000|
y<4> | 7.104(R)|clk_BUFGP | 0.000|
y<5> | 7.403(R)|clk_BUFGP | 0.000|
y<6> | 7.078(R)|clk_BUFGP | 0.000|
y<7> | 7.055(R)|clk_BUFGP | 0.000|
------------+------------+------------------+--------+

Clock to Setup on destination clock clk

---------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clk | 5.481| | | |
---------------+---------+---------+---------+---------+

Pad to Pad
---------------+---------------+---------+
Source Pad |Destination Pad| Delay |
---------------+---------------+---------+
src_ready |src_read | 6.930|
---------------+---------------+---------+

Analysis completed Thu Dec 29 17:54:57 2011

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Trace Settings:
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Trace Settings

Peak Memory Usage: 121 MB