CA555, CA555C,

S E M I C O N D U C T O R
LM555, LM555C, NE555
Timers for Timing Delays and Oscillator Application
May 1997 in Commercial, Industrial and Military Equipment

Features Description
• Accurate Timing From Microseconds Through Hours The CA555 and CA555C are highly stable timers for use in
• Astable and Monostable Operation precision timing and oscillator applications. As timers, these
• Adjustable Duty Cycle
monolithic integrated circuits are capable of producing accu-
• Output Capable of Sourcing or Sinking up to 200mA
• Output Capable of Driving TTL Devices rate time delays for periods ranging from microseconds
• Normally ON and OFF Outputs through hours. These devices are also useful for astable
• High Temperature Stability . . . . . . . . . . . . . . 0.005%/oC oscillator operation and can maintain an accurately con-
• Directly Interchangeable with SE555, NE555, MC1555, trolled free running frequency and duty cycle with only two
and MC1455 external resistors and one capacitor.
Applications The circuits of the CA555 and CA555C may be triggered by
• Precision Timing • Pulse Generation the falling edge of the waveform signal, and the output of
• Sequential Timing • Pulse Detector these circuits can source or sink up to a 200mA current or
• Time Delay Generation • Pulse Width and Position drive TTL circuits.
Modulation These types are direct replacements for industry types in
Ordering Information packages with similar terminal arrangements e.g. SE555
PART NUMBER TEMP. PKG. and NE555, MC1555 and MC1455, respectively. The CA555
(BRAND) RANGE (oC) PACKAGE NO. type circuits are intended for applications requiring premium
CA0555E -55 to 125 8 Ld PDIP E8.3 electrical performance. The CA555C type circuits are
CA0555M (555) -55 to 125 8 Ld SOIC M8.15 intended for applications requiring less stringent electrical
CA0555M96 (555) -55 to 125 8 Ld SOIC † M8.15 characteristics.
CA0555T -55 to 125 8 Pin Metal Can T8.C
CA0555CE 0 to 70 8 Ld PDIP E8.3
CA0555CM (555C) 0 to 70 8 Ld SOIC M8.15
CA0555CM96 (555C) 0 to 70 8 Ld SOIC † M8.15
CA0555CT 0 to 70 8 Pin Metal Can T8.C
LM555N -55 to 125 8 Ld PDIP E8.3
LM555CN 0 to 70 8 Ld PDIP E8.3
NE555N 0 to 70 8 Ld PDIP E8.3
NOTE: † Denotes Tape and Reel

Pinouts Functional Block Diagram

CA555, CA555C (PDIP, SOIC)
LM555, LM555C, NE555 (PDIP) V+ TRIGGER
CONTROL
TOP VIEW 8 VOLTAGE 5 2

GND 1 8 V+

TRIGGER 2 7 DISCHARGE
TRIGGER
OUTPUT
THRESHOLD

OUTPUT 3 6 THRESHOLD COMPAR

3
RESET 4 5 CONTROL 6
VOLTAGE OUTPUT
DISCHARGE

THRESHOLD
CA555, CA555C (METAL CAN) COMPAR
TOP VIEW 7
V+
RESET

TAB
FLIP-FLOP
8 4
GND 1 7 DISCHARGE

TRIGGER 2 6 THRESHOLD
1
GND
OUTPUT 3 5 CONTROL
4 VOLTAGE
RESET

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. File Number 834.4
Copyright © Harris Corporation 1997
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 CA555, CA555C, LM555, LM555C, NE555

Absolute Maximum Ratings Thermal Information

DC Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18V Thermal Resistance (Typical, Note 1) θJA (oC/W) θJC (oC/W)
Metal Can Package . . . . . . . . . . . . . . . 170 85
Operating Conditions PDIP Package . . . . . . . . . . . . . . . . . . . 100 N/A
SOIC Package . . . . . . . . . . . . . . . . . . . 160 N/A
Temperature Range Maximum Junction Temperature (Hermetic Package) . . . . . . . . 175oC
CA555, LM555 . . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC
CA555C, LM555C, NE555 . . . . . . . . . . . . . . . . . . . . .0oC to 70oC Maximum Storage Temperature Range . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:
1. θJA is measured with the component mounted on an evaluation PC board in free air.

Electrical Specifications TA = 25oC, V+ = 5V to 15V Unless Otherwise Specified

CA555, LM555 CA555C, LM555C, NE555

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX MIN TYP MAX UNITS

DC Supply Voltage V+ 4.5 - 18 4.5 - 16 V

DC Supply Current (Low State), I+ V+ = 5V, RL = ∞ - 3 5 - 3 6 mA

(Note 2)
V+ = 15V, RL = ∞ - 10 12 - 10 15 mA

Threshold Voltage VTH - (2/3)V+ - - (2/3)V+ - V

Trigger Voltage V+ = 5V 1.45 1.67 1.9 - 1.67 - V

V+ = 15V 4.8 5 5.2 - 5 - V

Trigger Current - 0.5 - - 0.5 - µA

Threshold Current (Note 3) ITH - 0.1 0.25 - 0.1 0.25 µA

Reset Voltage 0.4 0.7 1.0 0.4 0.7 1.0 V

Reset Current - 0.1 - - 0.1 - mA

Control Voltage Level V+ = 5V 2.9 3.33 3.8 2.6 3.33 4 V

V+ = 15V 9.6 10 10.4 9 10 11 V

Output Voltage VOL V+ = 5V, ISINK = 5mA - - - - 0.25 0.35 V

Low State ISINK = 8mA - 0.1 0.25 - - - V

V+ = 15V, ISINK = 10mA - 0.1 0.15 - 0.1 0.25 V

ISINK = 50mA - 0.4 0.5 - 0.4 0.75 V

ISINK = 100mA - 2.0 2.2 - 2.0 2.5 V

ISINK = 200mA - 2.5 - - 2.5 - V

Output Voltage VOH V+ = 5V, ISOURCE = 100mA 3.0 3.3 - 2.75 3.3 - V

High State V+ = 15V, ISOURCE = 100mA 13.0 13.3 - 12.75 13.3 - V

ISOURCE = 200mA - 12.5 - - 12.5 - V

Timing Error (Monostable) R1, R2 = 1kΩ to 100kΩ, - 0.5 2 - 1 - %

C = 0.1µF
Frequency Drift with Temperature Tested at V+ = 5V, V+ = 15V - 30 100 - 50 - ppm/oC

Drift with Supply Voltage - 0.05 0.2 - 0.1 - %/V

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 CA555, CA555C, LM555, LM555C, NE555

Electrical Specifications TA = 25oC, V+ = 5V to 15V Unless Otherwise Specified (Continued)

CA555, LM555 CA555C, LM555C, NE555

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX MIN TYP MAX UNITS

Output Rise Time tR - 100 - - 100 - ns

Output Fall Time tF - 100 - - 100 - ns

NOTES:
2. When the output is in a high state, the DC supply current is typically 1mA less than the low state value.
3. The threshold current will determine the sum of the values of R1 and R2 to be used in Figure 4 (astable operation); the maximum total
R1 + R2 = 20MΩ.

Schematic Diagram
THRESHOLD TRIGGER
V+
COMPARATOR COMPARATOR FLIP-FLOP OUTPUT
8

4.7K 830 4.7K 1K 5K 6.8K

D1 D2
Q10 Q16

Q3 Q4 Q19

Q20
OUTPUT
3.9K 3
7K
THRESHOLD
6 Q1 Q7

Q2 Q5 D3
4.7K D4

5K
10K
Q11 Q12 Q18
CONTROL
220
VOLTAGE Q21
Q9 Q13 Q17
5
Q15
2 5K 4.7K
TRIGGER Q14
RESET
100K
4 Q8
RESET
7
DISCHARGE Q6
1 DISCHARGE 100

V-

NOTE: Resistance values are in ohms.

Typical Applications
Reset Timer (Monostable Operation)
Figure 1 shows the CA555 connected as a reset timer. In this
mode of operation capacitor CT is initially held discharged by
a transistor on the integrated circuit. Upon closing the “start”
switch, or applying a negative trigger pulse to terminal 2, the
integral timer flip-flop is “set” and releases the short circuit
across CT which drives the output voltage “high” (relay ener-
gized). The action allows the voltage across the capacitor to
increase exponentially with the constant t = R1CT. When the
voltage across the capacitor equals 2/3 V+, the comparator
resets the flip-flop which in turn discharges the capacitor rap-
idly and drives the output to its low state.

8-5
 CA555, CA555C, LM555, LM555C, NE555

V+ 100
RESET 5V
TA = 25oC
R1 680 V+ = 5V
4
10
7 8

CAPACITANCE (µF)
EO
CA555 3 R1 = 1kΩ
1
1N4001 10kΩ
6 5 100kΩ
1
2 10K 0.1 1MΩ
RELAY 10MΩ
CT 4.7K COIL
680
0.01µF 0.01
S1
START
0.001
10-5 10-4 10-3 10-2 10-1 1 10
TIME DELAY(s)
NOTE: All resistance values are in ohms.
FIGURE 3. TIME DELAY vs RESISTANCE AND CAPACITANCE
FIGURE 1. RESET TIMER (MONOSTABLE OPERATION)
Repeat Cycle Timer (Astable Operation)
Since the charge rate and threshold level of the comparator
are both directly proportional to V+, the timing interval is rel- Figure 4 shows the CA555 connected as a repeat cycle
atively independent of supply voltage variations. Typically, timer. In this mode of operation, the total period is a function
the timing varies only 0.05% for a 1V change in V+. of both R1 and R2.
Applying a negative pulse simultaneously to the reset termi-
V+
nal (4) and the trigger terminal (2) during the timing cycle 5V
discharges CT and causes the timing cycle to restart. R1
Momentarily closing only the reset switch during the timing 4
interval discharges CT, but the timing cycle does not restart. 7 8
EO
Figure 2 shows the typical waveforms generated during this R2 CA555 3
mode of operation, and Figure 3 gives the family of time
6 5 RELAY
delay curves with variations in R1 and CT.
1 COIL
2
SWITCH S1 “OPEN”
3V
INPUT
VOLTAGE (TERMINAL 2) CT 0.01µF
SWITCH S1 “CLOSED”
0

3.3V
CAPACITOR FIGURE 4. REPEAT CYCLE TIMER (ASTABLE OPERATION)
VOLTAGE (TERMINALS 6, 7)
0 T = 0.693 (R1 + 2R2) CT = t1 + t2
tD
where t1 = 0.693 (R1 + R2) CT
5V
and t2 = 0.693 (R2) CT
OUTPUT
VOLTAGE the duty cycle is:
(TERMINAL 3)
0 t1 R1 + R2
---------------- = ------------------------
t 1 + t 2 R 1 + 2R 2
FIGURE 2. TYPICAL WAVEFORMS FOR RESET TIMER
Typical waveforms generated during this mode of operation
are shown in Figure 5. Figure 6 gives the family of curves of
free running frequency with variations in the value of
(R1 + 2R2) and CT .

8-6
 CA555, CA555C, LM555, LM555C, NE555

t2
t1 100
TA = 25oC, V+ = 5V
5V

10

CAPACITANCE (µF)
R1 + 2R2 = 1kΩ
1 10kΩ
0 100kΩ
1MΩ
0.1 10MΩ
3.3V

0.01
1.7V

0.001
10-1 1 10 102 103 104 105
0
FREQUENCY (Hz)
Top Trace: Output voltage (2V/Div. and 0.5ms/Div.)
Bottom Trace: Capacitor voltage (1V/Div. and 0.5ms/Div.)

FIGURE 5. TYPICAL WAVEFORMS FOR REPEAT CYCLE TIMER FIGURE 6. FREE RUNNING FREQUENCY OF REPEAT CYCLE
TIMER WITH VARIATION IN CAPACITANCE AND
RESISTANCE

Typical Performance Curves

MINIMUM PULSE WIDTH (ns)

150
10 TA = 125oC
9
SUPPLY CURRENT (mA)

TA = -55oC 8
100 25oC
7
0oC
6
50oC
25oC 5
50 70oC 4
125oC 3
2
1
0 0.1 0.2 0.3 0.4
MINIMUM TRIGGER (PULSE) VOLTAGE (x V+) (NOTE) 0 2.5 5 7.5 10 12.5 15
SUPPLY VOLTAGE (V)
NOTE: Where x is the decimal multiplier of the supply voltage.
FIGURE 7. MINIMUM PULSE WIDTH vs MINIMUM TRIGGER FIGURE 8. SUPPLY CURRENT vs SUPPLY VOLTAGE
VOLTAGE
2.0 10.0
SUPPLY VOLTAGE - OUTPUT VOLTAGE (V)

TA = -55oC V+ = 5V
OUTPUT VOLTAGE - LOW STATE (V)

1.6 TA = -55oC
25oC
25oC
1.0 125oC
1.2
125oC

0.8
0.1

0.4
5V ≤ V+ ≤ 15V

0 0.01
1 10 100 1 10 100
SOURCE CURRENT (mA) SINK CURRENT (mA)

FIGURE 9. OUTPUT VOLTAGE DROP (HIGH STATE) vs FIGURE 10. OUTPUT VOLTAGE LOW STATE vs SINK
SOURCE CURRENT CURRENT

8-7
 CA555, CA555C, LM555, LM555C, NE555

Typical Performance Curves (Continued)

10.0 10.0
V+ = 10V V+ = 15V

OUTPUT VOLTAGE - LOW STATE (V)

OUTPUT VOLTAGE - LOW STATE (V)

-55oC
TA = -55oC

1.0 1.0
25oC
125oC
125oC 125oC
25oC 25oC
0.1 0.1 TA = -55oC

0.01 0.01
1 10 100 1 10 100
SINK CURRENT (mA) SINK CURRENT (mA)

FIGURE 11. OUTPUT VOLTAGE LOW STATE vs SINK FIGURE 12. OUTPUT VOLTAGE LOW STATE vs SINK
CURRENT CURRENT

1.100
TA = 25oC
NORMALIZED DELAY TIME

1.000
1.005
NORMALIZED DELAY TIME

0.990
0.995

0.980 0.985
0 2.5 5 7.5 10 12.5 15 17.5 -75 -50 -25 0 25 50 75 100 125

SUPPLY VOLTAGE (V) TEMPERATURE (oC)

FIGURE 13. DELAY TIME vs SUPPLY VOLTAGE FIGURE 14. DELAY TIME vs TEMPERATURE

300
PROPAGATION DELAY TIME (ns)

250

200
TA = -55oC

150

100 0 oC
25oC
50 70oC
125oC

0 0.1 0.2 0.3 0.4

MINIMUM TRIGGER (PULSE) VOLTAGE (x V+) (NOTE)

NOTE: Where x is the decimal multiplier of the supply voltage.

FIGURE 15. PROPAGATION DELAY TIME vs TRIGGER VOLTAGE

8-8
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