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FEATURES SUMMARY
■ 2.7 TO 5.5V OPERATING VOLTAGE Figure 1. 16-pin SOIC Package
■ SERIAL PERIPHERAL INTERFACE (SPI)
■ 2.5 TO 5.5V OSCILLATOR OPERATING
VOLTAGE 16
Rev. 2.0
M41T94
TABLE OF CONTENTS
SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 3. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 4. 16-pin SOIC Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 5. 28-pin SOIC Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 6. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 7. Hardware Hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 2. Function Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 3. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 4. DC and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 9. AC Testing Input/Output Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 5. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 6. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 7. Crystal Electrical Characteristics (Externally Supplied) . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
CLOCK OPERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
TIMEKEEPER® Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 10. TIMEKEEPER® Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2/31
M41T94
Power-on Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Century Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
tREC Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 21. SNAPHAT Battery Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3/31
M41T94
SUMMARY DESCRIPTION
The M41T94 Serial TIMEKEEPER® SRAM is a made automatically. The ninth clock address loca-
low power, 512-bit static CMOS SRAM organized tion controls user access to the clock information
as 64 words by 8 bits. A built-in 32,768 Hz oscilla- and also stores the clock software calibration set-
tor (external crystal controlled) and 8 bytes of the ting.
SRAM (see Table 10, page 17) are used for the The M41T94 is supplied in either a 16-lead plastic
clock/calendar function and are configured in bina- SOIC (requiring user supplied crystal and battery)
ry coded decimal (BCD) format. or a 28-lead SOIC SNAPHAT® package (which in-
An additional 12 bytes of RAM provide status/con- tegrates both crystal and battery in a single
trol of Alarm, Watchdog and Square Wave func- SNAPHAT top). The 28-pin, 330mil SOIC provides
tions. Addresses and data are transferred serially sockets with gold plated contacts at both ends for
via a serial SPI interface. The built-in address reg- direct connection to a separate SNAPHAT hous-
ister is incremented automatically after each ing containing the battery and crystal. The unique
WRITE or READ data byte. The M41T94 has a design allows the SNAPHAT battery/crystal pack-
built-in power sense circuit which detects power age to be mounted on top of the SOIC package af-
failures and automatically switches to the battery ter the completion of the surface mount process.
supply when a power failure occurs. The energy Insertion of the SNAPHAT housing after reflow
needed to sustain the SRAM and clock operations prevents potential battery and crystal damage due
can be supplied by a small lithium button-cell sup- to the high temperatures required for device sur-
ply when a power failure occurs. Functions avail- face-mounting. The SNAPHAT housing is also
able to the user include a non-volatile, time-of-day keyed to prevent reverse insertion.
clock/calendar, Alarm interrupts, Watchdog Timer
The SOIC and battery/crystal packages are
and programmable Square Wave output. Other
shipped separately in plastic anti-static tubes or in
features include a Power-On Reset as well as two
additional debounced inputs (RSTIN1 and Tape & Reel form. For the 28-lead SOIC, the bat-
tery/crystal package (e.g., SNAPHAT) part num-
RSTIN2) which can also generate an output Reset
ber is “M4TXX-BR12SH” (see Table 21, page 29).
(RST). The eight clock address locations contain
the century, year, month, date, day, hour, minute, Caution: Do not place the SNAPHAT battery/crys-
second and tenths/hundredths of a second in 24 tal top in conductive foam, as this will drain the lith-
hour BCD format. Corrections for 28, 29 (leap year ium button-cell battery.
- valid until year 2100), 30 and 31 day months are
4/31
M41T94
Interrupt/Frequency Test/Out
IRQ/FT/OUT
(1)
Output (Open Drain)
VCC VBAT
RST Reset Output (Open Drain)
VSS Ground
Note: 1. For SO16 package only. Note: 1. For SO16 package only.
SQW 1 28 VCC
NC 2 27 E
NC 3 26 IRQ/FT/OUT
XI 1 16 VCC
NC 4 25 NC
XO 2 15 E
NC 5 24 NC
RST 3 14 IRQ/FT/OUT
NC 6 23 THS
WDI 4 13 THS
M41T94 NC 7 22 NC
RSTIN1 5 12 SDI M41T94
WDI 8 21 NC
RSTIN2 6 11 SQW
RSTIN1 9 20 SCL
VBAT 7 10 SCL
RSTIN2 10 19 NC
VSS 8 9 SDO
NC 11 18 RST
AI03684 NC 12 17 SDI
NC 13 16 SDO
VSS 14 15 NC
AI03685
5/31
M41T94
WDI
VCC
VBAT
BL
VBL= 2.5V COMPARE
RSTIN2
AI04785
Master
(ST6, ST7, ST9, C Q D C Q D C Q D
ST10, Others)
M41T94 XXXXX XXXXX
AI03686
Note: 1. CPOL (Clock Polarity) and CPHA (Clock Phase) are bits that may be set in the SPI Control Register of the MCU.
6/31
M41T94
Note: 1. SDO remains at High Z until eight bits of data are ready to be shifted out during a READ.
CPOL CPHA
0 0 C
1 1 C
AI04632
Signal Description
Serial Data Output (SDO). The output pin is The M41T94 can be driven by a microcontroller
used to transfer data serially out of the Memory. with its SPI peripheral running in either of the two
Data is shifted out on the falling edge of the serial following modes:
clock. (CPOL, CPHA) = ('0', '0') or
Serial Data Input (SDI). The input pin is used to (CPOL, CPHA) = ('1', '1').
transfer data serially into the device. Instructions,
addresses, and the data to be written, are each re- For these two modes, input data (SDI) is latched in
ceived this way. Input is latched on the rising edge by the low-to-high transition of clock SCL, and out-
of the serial clock. put data (SDO) is shifted out on the high-to-low
Serial Clock (SCL). The serial clock provides the transition of SCL (see Table 2, page 7 and Figure
timing for the serial interface (as shown in Figure 8, page 7).
10, page 12 and Figure 11, page 12). The W/R Bit, Chip Enable (E). When E is high, the memory
addresses, or data are latched, from the input pin, device is deselected, and the SDO output pin is
on the rising edge of the clock input. The output held in its high impedance state.
data on the SDO pin changes state after the falling After power-on, a high-to-low transition on E is re-
edge of the clock input. quired prior to the start of any operation.
7/31
M41T94
MAXIMUM RATING
Stressing the device above the rating listed in the not implied. Exposure to Absolute Maximum Rat-
“Absolute Maximum Ratings” table may cause ing conditions for extended periods may affect de-
permanent damage to the device. These are vice reliability. Refer also to the
stress ratings only and operation of the device at STMicroelectronics SURE Program and other rel-
these or any other conditions above those indicat- evant quality documents.
ed in the Operating sections of this specification is
IO Output Current 20 mA
PD Power Dissipation 1 W
Note: 1. Reflow at peak temperature of 215°C to 225°C for < 60 seconds (total thermal budget not to exceed 180°C for between 90 to 120
seconds).
CAUTION: Negative undershoots below –0.3V are not allowed on any pin while in the Battery Back-up mode.
CAUTION: Do NOT wave solder SOIC to avoid damaging SNAPHAT sockets.
8/31
M41T94
DC AND AC PARAMETERS
This section summarizes the operating and mea- ment Conditions listed in the relevant tables. De-
surement conditions, as well as the DC and AC signers should check that the operating conditions
characteristics of the device. The parameters in in their projects match the measurement condi-
the following DC and AC Characteristic tables are tions when using the quoted parameters.
derived from tests performed under the Measure-
0.8VCC
0.7VCC
0.3VCC
0.2VCC
AI02568
Table 5. Capacitance
Symbol Parameter(1,2) Min Max Unit
CIN Input Capacitance 7 pF
9/31
M41T94
Table 6. DC Characteristics
Symb. Parameter Test Condition(1) Min Typ Max Unit
10/31
M41T94
OPERATION
The M41T94 clock operates as a slave device on power supply is switched to external VCC. Write
the SPI serial bus. Each memory device is access- protection continues until VCC reaches VPFD (min)
ed by a simple serial interface that is SPI bus com- plus tREC (min). For more information on Battery
patible. The bus signals are SCL, SDI and SDO Storage Life refer to Application Note AN1012.
(see Table 1, page 5 and Figure 7, page 6). The SPI Bus Characteristics
device is selected when the Chip Enable input (E)
The Serial Peripheral interface (SPI) bus is intend-
is held low. All instructions, addresses and data
are shifted serially in and out of the chip. The most ed for synchronous communication between dif-
significant bit is presented first, with the data input ferent ICs. It consists of four signal lines: Serial
Data Input (SDI), Serial Data Output (SDO), Serial
(SDI) sampled on the first rising edge of the clock
Clock (SCL) and a Chip Enable (E).
(SCL) after the Chip Enable (E) goes low. The 64
bytes contained in the device can then be access- By definition a device that gives out a message is
ed sequentially in the following order: called “transmitter,” the receiving device that gets
the message is called “receiver.” The device that
1. Tenths/Hundredths of a Second Register
controls the message is called “master.” The de-
2. Seconds Register vices that are controlled by the master are called
3. Minutes Register “slaves.”
4. Century/Hours Register The E input is used to initiate and terminate a data
5. Day Register transfer. The SCL input is used to synchronize
data transfer between the master (micro) and the
6. Date Register
slave (M41T94) devices.
7. Month Register
The SCL input, which is generated by the micro-
8. Year Register controller, is active only during address and data
9. Control Register transfer to any device on the SPI bus (see Figure
10. Watchdog Register 7, page 6).
11 - 16.Alarm Registers The M41T94 can be driven by a microcontroller
with its SPI peripheral running in either of the two
17 - 19.Reserved following modes:
20. Square Wave Register (CPOL, CPHA) = ('0', '0') or
21 - 64.User RAM
(CPOL, CPHA) = ('1', '1').
The M41T94 clock continually monitors VCC for an
out-of tolerance condition. Should VCC fall below For these two modes, input data (SDI) is latched in
VPFD, the device terminates an access in progress by the low-to-high transition of clock SCL, and out-
and resets the device address counter. Inputs to put data (SDO) is shifted out on the high-to-low
the device will not be recognized at this time to transition of SCL (see Table 2, page 7 and Figure
prevent erroneous data from being written to the 8, page 7).
device from a an out-of-tolerance system. When There is one clock for each bit transferred. Ad-
VCC falls below VSO, the device automatically dress and data bits are transferred in groups of
switches over to the battery and powers down into eight bits. Due to memory size the second most
an ultra low current mode of operation to conserve significant address bit is a Don’t Care (address bit
battery life. As system power returns and VCC ris- 6).
es above VSO, the battery is disconnected, and the
11/31
M41T94
tEHEL
SCL
tDVCH tCHCL
tCHDX tCLCH
tDLDH
tDHDL
HIGH IMPEDANCE
SDO
AI04633
tCH
SCL
tCLQV tCL tEHQZ
tCLQX
tQLQH
tQHQL
ADDR. LSB IN
SDI
AI04634
12/31
M41T94
Table 8. AC Characteristics
Symbol Parameter(1) Min Max Unit
13/31
M41T94
0 1 2 3 4 5 6 7 8 9 12 13 14 15 16 17 22
SCL
SDI 7 6 5 4 3 2 1 0
MSB
DATA OUT DATA OUT
(BYTE 1) (BYTE 2)
SDO 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
HIGH IMPEDANCE
MSB MSB
AI04635
14/31
M41T94
0 1 2 3 4 5 6 7 8 9 10 15
SCL
SDI 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7
MSB MSB
SDO
HIGH IMPEDANCE
AI04636
VCC
VPFD (max)
VPFD (min)
VSO
tF tR
tFB tRB
tDR tREC
RST
HIGH-Z
OUTPUTS VALID VALID
(PER CONTROL INPUT) (PER CONTROL INPUT)
AI03687
15/31
M41T94
CLOCK OPERATIONS
The eight byte clock register (see Table 10, page ters will be halted. This will prevent a transition of
17) is used to both set the clock and to read the data during the READ.
date and time from the clock, in a binary coded Note: When a power failure occurs, the Halt Up-
decimal format. Tenths/Hundredths of Seconds, date Bit (HT) will automatically be set to a '1.' This
Seconds, Minutes, and Hours are contained within will prevent the clock from updating the clock reg-
the first four registers. Bits D6 and D7 of Clock isters, and will allow the user to read the exact time
Register 03h (Century/Hours Register) contain the of the power-down event. Resetting the HT Bit to
CENTURY ENABLE Bit (CEB) and the CENTURY a '0' will allow the clock to update the clock regis-
Bit (CB). Setting CEB to a '1' will cause CB to tog- ters with the current time.
gle, either from '0' to '1' or from '1' to '0' at the turn
TIMEKEEPER ® Registers
of the century (depending upon its initial state). If
CEB is set to a '0,' CB will not toggle. Bits D0 The M41T94 offers 20 internal registers which
through D2 of Register 04h contain the Day (day contain Clock, Alarm, Watchdog, Flag, Square
of week). Registers 05h, 06h, and 07h contain the Wave and Control data (see Table 10, page 17).
Date (day of month), Month and Years. The ninth These registers are memory locations which con-
clock register is the Control Register (this is de- tain external (user accessible) and internal copies
scribed in the Clock Calibration section). Bit D7 of of the data (usually referred to as BiPORT™ TIME-
Register 01h contains the STOP Bit (ST). Setting KEEPER cells). The external copies are indepen-
this bit to a '1' will cause the oscillator to stop. If the dent of internal functions except that they are
device is expected to spend a significant amount updated periodically by the simultaneous transfer
of time on the shelf, the oscillator may be stopped of the incremented internal copy. The internal di-
to reduce current drain. When reset to a '0' the os- vider (or clock) chain will be reset upon the com-
cillator restarts within one second. pletion of a WRITE to any clock address.
The eight Clock Registers may be read one byte at The system-to-user transfer of clock data will be
a time, or in a sequential block. The Control Reg- halted whenever the clock addresses (00h to 07h)
ister (Address location 08h) may be accessed in- are being written. The update will resume either
dependently. Provision has been made to assure due to a deselect condition or when the pointer in-
that a clock update does not occur while any of the crements to a non-clock or RAM address.
eight clock addresses are being read. If a clock ad- TIMEKEEPER and Alarm Registers store data in
dress is being read, an update of the clock regis- BCD. Control, Watchdog and Square Wave Reg-
isters store data in Binary format.
16/31
M41T94
17/31
M41T94
ACTIVE FLAG
IRQ/FT/OUT HIGH-Z
AI03664
18/31
M41T94
VCC
VPFD
VSO
tREC
IRQ/FT/OUT
HIGH-Z HIGH-Z
AI03920
Watchdog Timer
The watchdog timer can be used to detect an out- end of a Watchdog time-out when the WDS Bit is
of-control microprocessor. The user programs the set to a '1.'
watchdog timer by setting the desired amount of The watchdog timer can be reset by two methods:
time-out into the Watchdog Register, address 09h.
Bits BMB4-BMB0 store a binary multiplier and the 1. a transition (high-to-low or low-to-high) can be
applied to the Watchdog Input pin (WDI), or
two lower order bits RB1-RB0 select the resolu-
tion, where 00 = 1/16 second, 01 = 1/4 second, 2. the microprocessor can perform a WRITE of the
10 = 1 second, and 11 = 4 seconds. The amount Watchdog Register.
of time-out is then determined to be the multiplica- The time-out period then starts over. The WDI pin
tion of the five-bit multiplier value with the resolu- should be tied to VSS if not used. In order to per-
tion. (For example: writing 00001110 in the form a software reset of the watchdog timer, the
Watchdog Register = 3*1 or 3 seconds). original time-out period can be written into the
Note: Accuracy of timer is within ± the selected Watchdog Register, effectively restarting the
resolution. count-down cycle.
If the processor does not reset the timer within the Should the watchdog timer time-out, and the WDS
specified period, the M41T94 sets the WDF Bit is programmed to output an interrupt, a value of
(Watchdog Flag) and generates a watchdog inter- 00h needs to be written to the Watchdog Register
rupt or a microprocessor reset. WDF is reset by in order to clear the IRQ/FT/OUT pin. This will also
reading the Flags Register (0Fh). disable the watchdog function until it is again pro-
grammed correctly. A READ of the Flags Register
The most significant bit of the Watchdog Register
is the Watchdog Steering Bit (WDS). When set to will reset the Watchdog Flag (Bit D7; Register
a '0,' the watchdog will activate the IRQ/FT/OUT 0Fh).
pin when timed-out. When WDS is set to a '1,' the The watchdog function is automatically disabled
watchdog will output a negative pulse on the RST upon power-up and the Watchdog Register is
pin for tREC. The Watchdog register and the AFE, cleared. If the watchdog function is set to output to
ABE, SQWE, and FT Bits will reset to a '0' at the the IRQ/FT/OUT pin and the Frequency Test (FT)
function is activated, the watchdog function pre-
vails and the Frequency Test function is denied.
19/31
M41T94
20/31
M41T94
RSTIN1
tRLRH1
RSTIN2
tRLRH2
(1)
RST
tR1HRH tR2HRH
AI03665
Note: 1. Valid for Ambient Operating Temperature: TA = –40 to 85°C; VCC = 2.7 to 5.5V (except where noted).
2. Pulse width less than 50ns will result in no RESET (for noise immunity).
3. Pulse width less than 20ms will result in no RESET (for noise immunity).
4. Programmable (see Table 14, page 23).
21/31
M41T94
22/31
M41T94
0 1 40 200(1) ms
1 X 50 2000 µs
Note: 1. Default Setting
23/31
M41T94
Frequency (ppm)
20
–20
–40
–60
–80
∆F = -0.038 ppm (T - T )2 ± 10%
0
–100 F C2
T0 = 25 °C
–120
–140
–160
–40 –30 –20 –10 0 10 20 30 40 50 60 70 80
Temperature °C
AI00999
NORMAL
POSITIVE
CALIBRATION
NEGATIVE
CALIBRATION
AI00594B
24/31
M41T94
A2 A
C
B
e CP
E H
1
A1 α L
SO-b
Table 16. SO16 – 16-lead Plastic Small Outline Package Mechanical Data
millimeters inches
Symbol
Typ. Min. Max. Typ. Min. Max.
A – – 1.75 – – 0.069
A1 – 0.10 0.25 – 0.004 0.010
A2 – – 1.60 – – 0.063
B – 0.35 0.46 – 0.014 0.018
C – 0.19 0.25 – 0.007 0.010
D – 9.80 10.00 – 0.386 0.394
E – 3.80 4.00 – 0.150 0.158
e 1.27 – – 0.050 – –
H – 5.80 6.20 – 0.228 0.244
L – 0.40 1.27 – 0.016 0.050
a – 0° 8° – 0° 8°
N 16 16
CP – – 0.10 – – 0.004
25/31
M41T94
Figure 21. SOH28 – 28-lead Plastic Small Outline, Battery SNAPHAT, Package Outline
A2 A
C
B e eB
CP
D
N
E H
A1 α L
1
SOH-A
Table 17. SOH28 – 28-lead Plastic Small Outline, battery SNAPHAT, Package Mechanical Data
millimeters inches
Symbol
Typ Min Max Typ Min Max
A – – 3.05 – – 0.120
A1 – 0.05 0.36 – 0.002 0.014
A2 – 2.34 2.69 – 0.092 0.106
B – 0.36 0.51 – 0.014 0.020
C – 0.15 0.32 – 0.006 0.012
D – 17.71 18.49 – 0.697 0.728
E – 8.23 8.89 – 0.324 0.350
e 1.27 – – 0.050 – –
eB – 3.20 3.61 – 0.126 0.142
H – 11.51 12.70 – 0.453 0.500
L – 0.41 1.27 – 0.016 0.050
α – 0° 8° – 0° 8°
N 28 28
CP – – 0.10 – – 0.004
26/31
M41T94
Figure 22. SH – 4-pin SNAPHAT Housing for 48mAh Battery & Crystal, Package Outline
A1 A2
A A3
eA B L
eB
D
SHTK-A
Table 18. SH – 4-pin SNAPHAT Housing for 48mAh Battery & Crystal, Package Mechanical Data
millimeters inches
Symbol
Typ Min Max Typ Min Max
A – – 9.78 – – 0.385
A1 – 6.73 7.24 – 0.265 0.285
A2 – 6.48 6.99 – 0.255 0.275
A3 – – 0.38 – – 0.015
B – 0.46 0.56 – 0.018 0.022
D – 21.21 21.84 – 0.835 0.8560
E – 14.22 14.99 – 0.556 0.590
eA – 15.55 15.95 – 0.612 0.628
eB – 3.20 3.61 – 0.126 0.142
L – 2.03 2.29 – 0.080 0.090
27/31
M41T94
Figure 23. SH – 4-pin SNAPHAT Housing for 120mAh Battery & Crystal, Package Outline
A1 A2
A A3
eA B L
eB
D
SHTK-A
Table 19. SH – 4-pin SNAPHAT Housing for 120mAh Battery & Crystal, Package Mechanical Data
millimeters inches
Symbol
Typ Min Max Typ Min Max
A – – 10.54 – – 0.415
A1 – 8.00 8.51 – 0.315 0.335
A2 – 7.24 8.00 – 0.285 0.315
A3 – – 0.38 – – 0.015
B – 0.46 0.56 – 0.018 0.022
D – 21.21 21.84 – 0.835 0.860
E – 17.27 18.03 – 0.680 0.710
eA – 15.55 15.95 – 0.612 0.628
eB – 3.20 3.61 – 0.126 0.142
L – 2.03 2.29 – 0.080 0.090
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M41T94
PART NUMBERING
Device Type
M41T
Package
MQ = SO16
MH (1) = SOH28
Temperature Range
6 = –40 to 85°C
Note: 1. The 28-pin SOIC package (SOH28) requires the battery/crystal package (SNAPHAT®) which is ordered separately under the part
number “M4TXX-BR12SHX” in plastic tube or “M4TXX-BR12SHXTR” in Tape & Reel form.
Caution: Do NOT place the SNAPHAT battery package “M4TXX-BR12SH” in conductive foam as it will drain the lithium button-cell
battery.
For a list of available options (e.g., Speed, Package) or for further information on any aspect of this device,
please contact the ST Sales Office nearest to you.
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M41T94
REVISION HISTORY
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M41T94
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
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