IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 24, NO.

7, JULY 2009 1737

Control and Experiment of Pulsewidth-Modulated

Modular Multilevel Converters
Makoto Hagiwara, Member, IEEE, and Hirofumi Akagi, Fellow, IEEE

Abstract—A modular multilevel converter (MMC) is one of

the next-generation multilevel converters intended for high- or
medium-voltage power conversion without transformers. The
MMC is based on cascade connection of multiple bidirectional
chopper-cells per leg, thus requiring voltage-balancing control of
the multiple floating dc capacitors. However, no paper has made
an explicit discussion on voltage-balancing control with theoretical
and experimental verifications. This paper deals with two types
of pulsewidth-modulated modular multilevel converters (PWM-
MMCs) with focus on their circuit configurations and voltage-
balancing control. Combination of averaging and balancing con-
trols enables the PWM-MMCs to achieve voltage balancing without
any external circuit. The viability of the PWM-MMCs, as well as
the effectiveness of the voltage-balancing control, is confirmed by
simulation and experiment.
Index Terms—Medium-voltage power conversion, multilevel
converters, voltage-balancing control.

I. INTRODUCTION
IGH-POWER converters for utility applications require
H line-frequency transformers for the purpose of enhanc-
ing their voltage or current rating [1]–[4]. The 80-MVA Static
synchronous Compensator (STATCOM) commissioned in 2004
consists of 18 neutral-point-clamped (NPC) converter legs [4],
where each of the ac sides is connected in series by the corre-
sponding transformer. The use of line-frequency transformers,
however, not only makes the converter heavy and bulky, but
also induces the so-called dc magnetic flux deviation when a
single-line-to-ground fault occurs [5].
Recently, many scientists and engineers of power systems
and power electronics have been involved in multilevel convert-
ers intended for achieving medium-voltage power conversion
without transformers [6]–[8]. Two of the representatives are:
1) the diode-clamped multilevel converter (DCMC) [6], [7];
2) the flying-capacitor multilevel converter (FCMC) [8].
The three-level DCMC, or a NPC converter [9] has been put
into practical use [10]. If a voltage-level number is more than
three in the DCMC, inherent voltage imbalance occurs in the
series-connected dc capacitors, thus resulting in requiring an
external balancing circuit (such as a buck–boost chopper) for a
pair of dc capacitors [11]. Furthermore, a significant increase
in the clamping diodes required renders assembling and build-
ing of each leg more complex and difficult. Thus, a reasonable
voltage-level number would be up to five from a practical point
Manuscript received July 16, 2008; revised October 16, 2008. Current version
published July 22, 2009. Recommended for publication by Associate Editor
S. Bhattacharya.
The authors are with the Department of Electrical and Electronic Engineering,
Tokyo Institute of Technology, 152-8552 Tokyo, Japan (e-mail: mhagi@akg.
ee.titech.ac.jp; akagi@ee.titech.ac.jp).
Digital Object Identifier 10.1109/TPEL.2009.2014236
0885-8993/$26.00 © 2009 IEEE
Fig. 1. Circuit configuration of a chopper-cell-type modular multilevel in-
verter: (a) Power circuit, and (b) Bidirectional PWM chopper-cell with a floating
dc capacitor.
of view. As for the FCMC, the four-level pulsewidth modulation
(PWM) inverter is currently produced by one manufacture of in-
dustrial medium-voltage drives [12]. However, the high expense
of flying capacitors at low carrier frequencies (say, lower than
1 kHz) is the major disadvantage of the FCMC [13].
A modular multilevel converter (MMC) has been proposed
in [14]–[20], intended for high-power applications. Fig. 1 shows
a basic circuit configuration of a three-phase modular multilevel
inverter. Each leg consists of two stacks of multiple bidirectional
cascaded chopper-cells and two noncoupled buffer inductors.
The MMC is suitable for high- or medium-voltage power con-
version due to easy construction/assembling and flexibility in
converter design. Siemens has a plan of putting it into practical
use with the trade name of “high-voltage direct current (HVDC)-
plus.” It is reported in [19] that a system configuration of the
HVDC-plus has a power rating of 400 MVA, a dc-link voltage
of ±200 kV, and 200 cascaded chopper cells per leg. The au-
thors of [14]–[20], however, have made no detailed description
of staircase modulation, especially about a crucial issue of how
to achieve voltage balancing of 200 floating dc capacitors per
leg. Moreover, no experimental result has been reported yet.
1738
Fig. 2. Classification of modular multilevel converters.
This paper focuses on voltage-balancing control and oper-
ating performance of a pulsewidth-modulated MMC (PWM-
MMC) equipped with either two noncoupled buffer inductors
or a single coupled buffer inductor per leg. The final aim of this
paper is to apply the PWM-MMC to medium-voltage power
converters in a power rating of 1–10 MVA, a dc-link voltage of
10–30 kV, and a switching frequency of 200–2000 Hz. Combin-
ing averaging control with balancing control enables achieve-
ment of voltage balancing of multiple floating dc capacitors
without any external circuit. In addition, this paper proposes
the dual MMC for low-voltage large-current power conversion.
Each dc side of positive and negative chopper-cells possesses a
common dc capacitor, whereas its ac side is connected in par-
allel via multiple buffer inductors. The similarity between the
two MMCs exists in terms of circuit configuration and control
method. The validity of the two MMCs is confirmed not only
by simulated results, but also by experimental results.
II. TOPOLOGIES OF MMCS
A. Classification From the Topologies
Fig. 2 shows a classification of MMCs based on single-phase
half-bridge or full-bridge converter-cells. From their topologies,
MMCs can be classified into:
1) double-star-configured MMCs;
2) a star-configured MMC [Fig. 3(a)];
3) a delta-configured MMC [Fig. 3(b)]; and
4) the dual MMC (Fig. 14).
Moreover, the double-star-configured MMCs can be classi-
fied into:
1) a chopper-cell-type MMC (Fig. 1); and
2) a bridge-cell-type MMC.
B. Comparisons in Function and Application
The double-star-configured MMC topology possesses the
common dc-link terminals as shown in Fig. 1(a), which en-
able dc-to-ac and ac-to-dc power conversion. However, the
star/delta-configured MMC topology has no common dc-link
terminals as shown in Fig. 3. As a result, it has no capability
of achieving dc-to-ac and ac-to-dc power conversion although
it can control active power back and forth between the three-
phase ac terminals and the floating dc capacitors. This means
IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 24, NO. 7, JULY 2009
Fig. 3. Circuit configuration of MMCs: (a) Star-configured MMC, and
(b) Delta-configured MMC.
that the star/delta-configured MMC topology is not applicable
to industrial motor drives, but it is suitable for STATCOMs and
energy storage systems [21]–[23]. This consideration is one of
the most significant differences in function and application be-
tween the double-star-configured MMC topology in Fig. 1 and
the star/delta-configured MMC topology in Fig. 3.
The bridge-cell-type MMC replaces the chopper cell in
Fig. 1(b) with single-phase full-bridge converter cells. Hence,
the dc-voltage source E can be replaced with a single-phase
ac-voltage source [16]. The detail of the dual MMC is discussed
in Section V. In this paper, the chopper-cell-type MMC is
referred to simply as “the MMC” because attention is paid to
it exclusively.
C. Definition of DC Loop Currents
Fig. 1 shows a three-phase inverter based on the MMC.
Each leg of the circuit consists of two stacks of four bidirec-
tional chopper-cells and two noncoupled buffer inductors. Each
chopper-cell consists of a floating dc capacitor and two
insulated-gate bipolar transistors that form a bidirectional chop-
per. Attention is paid to the u-phase chopper-cells because the
operating principle is identical among the three legs.
The following circuit equation exists in Fig. 1(a)1 :


8
d
E= vj u + l (iP u + iN u ). (1)
j =1
dt
Here, E is a supply dc voltage, vj u is an output voltage of the u-
phase chopper-cell numbered j, l is a buffer inductance, and iP u
and iN u are positive- and negative-arm currents, respectively.
The Kirchhoff’s voltage law (KVL) loop given by (1) is referred
to as the “dc loop,” which is independent of the load. The circu-
lating current along the u-phase dc loop, iZ u can be defined as
iu iu
iZ u = iP u − = iN u +
2 2
1
= (iP u + iN u ). (2)
2
1 The subscript symbol j means numbering of each chopper cell.
HAGIWARA AND AKAGI: CONTROL AND EXPERIMENT OF PULSEWIDTH-MODULATED MODULAR MULTILEVEL CONVERTERS 1739

Fig. 5. Voltage command of each arm: (a) Positive arm, and (b) Negative arm.

of vB∗ j u should be changed according to that of iP u or iN u .

Fig. 4. Block diagram of dc-capacitor voltage control: (a) Averaging control, When vC∗ ≥ vC j u (j : 1 − 4) in the positive arm of Fig. 1(a), a
and (b) Balancing control. positive active power should be taken from the dc power supply
into the four chopper-cells. When iP u is positive, the product of
Note that iP u , iN u , iu , and id are branch currents whereas iZ u vB j u (= vB∗ j u ) and iP u forms the positive active power. When
is a loop current that is impossible to measure directly. iP u is negative, the polarity of vB j u should get inverse to take the
positive active power. Finally, vB∗ j u for j = 1 − 4 is represented
III. CONTROL METHOD OF THE MMC as

The voltage-balancing control of eight floating dc capacitors ∗
K5 (vC∗ − vC j u ) (iP u > 0)
vB j u = ∗
(6)
per leg in Fig. 1 can be divided into: −K5 (vC − vC j u ) (iP u < 0)
1) averaging control; and
while vB∗ j u for j = 5 − 8 is represented as
2) balancing control.

∗
K5 (vC∗ − vC j u ) (iN u > 0)
A. Averaging Control vB j u = ∗
(7)
−K5 (vC − vC j u ) (iN u < 0).
Fig. 4(a) shows a block diagram of the averaging control. It
Fig. 5 shows a voltage command of each chopper-cell vj∗u .
forces the u-phase average voltage v̄C u to follow its command
The positive-arm and negative-arm commands are obtained as:
vC∗ , where v̄C u is given by
vu∗ E
1

8 vj∗u = vA∗ u + vB∗ j u − + (j : 1 − 4) (8)
v̄C u = vC j u . (3) 4 8
8 j =1 v∗ E
vj∗u = vA∗ u + vB∗ j u + u + (j : 5 − 8) (9)
Let a dc-loop current command of iZ u be i∗Z u , as shown in 4 8
Fig. 4(a). It is given by where vu∗ is an ac-voltage command for the u-phase load. Note
 that Fig. 5 includes the feedforward control of the dc supply
i∗Z u = K1 (vC∗ − v̄C u ) + K2 (vC∗ − v̄C u ) dt. (4) voltage E. The voltage command vj∗u is normalized by each
dc-capacitor voltage vC j u , followed by comparison with a tri-
The voltage command obtained from the averaging control, vA∗ u angular waveform having a maximal value of unity and a min-
is given by imal value of zero with a carrier frequency of fC . The actual
 switching frequency of each chopper-cell, fS is equal to fC . The
vA u = K3 (iZ u − iZ u ) + K4 (iZ u − i∗Z u ) dt.
∗ ∗
(5) eight chopper-cells have the eight triangular waveforms with the
same frequency but a phase difference of 45◦ (= 360◦ /8) to each
When vC∗ ≥ v̄C u , i∗Z u increases. The function of the current other for achieving harmonic cancellation and enhancing cur-
minor loop in Fig. 4(a) forces the actual dc-loop current iZ u rent controllability. As a result, the line-to-neutral voltage is a
to follow its command i∗Z u . As a result, this feedback control nine-level voltage waveform, and a line-to-line voltage is a 17-
of iZ u enables v̄C u to follow its command vC∗ without being level voltage waveform with an equivalent switching frequency
affected by the load current iu . of 8fC .
C. Simulated Results
B. Balancing Control Fig. 6 shows simulated waveforms from Fig. 1. Tables I and II
The use of the balancing control described in [21] forces the summarize circuit parameters and control gains used for simu-
individual dc voltage to follow its command vC∗ . Fig. 4(b) shows lation using a software package of the “PSCAD/EMTDC” [24].
a block diagram of the u-phase balancing control, where vB∗ j u is The dc supply voltage E and the rated active power P are set
the voltage command obtained from the balancing control. Since as E = 9 kV and P = 1 MW, and therefore, the nominal rated
the balancing control is based on either iP u or iN u , the polarity line-to-line rms voltage of the MMC is 5.5 kV. An intrinsic
1740 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 24, NO. 7, JULY 2009

TABLE II
CONTROL GAINS USED FOR SIMULATION

one-sampling delay occurs due to digital control. The dc-

capacitor voltage command of each chopper-cell is vC∗ =
2.25 kV (= 9 kV/4), while three-phase load voltage commands
of each phase are given as
vu∗ = 0.5E sin 2πf t
 
2
vv∗ = 0.5E sin 2πf t − π
3
 
4
vw∗ = 0.5E sin 2πf t − π
3
E = 9 kV
f = 50 Hz. (10)
Note that vu∗ , vv∗ , and vw∗ are the three-phase line-to-neutral volt-
ages. In Fig. 6, each chopper cell is operated at unity modulation
index.
In Table I, a unit capacitance constant H is defined as
3 × 8 × 12 CVC2
H=
P
12 × 1.9 × 10−3 × 2.252 × 106
= = 0.115 (11)
106
where VC is the rated dc voltage of each chopper cell. Note that
H is defined as a ratio of all electrostatic energy stored in dc
capacitors with respect to rated active power [25]. Therefore, H
has a unit of second.2
Fig. 6 indicates that vu v is a 17-level line-to-line voltage,
∗ =
Fig. 6. Simulated waveforms obtained from Fig. 1, where f = 50 Hz, v C
achieving voltage balancing of all the dc capacitors. The dc
2.25 kV, and E = 9 kV. input power pd is represented as
pd = E × id (12)
where id is a dc input current. The waveform of pd includes the
following two frequency components: one is a 6th-frequency
(300 Hz) component stemming from a three-phase full-bridge
TABLE I
CIRCUIT PARAMETERS USED FOR SIMULATION converter, and the other is a fundamental frequency (50 Hz)
component stemming from an output frequency of 50 Hz. The
detailed analysis of each waveform will be carried out in the
next section.

IV. EXPERIMENTAL RESULTS

A. System Configuration Used for Experiment
Fig. 7(a) shows a half-bridge circuit based on the MMC,
where the stack number of chopper cells was selected as four per
leg to confirm the basic operating principle, although the stack

2 H can be defined in the traditional two-level converters as well. An opti-

mization of H is left for the future work.
HAGIWARA AND AKAGI: CONTROL AND EXPERIMENT OF PULSEWIDTH-MODULATED MODULAR MULTILEVEL CONVERTERS
Fig. 7. Experimental circuit: (a) Half-bridge circuit, and (b) System
configuration.
Fig. 8. Digital control system used for experiment.
number of chopper cells was eight in Fig. 1. Fig. 7(b) shows
a system configuration used for experiment. The midpoint of
the two dc input series-connected capacitors is connected back
to the neutral point of the star winding of the transformer, thus
making the midpoint voltage stable. The dc supply voltage E is
regulated at 140 V, and the capacitance value of Cd is chosen as
20 mF.
Fig. 8 shows the digital control system used for experiment.
The system detects each dc-capacitor voltage vC j , both positive-
and negative-arm currents iP and iN , and a dc supply voltage
E as input signals to the A/D unit. The A/D unit consisting of
seven A/D converters takes in the analog signals, and then it
converts them into seven 12-bits digital signals. A digital signal
processor (DSP) unit using a 16-bit DSP (ADSP-2105) takes
in the digital signals, and produces the voltage commands vj∗
after completing the digital processing shown in Figs. 4 and 5.
A field-programmable gate array (FPGA) unit has the following
multifunctions:
1741
TABLE III
CIRCUIT PARAMETERS USED FOR EXPERIMENT
TABLE IV
CONTROL GAINS USED FOR EXPERIMENT
1) generating carrier signals with appropriate phase differ-
ences;
2) comparing vj∗ with the corresponding triangular carrier
signal; and
3) producing gate signals with a dead time of 2 µs.
The FPGA unit produces 8-bit (= 2 × 4) gate signals in to-
tal, because each chopper cell possesses two semiconductor
switches. Furthermore, the FPGA unit sends back sampling sig-
nals to the DSP unit for realizing the so-called “synchronous
sampling.”
Attention is paid to a one-sampling delay occurring in the DSP
unit. The experiment selected the carrier frequency as fC =
8 kHz, while each triangular carrier had a phase difference
of 90◦ (= 360◦ /4). If a conventional synchronous sampling
was adopted, the DSP unit would yield a time delay of 63 µs
[=1/(2 fC )] because its sampling and command renewal would
be conducted at the peak value of each carrier waveform. The
sampling delay can be reduced with the following sampling
method for improving controllability of output voltages: As for
chopper-cell 1, for instance, the sampling is conducted at the
peak value of carrier signal 4, and then vj∗ is changed at the peak
value of carrier signal 1. As a consequence, the time delay is
minimized to be 31 µs [= 1 / (4 fC )]. A three-phase MMC can
reduce the time delay further by phase-shifting of each leg by
120◦ .
B. Operating Performance Under a Steady-State Condition
Tables III and IV summarize the circuit parameters and con-
trol gains used for experiment.3 An R-L load with a power
factor of 0.9 at 50 Hz was utilized. The experiment was carried
out under the condition P = 250 W.
3 The experimental conditions are the same in H and l (per unit) as those in
Fig. 6.
1742 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 24, NO. 7, JULY 2009

Hence, harmonic voltages included in the left hand in (16) ap-

pear across both L and l/2. If l/2 is dominant over L (L  l/2),
most of the harmonic voltages appear across l/2, bringing less
harmonic voltages to v0 . If L is dominant over l/2 (L  l/2),
most of the harmonic voltages appear across L to the contrary.
Although the load current i0 is sinusoidal with a fundamental
component of 50 Hz, the arm currents iP and iN contain non-
negligible low-order harmonic currents. This interesting phe-
nomenon occurs due to the effect of the balancing control. Fig. 9
indicates that the voltage command from the balancing control,
vB∗ 1 is a discontinuous sawtooth waveform as expected from
(6) and (7). As a result, vB∗ 1 brings a discontinuous circulating
current to the dc loop, producing low-order harmonic currents
in iP and iN . It is obvious that the fluctuations in iP and iN
are accompanied by those in vB∗ 1 . The switching ripple currents
contained in iP and iN are determined by the inductance value
of the buffer inductors and the harmonic voltages resulting from
the four chopper-cells. Note that switching-frequency compo-
nents of 16 kHz are dominant in iP and iN . In other words,
the ripple currents can be reduced by increasing the carrier fre-
quency and the buffer inductance value. Carefully looking into
vB∗ 1 and iP in Fig. 9 reveals that a subtle difference exists at
the times of polarity change between the waveforms of vB∗ 1 and
iP . The reason is that the 16-kHz switching ripple component
contained in iP is not taken into the control circuit precisely,
because the sampling frequency of DSP is set as 16 kHz. This
phenomenon produces no effect on the balancing control be-
cause the harmonic current makes no contribution to forming
any active power.
Fig. 9. Experimental waveforms obtained from Fig. 7, where f = 50 Hz, Applying the averaging control forces the average voltage
∗ = 70 V, and E = 140 V.
vC v̄C to follow its command vC∗ (= 70 V). The calculation of (3)
has a function of reducing ac components in v̄C . From Fig. 9,
Fig. 9 shows the experimental waveforms when the dc-voltage vC 1 and vC 3 contain 50-Hz components caused by i0 . This ac
command of each chopper-cell was set as vC∗ = 70 V. The ac component is inverse proportional to the fundamental frequency
voltage command for the load was given by of i0 . This is similar to flying capacitors in the FCMC.
√ The dc voltage of each chopper-cell is kept balanced by the
v0∗ = 2V0 sin 2πf t balancing control. Making reference to (8) simplifies the voltage
commands of chopper-cells 1 and 2, v1∗ and v2∗ , as follows:
V0 = 50 V
v0∗ E
f = 50 Hz. (13) v1∗ = v2∗  − + (17)
2 4

Fig. 7(a) yields the following equation: where a reasonable approximation of vB∗ 1 = vB∗ 2 = vA∗  0 was
 4  made. Equation (17) implies that chopper-cells 1 and 2 were
1

2
l d operated under the same modulation index. As a result, vC 1 was
v0 = vj − vj − i0 (14)
2 j =3 2 dt equal to vC 2 in Fig. 9 because the chopper-cells 1 and 2 utilize a
common arm current iP , and (17) leads to a relation of v1∗ = v2∗ .
j =1
 
d In a similar way, vC 3 was equal to vC 4 in Fig. 9. Experimental
v0 = R + L i0 . (15)
dt waveforms of iZ and i∗Z show that no steady-state error, even in
a small control gain, existed between iZ and i∗Z in terms of their
The waveform of v0 is slightly different from that in a DCMC
dc components because of an extremely low resistance along
and an FCMC, due to the existence of the second term of the right
the dc loop.
hand in (14). Note that both DCMC and FCMC have a complete
staircase waveform with a constant (not curved) voltage level.
Substituting (14) into (15) yields C. Operating Performance Under a Transient-State Condition
 4    Fig. 10 shows experimental waveforms of the MMC when the
1

2
l d
vj − vj = Ri0 + L + i0 . (16) voltage command was reduced to half, but the circuit parameters
2 j =3 j =1
2 dt and the control gains were not changed. The transient voltage
HAGIWARA AND AKAGI: CONTROL AND EXPERIMENT OF PULSEWIDTH-MODULATED MODULAR MULTILEVEL CONVERTERS
Fig. 10. Experimental waveforms when the voltage command was changed
from 50 to 25 V.
Fig. 11. Experimental waveforms when only the balancing control was
disabled.
Fig. 12. Coupled inductor used for experiment.
fluctuations in vC 1 and vC 3 were suppressed to less than 5%
with respect to its rated voltage of 70 V.
Fig. 11 shows experimental waveforms before and after the
balancing control was disabled intentionally but the averaging
control was enabled. The voltage imbalance was gradually ex-
panding with the passage of time. Hence, the balancing control
is indispensable for stable operation.
D. Operating Performance Using a Coupled Buffer Inductor
The two noncoupled buffer inductors in Fig. 7 can be replaced
with a single coupled buffer inductor intended for a size reduc-
tion in the magnetic components. Fig. 12 shows specifications
of the inductor used for experiment. The terminals “a” and “b”
are connected to the positive- and negative-arms, respectively,
1743
Fig. 13. Experimental waveforms when a coupled buffer inductor was used.
while the terminal “c,” or the midpoint is directly connected
to the load. The relation of lab = 4lac = 4lbc exists in Fig. 12.
It should be noted that the inductor presents no inductance to
i0 because the magnetic fluxes produced by the fundamental
frequency components in iP and iN cancel out each other. As
a consequence, the inductor presents the inductance of lab only
to the circulating current iZ . The use of the coupled inductor
results in bringing considerable reductions in size, weight, and
cost to the magnetic core.4
Fig. 13 shows experimental waveforms when the coupled
inductor was utilized. In Fig. 13, each chopper cell was oper-
ated at a modulation index of 0.83, while the balancing control
using the load current was utilized (see the Appendix.). Since
the inductor produces no effect on i0 , (14) can be rewritten as
follows:
 4 
1


2
v0 = vj − vj . (18)
2 j =3
j =1
Hence, v0 is a staircase waveform with a constant voltage level
as shown in Fig. 13. In other words, the MMC operates as a
multilevel voltage source that is independent of i0 . Comparison
between Figs. 9 and 13 reveals that both have similar waveforms
except for v0 .
4 An optimization of the inductor is left for the future work.
1744 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 24, NO. 7, JULY 2009

Fig. 14. Half-bridge circuit using the dual MMC.

V. DUAL MMC
Fig. 14 shows a half-bridge circuit of the other MMC with
a dual relation to Fig. 7. Each dc side of positive and negative
chopper-cells possesses a common dc capacitor, whereas its ac
side is connected in parallel via two buffer inductors.5

A. Control Method
The control method of the dual MMC is basically the same
as that of Fig. 1 except for the following: although Fig. 1 has
a common dc loop to cascaded chopper-cells per leg, the dual
MMC has multiple dc loops because the multiple chopper-cells
forming an arm are connected in parallel. This means that the Fig. 15. Experimental waveforms obtained from Fig. 14, where f = 50 Hz,
∗ = 70 V, and E = 70 V.
vC
multiple current minor loops should be provided for the aver-
aging control. Chopper-cell 1 in Fig. 14, for instance, should
control a circulating current iZ 1 included in iP 1 . Here, iZ 1 is inductance in the dual MMC is smaller than that in Fig. 7 due to
obtained as parallel connection of the two buffer inductors. Fig. 15 shows
i0 that iP 1 and iN 1 are halves of iP and iN, respectively. Therefore,
iZ 1 = iP 1 − . (19)
4 the dual MMC is suitable for low-voltage large-current power
conversion.

B. Operating Performance Under a Steady-State Condition VI. CONCLUSION

Fig. 15 shows experimental waveforms obtained from Fig. 14.
Here, the dc supply voltage was E = 70 V, and the dc voltage
command of each chopper cell was vC∗ = 70 V. The ac voltage
command of the load was given by
√ PWM-MMC. Experiments using a laboratory system have ver-
v0∗ = 2V0 sin 2πf t
V0 = 25 V
f = 50 Hz.
The circuit parameters and control gains were the same as those
in Fig. 9. It should be noted that the experiment was carried out
using four noncoupled buffer inductors.
Figs. 9 and 15 show that both MMCs have similar waveforms.
However, comparison reveals that the two waveforms of v0
are different in harmonic voltage. The reason is that the buffer
5 The dc capacitor of each chopper cell can be floated as in Fig. 7.
This paper has dealt with two types of PWM-MMCs, propos-
ing their control method and verifying their operating principle.
Computer simulation using the “PSCAD/EMTDC” software
package has confirmed the proper operation of the three-phase
ified the viability and effectiveness of the single-phase PWM-
MMC. The MMC is showing considerable promise as a power
(20) converter for medium-voltage motor-drives, high-voltage di-
rect current (HVDC) systems, STATCOMs, and back-to-back
systems.
APPENDIX
A. Another Averaging Control Method
This section describes another averaging control method dif-
ferent from Fig. 4(a), which is characterized by controlling in-
dependent average voltages of positive and negative chopper
HAGIWARA AND AKAGI: CONTROL AND EXPERIMENT OF PULSEWIDTH-MODULATED MODULAR MULTILEVEL CONVERTERS
cells v̄C u p and v̄C u n , which are given as follows:
1

4
v̄C u p = vC j u
4 j =1
1

8 [1] S. Mori, K. Matsuno, T. Hasegawa, S. Ohnishi, M. Takeda, M. Seto,
v̄C u n = vC j u .
4 j =5
The current command of the positive chopper-cells, i∗Z u p is
represented as
 [3] T. Uzuka, S. Ikedo, and K. Ueda, “A static voltage fluctuation compensator
iZ u p = K1 (vC − v̄C u p ) + K2 (vC∗ − v̄C u p ) dt
∗ ∗
(23)
while that of the negative chopper-cells, i∗Z u n is represented as
 [5] M. Hagiwara, P. V. Pham, and H. Akagi, “Calculation of dc magnetic
i∗Z u n = K1 (vC∗ − v̄C u n ) + K2 (vC∗ − v̄C u n ) dt. (24)
Here, the voltage command of the positive chopper-cells vA∗ u p
is given by
 2001.
vA∗ u p = K3 (iZ u − i∗Z u p ) + K4 (iZ u − i∗Z u p ) dt (25)
while that of the negative chopper-cells, vA∗ u n is given by
 [9] A. Nabae, I. Takahashi, and H. Akagi, “A new neutral-point-clamped
vA u n = K3 (iZ u − iZ u n ) + K4 (iZ u − i∗Z u n ) dt. (26)
∗ ∗
B. Other Balancing Control Methods
The balancing control forms an active power between the
output voltage of each chopper-cell vB j u and the correspond-
ing arm current. The following describes two other balancing
control methods different from Fig. 4(b).
1) The method using the arm currents iP u and iN u : For the
positive chopper-cells numbered 1 to 4, vB∗ j u is given by
vB∗ j u = K5 (vC∗ − vC j u )iP u .
For the negative chopper-cells numbered 5–8, vB∗ j u is given by
vB∗ j u = K5 (vC∗ − vC j u )iN u .
Equations (27) and (28) indicate that vB j u (= vB∗ j u ) contains the
same frequency components as iP u or iN u , if the ac components
included in vC j u can be eliminated. Hence, vB j u contains dc
and 50-Hz components. The dc component of vB j u forms an
active power with that of iP u or iN u , and the 50-Hz component
of vB j u with that of iP u or iN u . To avoid an undesirable effect
on the control system, ac components included in vC j u should
be eliminated fully by a low-pass filter.
2) The method using the load current iu : For the positive
chopper cells numbered 1–4, vB∗ j u is given by
vB∗ j u = K5 (vC∗ − vC j u )iu .
For the negative chopper cells numbered 5–8, vB∗ j u is given by
vB∗ j u = −K5 (vC∗ − vC j u )iu .
Equations (29) and (30) indicate that vB j u (= vB∗ j u ) contains
the same frequency components as iu or −iu . Note that iu is in
phase with iP u , whereas −iu is in phase with iN u . The 50-Hz
1745
component included in vB j u forms an active power with that of
iP u or iN u .
(21)
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Makoto Hagiwara (M’06) was born in Tokyo, Japan,
in 1979. He received the B.S., M.S., and Ph.D. de-
grees in electrical engineering from the Tokyo Insti-
tute of Technology, Tokyo, Japan, in 2001, 2003, and
2006, respectively.
Since April 2006, he has been an Assistant Pro-
fessor in the Department of Electrical and Electronic
Engineering, Tokyo Institute of Technology. His cur-
rent research interests include self-commutated con-
verters for utility applications.
IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 24, NO. 7, JULY 2009
Hirofumi Akagi (M’87–SM’94–F’96) was born in
Okayama, Japan, in 1951. He received the B.S.
degree from the Nagoya Institute of Technology,
Nagoya, Japan, in 1974, and the M.S. and Ph.D. de-
grees from the Tokyo Institute of Technology, Tokyo,
Japan, in 1976 and 1979, respectively, all in electrical
engineering.
In 1979, he was with the Nagaoka University of
Technology, Nagaoka, Japan, as an Assistant and then
Associate Professor in the Department of Electrical
Engineering. In 1987, he was a Visiting Scientist at
the Massachusetts Institute of Technology, Cambridge, for ten months. From
1991 to 1999, he was a Professor in the Department of Electrical Engineer-
ing, Okayama University, Okayama, Japan. From March to August of 1996, he
was a Visiting Professor at the University of Wisconsin, Madison, and then the
Massachusetts Institute of Technology. Since January 2000, he has been a Pro-
fessor in the Department of Electrical and Electronic Engineering at the Tokyo
Institute of Technology, Tokyo, Japan. He has made presentations many times
as a keynote or invited speaker internationally. He has authored or coauthored
more than 80 IEEE Transactions papers, and two invited papers in Proceedings
of the IEEE. According to Google Scholar, the total citation index for all his
papers is more than 7000. His current research interests include power conver-
sion systems, ac motor drives, active and passive EMI filters, high-frequency
resonant inverters for induction heating and corona discharge treatment pro-
cesses, and utility applications of power electronics such as active filters for
power conditioning, self-commutated back-to-back (BTB) systems, and flexi-
ble ac transmission system (FACTS) devices.
Prof. Akagi served as the President of the IEEE Power Electronics Society
(PELS) for 2007–2008. He was elected as a Distinguished Lecturer of the IEEE
Industry Applications Society (IAS) and PELS for 1998-1999. He received two
IEEE IAS Transactions Prize Paper Awards in 1991 and 2004, and two IEEE
PELS Transactions Prize Paper Awards in 1999 and in 2003, nine IEEE IAS
Committee Prize Paper Awards, the 2001 IEEE William E. Newell Power Elec-
tronics Award, the 2004 IEEE IAS Outstanding Achievement Award, and the
2008 IEEE Richard H. Kaufmann Technical Field Award.