2010 International Conference on Electronic Devices, Systems and Applications (ICEDSA2010)

Mitigating Arcing Defect at Pad Etch

Khairuddin Azizi Mohammad IEEE, Siaw Yong Chuang, Lee Dae Gun and Shannon Lee
X-FAB Sarawak Sdn. Bhd., 1 Silicon Drive, 93350, Kuching, Sarawak, Malaysia
Tel:+608235488 Fax: +6082361177 khairuddin.mohammad@xfab.com

Abstract — This paper is to present method to mitigate

arcing defect encountered at pad etch. The problem was
detected during wafer disposition due to equipment alarm.
Based on observation, this burnt- like defect material, is
observed to have inhibited the wafer surface and exposing
the top metal line. The inclination was observed mainly
during main etch step. The wafer is believed to have
encountered plasma instability during transition from Main
Etch (ME) to Over Etch (OE) step. However, this is only
detected during backside helium leak alarm. This arcing
defect was caused by several factors, of which were related
to recipe, wafer condition, processing tool and product
design. The approach taken was to mitigate these issues a) Spot mode captured b) Round type ball
where recipe optimization and tighter equipment parameter during inline defect defect from the spot
control were implemented. The design of experiment was inspection area at wafer edge
presented to find the optimal setting for backside helium Fig. 2. Arcing defect - spot mode
flow and chucking voltage. Apart from that, chamber mix
run also plays an important role.
common types of arcing defects. The first is the snake
Keywords—arcing, pad, defect, case study, etch mode as shown in Fig. 1. The latter is the spot defect as
shown in Fig. 2.
I. INTRODUCTION
Process plasma induced damage was reported as early This snake mode arcing would normally extend
as 1984 by Watanabe et. al. [1]. The paper reported the through the scribe line, guard ring or Electro Static
earliest gate oxide breakdown which was due to batch Discharge (ESD) structure. The impacts are, the affected
processing tool. Fonash et. al. [2] highlighted that wafers will be scrapped while the processing tool will be
plasma-based processing can produce damage due to down for investigation. The defect is normally observed
these conditions at either passivation etch and interconnect etch.
1) Impurity contamination from residual reaction
products; The spot mode is normally observed after interconnect
2) Impurity contamination of semiconductors and etch which comprises of more than three metal layers.
dielectrics from plasma species permeation; The disposition for affected wafers would be to continue
3) Bonding disruption in semiconductors and dielectrics flow after water jet scrubbing and the chamber will be
due to photon and particle bombardment; down for investigation. This would normally involved
4) Current damage due to charging and induced particle check and performing bare wafer seasoning to
electromotive force (EMF) currents ensure there is no damage on the wafer.

These can be mitigated by subsequent processes and also
through device and circuit design. There are two
This paper shall covers the defect encountered at pad
etch which is shown in Fig. 3. The problem was detected
during wafer disposition due to backside helium leak
alarm. A burnt like material was observed to have
inhibited the wafer and exposing the top metal. The
wafer is believed to encounter plasma instability during
transition from Main Etch (ME) step to Over Etch (OE)
step. However, this is only detected during backside
helium leak alarm.

Factors contributing to this arcing defect are shown

below. These factors are believed to be the driving forces
a) Snake mode captured b) Arcing propagated for higher etch rate and faster throughput.
at outgoing quality from wafer edge
inspection step exclusion (WEE)
area
Fig. 1. Arcing defect - snake mode

978-1-4244-6632-0/10/$26.00 ©2010 IEEE 344

 a) 20 X magnification b) 100 X magnification
Fig. 3 Arcing defect observed at pad etch step.
1) Radio frequency (RF) power.
2) Magnetic field
3) Process time
4) Pressure
High RF power recipe, when combined with high
power magnetic field inside a pressurized chamber and
longer processing time will definitely contribute towards
arcing.
Any one of these factors must be isolated or reduced in
magnitude to prevent arcing from occurring. Else, the
final disposition for this defect type is scrap. Due to the
high risk factor of scrapping, recipe optimization was
performed with these factors in mind to reduce the
backside helium leak alarm.
II. RECIPE OPTIMIZATION
Recipe optimization is normally involved with driving
the plasma to etch faster while maintaining the current
process of record (POR) profile in terms of uniformity
across the wafer. This is preferably obtained using fast
etching rate with high radio frequency (RF) power and
high pressurized process gases. The uniformity across the
wafer is sustained by employing high magnetic gauss
field. Apart from that, the uniformity is also influenced
by the backside helium flow to control the temperature
variation across the wafer.
High RF power when combined with high magnetic
field magnitude in a high pressurized chamber could
deliver the desired results in term of throughput.
However, these combinations would also lead to plasma
instability which could cause process plasma induced
damage (P2ID). This will affect the etch rate especially
the non-uniformity factor. This is overcome by
substituting high magnetic field with optimized dual
helium zone wafer cooling control. Recipe optimization
is much preferred rather than changing the chamber
design and for this case a few equipment parameter
controls were adjusted for example by tightening the
chucking voltage and controlling the backside helium
parameter.
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a) Abnormal – Pad Dual b) Normal Pad
Profile
Fig. 4. Optical images for pad etch
This is due to the fact that the current chucking voltage
setting is not adequate to sustain the wafer during plasma
strike causing the wafer to be displaced and inducing
arcing at the wafer edge.
The objective of this paper is to minimize backside
helium leak alarm to reduce arcing and to ensure the
chamber utilization is lengthen. When arcing wafer is
detected in-line, the affected chamber is opened to ensure
no immediate impact on the ESC or the process chamber.
This caused the chamber utilization to be less than the
desired lifetime. This is not feasible for running
production. In order to minimize this recipe optimization
is performed on affected product.
The criteria set to minimize arcing are:
1) The wafer will not have any backside helium leak
alarm during processing
2) There will be no major changes on the process recipe
3) There will be no arcing damage
4) The uniformity is evenly distributed across the wafer
and from wafer to wafer
5) There will be no pad dual profile issues as shown in
Fig. 4.
6) There will be no variation and impact on other
product due to chamber mix run
III. EXPERIMENTAL PROCEDURE
A. Hardware Optimal Setting
The objective of the experiment is to find the optimum
setting in controlling the chucking voltage with the
current dual helium cooling control setting. The
experiment is developed using short loop wafer prepared
from top metal to passivation stack. The process
chamber deployed for this project is the Magnetically
Enhanced Reactive Ion Etcher (MERIE) chamber. The
setting employed for the dual zone helium is centre/ inner
zone flowing higher than the outer zone. Fig. 5 showed
the dual zone distribution on the chuck.
 TABLE II
TABLE I
RESULT FROM TABLE I
DESIGN OF EXPERIMENT TO MINIMIZE
Std Run RF Chucking BHe
ARCING DEFECT Order Order Power Voltage Flow Result
Std Chucking BHe 5 1 0 1 1 0.9
Order Run Order RF Power Volt Flow 3 2 0 0 0 1.2
5 1 0 1 1 8 3 1 0 1 1.5
3 2 0 0 0 7 4 0 0 1 1.6
8 3 1 0 1 4 5 1 0 0 19.0
7 4 0 0 1 2 6 1 1 0 1.2
4 5 1 0 0 1 7 0 1 0 1.0
2 6 1 1 0 6 8 1 1 1 1.6
1 7 0 1 0
6 8 1 1 1
using visual image only. This is also to study the effect
The factors selected for analyses were: of polymer peeling which could drop onto the ESC which
1) RF Power could cause backside helium leak alarm flow fault to
2) Chucking voltage occur.
3) Backside Helium (BHe) flow
IV. RESULTS & DISCUSSION
The method for analysis is using the Design of A. Hardware Optimal Setting
Experiment Tool. These factors require high and low
values which were obtained from other baseline process The result for the experiment is shown in Table 2
and from vendors’ recommendation. The preferred above. The result is presented in such way that zero
setting for backside helium flow is the inner zone must would be the best result without any leak rate flow fault.
always be flowing higher than outer zone. The chucking This result represents the leak rate value that occurred
voltages proposed for the experiments were -500 volt (V) during the alarm. Run order 5 reported the highest leak
as high condition and -750V as low condition. The RF rate and upon verification, it is found that the wafer
power employed for these experiments were 1600 watt backside has white polymer sticking due to incoming
(W) as high value while 500 W as low value. The process.
backside helium setting for inner and outer were 16 torr
(T)/ 12T as high condition while 15 T/9 T as low This white polymer is later confirmed to be coming
condition. The design of experiment is tabulated in Table from the deposition chambers. This caused higher
1. The result is categorized as having a minimum backside helium leak rate since the helium flow is
backside helium leak rate flow fault alarm as 0 while obstructed by foreign materials.
getting maximum backside helium leak rate flow fault
alarm as 1 from these standard run. Comparing between backside helium (BHe) flow of
15/9 T and 16/12 T, pad dual profile was observed at the
B. Chamber Mix Run wafer edge as shown in Fig. 4. This is due to temperature
The final approach is to segregate these products into factor. The backside helium cooling is responsible for
two main groups for data collection. The period selected the temperature cooling efficiency across the wafer.
is during one chamber wet clean duration. Product with However, there are limitation due to thickness with
low RF power is dedicated inside one chamber and respect to the numbers of metal layers stack and the
product with low RF power is mixed run with high RF backside helium flow pressure. The current setting was
tested using 5 metal layers. In the case of more than 5

Fig. 5 The dual helium zone wafer cooling control.

Fig. 6 Polymer peeling due to product mix run.
metal layers, care should be taken to consider pad dual
power dedicated to run inside one process chamber. The
profile in determining the final optimum setting due to
objective is to study the polymer deposited inside the
the cooling efficiency effect. The final backside helium
chamber during one wet clean period. This is verified
setting is set at 16 / 12 T.

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 The chucking voltage also plays an important role in
controlling the wafer backside helium flow. Steady wafer
control on the Electro Static Chuck (ESC) was achieved
by having negative chucking. The negative chucking
voltage allows small gap for the backside helium to flow
through causing less helium leak rate alarm to occur. The
steady flow of BHe is obtained using 16/12 T and
negative chucking ESC.
B. Chamber Mix Run
The wet clean duration for one pad chamber is set to
150 RF hours. However, this is hard to achieve due to
arcing. ESC has to be verified in good working condition Fig. 8 Polymer blocking helium flow.
to prevent lift pin from melting and the only way to
perform this is to open the chamber for wet clean.
There is also impact observed from mix run chamber
After chamber dedication, high RF power chamber is
in term of polymer peeling and dropping onto the ESC.
able to reach the maximum lifetime which is around RF
This is prevented by having high RF power recipe and
148 RF hours, which normally could only be achieved
low RF power recipe being separated into different
around 80 RF hours due to backside helium leak flow
process chambers.
fault alarm. Fig.6 shows the image taken from the
Incoming process also contributed to backside helium
product mix run process kits during chamber dedication
flow obstruction with reference to Run Order 4, where
period. Polymer is observed to be peeling from the
white polymer is observed at the wafer backside causing
process kits. This is compared with uniform polymer
high leak rate flow fault alarm. This is prevented by
sticking on process kit chamber wall in Fig. 7 taken from
highlighting to Thin Film group to ensure the robot blade
the single product dedication for one wet clean duration
is free from particle to prevent polymer sticking to wafer
period. The polymer is observed to be uniformly
backside.
distributed on the chamber wall reducing the risk of
Backside helium flow plays an important role in
polymer peeling and blocking the backside helium flow
cooling the temperature across the wafer during
on the ESC as shown in Fig 8.
processing, however care to be taken for five metal layers
where the backside helium cooling will not be able to
V. CONCLUSIONS
remove the heat from the photo resist causing it to melt
The arcing defect detected at pad etch is presented. and creating the pad dual profile.
This occurred due to plasma instability caused by Currently, there is no arcing defect detected since
obstruction at backside helium flow. The design of recipe release and implementation. Due to this factor, all
experiment to find the optimal setting for backside the chambers are able to reach maximum wet clean cycle.
helium flow and chucking voltage were presented.
Recipe optimization is performed to ensure there is no ACKNOWLEDGMENT
equipment alarm that could lead to arcing defect. The The paper is not possible without the support and
arcing defect could be prevented by having low RF encouragement from the X-FAB Management Team. We
power, no magnetic field, shorter processing time and would like to take this opportunity to extend our
lower pressure based recipe. appreciation to the Defect Management, Yield
Enhancement, Quality, Reliability & Assurance and
Operation. We would like to express our humble
gratitude to Miss. Florence Chai from DM for her
technical advice and contributions for this paper.

REFERENCE

[1] T. Watanabe and Y. Yoshida, “Dielectric breakdown

of gate insulator due to reactive ion etching,” Solid
State Technology, vol. 27, no. 4, 1984, pp. 263-266.

[2] S. J. Fonash, C. R. Viswanathan, and Y. David Chan,

Fig. 7 Uniformly distributed polymer on wall chamber “A Survey of Damage Effects in Plasma Etching,”
running with low RF power recipe. Solid State Technology. Vol. 37, no. 99, 1994.

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