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510 IEEE ELECTRON DEVICE LETTERS, VOL. 25, NO.

7, JULY 2004

A Highly Threshold Voltage-Controllable 4T FinFET


with an 8.5-nm-Thick Si-Fin Channel
Yongxun Liu, Meishoku Masahara, Kenichi Ishii, Toshihiro Sekigawa, Hidenori Takashima, Hiromi Yamauchi,
and Eiichi Suzuki

Abstract—Highly threshold voltage ( th )-controllable four-ter-


minal (4T) FinFETs with an aggressively thinned Si-fin thickness
down to 8.5-nm have successfully been fabricated by using an ori-
entation-dependent wet-etching technique, and the th controlla-
bility by gate biasing has systematically been confirmed. The th
shift rate ( = th 2 ) dramatically increases with re-
ducing Si-fin thickness ( Si ), and the extremely high = 0 79
V/V is obtained at the static control gate bias mode for the 8.5-nm-
thick Si-fin channel device with the 1.7-nm-thick gate oxide. By
the synchronized control gate driving mode, = 0 46 V/V and
almost ideal S-slope are achieved for the same device. These exper-
imental results indicate that the optimum th tuning for the high
performance and low-power consumption very large-scale integra-
tions can be realized by a small gate bias voltage in the ultrathin
Si-fin channel device and the orientation-dependent wet etching is
the promising fabrication technique for the 4T FinFETs.
Index Terms—Double-gate (DG) MOSFET, FinFET, four-ter- Fig. 1. Schematic cross-sectional structures and electrical symbols for (a)
minal (4T) FinFET, orientation-dependent etching, (110)-oriented usual three-terminal FinFET and (b) proposed four-terminal FinFET.
SOI, short-channel effects (SCEs), threshold voltage th control.
In this letter, we present the successful fabrication of the 4T
I. INTRODUCTION FinFETs with an aggressively thinned Si-fins by the orienta-
tion-dependent wet etching, and demonstrate the excellent

T HE DOUBLE-GATE (DG) MOSFET [1] is well rec-


ognized as the most promising candidate for future
ultimately scaled very large-scale integrated (VLSI) circuits
controllability with the 4T device by reducing down to 8.5
nm, which is the thinnest Si-fin channel among all FinFETs re-
ported so far. We also discuss the dependence of the
[2]–[7]. Among several types of DG MOSFETs, the fin-type tunable range.
DG MOSFET (FinFET) has widely been investigated because
of its simple fabrication process. In the usual FinFETs, how- II. DEVICE FBRICATON
ever, the threshold voltage ( ) is mainly determined by the
gate work function [3] and its control is difficult because of the The schematic structure of the proposed 4T FinFET is
inseparable double gates as shown in Fig. 1(a). For the future shown in Fig. 1(b). By separating the double gates as shown
ultralow power circuits design, the flexible control will in Fig. 1(b), the 4T-driven FinFET is available, which leads to
inevitably be required. For this purpose, although the traditional flexible control as will be shown later. To fabricate ultrathin
planar-type DG MOSFET [8] can provide the controlla- and perfect rectangular cross section Si-fins by wet etching,
bility, the device fabrication processes, especially for the perfect we used lightly doped ( cm ) p-type (110)-oriented
self-aligned top and bottom gates, are still difficult. Recently, silicon-on-insulator (SOI) wafers as a starting material. The
we developed the simple processes for fabricating ultra-narrow initial thickness of the (110) SOI and buried oxide (BOX)
Si-fins and Si-walls for the fin-type and vertical-type DG MOS- layers were 100 and 300 nm, respectively. The fabrication
FETs [6], [9] by the orientation-dependent wet etching, and the processes of the Si-fins were almost the same as described in
high drive current and excellent subthreshold characteristics the previous report [6].
have experimentally been confirmed in the fabricated FinFETs First, heavily doped n source/drain (S/D) contact regions
[6]. However, there are very few studies [10]–[12] on the were formed by phosphorus thermal diffusion. Then, a 20-nm-
controllable independent DG FinFETs have been reported. thick nondoped silicate glass (NSG) layer and a 30-nm-thick
nitride (Si N ) layer were deposited considering higher pol-
ishing selectivity of 4.3 for poly-Si–Si N than that of 1.7 for
Manuscript received April 12, 2004; revised May 7, 2004. This work was
supported in part by the program for the support of young reserachers with a poly-Si–NSG. The EB-resist fin-mask patterns were shaped on
term from the Ministry of Education, Culture, Sports, Science, and Technology. the wafer in parallel in a direction by EB lithography, and
The review of this letter was arranged by Editor B. Yu. were trimmed by O ashing. To form the upright Si-fins with
The authors are with the National Institute of Advanced Industrial Science
and Technology (AIST), Ibaraki 305-8568, Japan (e-mail: yx-liu@aist.go.jp). (111)-oriented channel surface, the SOI layer was etched with
Digital Object Identifier 10.1109/LED.2004.831205 a 2.38 % tetramethylammonium hydroxide (TMAH) solution
0741-3106/04$20.00 © 2004 IEEE
LIU et al.: HIGHLY THRESHOLD-VOLTAGE CONTROLLABLE FOUR-TERMINAL FinFETs 511

Fig. 2. Cross-sectional STEM image of the fabricated ultranarrow ideal


rectangular Si-fin channel across the gate. The Si-fin thickness and height are
T = 8:5 nm and H = 80 nm, and the aspect ratio is 9.4.

at 50 C for 1 min. For the FinFETs with (111)-oriented side-


wall fin, the high current drivability was experimentally con-
firmed [6], which might be attributed to crystallographic flat-
ness of (111) sidewalls, causing less surface roughness scat-
tering [13]. The gate oxide thickness was 1.7 nm. The n
poly-Si gates were made by using EB lithography and reactive
ion etching. After removing the thin oxide layer on the sidewalls
of extension regions, the ultrashallow phosphorus diffusion into
the S/D extension regions was performed by rapid thermal an-
nealing. To separate the initial poly-Si gate, the convex area at
the crossregion of the poly-Si gate and Si-fin was polished to
the stopper Si N –NSG layer by using a chemical–mechanical
polishing (CMP) process. The key issue is how to stop the CMP
at the appropriate height. We monitored the poly-Si layer thick-
ness at the gate electrode regions carefully to insure the accurate Fig. 3. Electrical characteristics of the fabricated 4T FinFETs with the same
CMP stopping at the top of stopper mask. Then, a 70-nm-thick L = 160 nm and T = 1:7 nm at the static biasing mode operation. (a)
I –V characteristics at different V for the 8.5-nm-thick Si-fin channel
NSG layer was deposited to protect the processed wafer surface. device and (b) V and S-slope as a function of V with different T from
Finally, the contact holes and aluminum electrodes were formed 8.5 to 43 nm.
and sintered in a pure H ambient at 400 C for 30 min.
ranging from 8.5 to 43 nm and with the same nm
III. RESULT AND DISCUSSION and nm. It is noteworthy that we achieve the very
Fig. 2 shows the cross-sectional scanning transmission-elec- large of 0.79 V/V for the ultrathin 8.5-nm-thick Si-fin 4T
tron microscope (STEM) image of the fabricated 4T FinFET device. These experimental results clearly indicate that the
with an 8.5-nm-thick Si-fin channel. It is clearly confirmed that thinner is effective to obtain a flexible tuning with the
the poly-Si gates were completely separated, and the Si-fin cross larger , i.e., the can be controlled by the lower control
section shows an ideal rectangular channel shape. Thanks to the voltage in the case of the thinner . This fact can be easily
electrically isolated double gates, we can use a DG MOSFET understood from the simple capacitor model. For the fully
as a 4T-driven MOSFET and expect new functions such as a depleted 4T FinFET, the shift rate can be expressed as
threshold voltage control. Here, we define the left gate as , where and
a driving gate, and the right gate as a control gate. are the driving-gate and control-gate capacitances, and
The measured – characteristics of the 4T FinFET with is the capacitance of the depleted Si-fin channel layer. If the
the 8.5-nm-thick Si-fin channel and 160-nm gate length at double gates have the same gate oxide thickness, , the can
different values of from to 0 V are shown in Fig. 3(a). be expressed as . It is obvious that the
It is noteworthy that the – curve shifts linearly with increases with reducing . However, it is noticed in Fig. 3(b)
biases, which implies that the can be controlled flexibly that the S-slopes are deteriorated when reducing in this
by changing . The Si-fin thickness dependence of the static biasing mode at V due to the undesirable
– characteristics was also examined, and it was found relation of S-slope [14] for our case of the long
that the shift rate defined by dramatically of 160 nm. At V region, the right channel
increases with reducing . Fig. 3(b) shows the accumulated controlled by the control gate changes from depletion
results of the (at A/ m, V) and state to inversion state by increasing , which results in the
S-slope as a function of for the 4T FinFETs with various abrupt changing in the S-slope and [7].
512 IEEE ELECTRON DEVICE LETTERS, VOL. 25, NO. 7, JULY 2004

In the fabricated 8.5-nm-thick Si-fin channel 4T FinFET, we


demonstrated the high shift rates of V/V in the
static control gate biasing mode, and V/V in the
synchronized control gate driving mode with an offset voltage.
The 4T FinFETs are attractive for flexible power-controllable
VLSI circuits.

ACKNOWLEDGMENT
The authors would like to thank Dr. T. Tsutsumi of Meiji Uni-
versity and Dr. K. Sakamoto of AIST for fruitful discussions,
and Dr. S. Kanemaru, Dr. M. Nagao and Dr. T. Matsukawa of
AIST for their help with the device fabrication.

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