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A MOS Transistor with Source/Drain on Insulator and

Channel Doped in Step-Function Profile


Dingyu Li, Wei Ke, Lei Sun, Xiaoyan Liu, Ruqi Han, and Shengdong Zhang

Abstract -A new MOS device design applied to the concern, the threshold voltages are very sensitive to the
nano-scale is proposed. In this design, while the UTB thickness, resulting in a critical requirement for the
channel region is in the substrate, the source and drain UTB film thickness uniformity, which is extremely
regions except for the lateral sides connecting to the difficult to meet with the current SOI techniques[1].
channel are insulated from the substrate. The insulated
source/drain helps to reduce the junction capacitances In this paper, a new device design for nano-scale
and leakages, and potentially eliminate the CMOS technology is proposed. The proposed approach
punch-through between them. On the other hand, the allows devices to possess the advantages of both
channel region is doped in a step-function (extremely super-halo-doping and UTB schemes, and at the same time
retrograde) profile to minimize the threshold voltage eliminate or avoid the disadvantages of them. We present
variations caused by dopant number fluctuations and the characteristics of the proposed devices compare with
the carrier mobility degradation related to the high that of the devices with super-halo schemes and UTB
electrical field in the channel region. The device
characteristics of MOSFETs with the new design are structures in detail.
compared with that of both bulk devices with
super-halo doping profile in the channel and the Ultra IL. SIMULATION
Thin Body (UTB) SOI MOSFETs. The Simulated
results show the new design provides nano-scale MOS Fig. 1 shows the schematic cross-sectional structure of
devices with similar or better short channel effect the proposed SDOI structure MOSFETs. As shown, while
immunity and sub-threshold characteristics to or than the channel region is still in the bulk substrate, the
both super-halo and UTB schemes. A process for
fabricating the device with the proposed design is also source/drain region locates on the insulators. That is, the
investigated. source/drain is insulated from the substrate except for the
lateral sides connecting to the channel. In this way, the
I. INTRODUCTION punch-through between the source and drain is eliminated
if the source/drain is thin enough, and the parasitic
With CMOS technology scaling into sub-50 nm source/drain junction capacitance and leakage are
nodes, the device shrinking is getting ever more minimized.
challenging since the fundamental and practical limitations
start to take effect significantly[1-5]. A lot of approaches
have been proposed to develop suitable device technology
for sub-50 nm ULSI applications in the recent years. Of
those approaches, the super-halo doping and
ultra-thin-body (UTB) are two major representatives. The
super-halo doping offers much improved short channel
effect immunity and threshold voltage adjustment I
capability, but it necessitates a precise doping profile
control[6-8]. In addition, the large junction capacitance Fig. 1. Schematic cross-sectional structure of the
/leakage, and threshold voltage variations caused by the proposed transistor design.
dopant number fluctuation remain the major concerns due
to the high doping concentration. On the other hand, the At the same time, the channel region in the substrate
UTB devices have highly suppressed short-channel effects, is doped in a Step-function (extremely retrograde) profile.
small parasitic capacitances, nearly ideal sub-threshold And the step-function profile is lightly doped at the
swings, and minimized statistical dopant fluctuation substrate surface and heavily doped in the underneath. The
effects if the UTB is un- or lightly doped[l, 9, 10]. light doping region prevents a high electrical field from
Unfortunately, in addition to the intrinsical floating body being developed at the surface, resulting in less degraded
carrier mobility there. The heavily doped region shields the
Dingyu Li, Wei Ke, Lei Sun, Xiaoyan Liu, Ruqi Han, source from the drain field penetration, keeping a low
and Shengdong Zhang are with the Institute of drain induced barrier lowering (DIBL). Moreover, the
Microelectronics, Peking University, Beijing China, step-function profile in doping minimizes the threshold
100871, E-mail:zsd(d3ime.pku.edu.cn voltage variations caused by the dopant number fluctuation

0-7803-9339-2/05/$20.00 02005 IEEE. 683


since it greatly reduces the dependence of the threshold substrate is kept grounded in all cases. It can be seen that
voltage on the dopant concentration in the channel region. super-halo doping profile suppresses threshold voltages
roll-off more efficiently than the step-function doping
The electrical characteristics of the proposed devices profile as Lg equals to 40 nm. However, as the Lg decreases
shown in Fig. 1 were simulated using the device simulator to 20nm, Super-halo doping profile has nearly no any more
ISE 8.0. In the simulation, the thickness of the gate oxide superiority than the step-function profile. As Lg decreases
(T0x) and that of the oxide under the source/drain (TSd) are from 100nm to 20nm, the threshold voltage roll-off of
constantly 1.5 nm and 20 nm, respectively. The low and UTB structure becomes much bigger than that of both the
high dopant concentrations forming the step-function super-halo schemes and the SDOI structure.
doping profile in the channel regions are lX 1016 CM-3 and
Ix 1 0'9cm-3, respectively. The doping concentration in the
source/drain is l x I020 cm -3. 50
0
III. RESULTS AND DISCUSSIONS
-50
With the gate length scaling down, the influence of >-100
drain induced barrier lowering (DIBL) effect becomes
> -150 -lthe proposed devices
more and more strong and the short channel effect (SCE) is
-U- Super-halo schemes
more serious. Fig. 2 shows the DIBL effects versus the -200 - UTB Structure
gate lengths (Lg) in the super-halo scheme, the proposed
-250
design and UTB scheme. The DIBL here is defined as the
difference between the threshold voltages (Vt) at the drain 20 40 60 80 100
voltages (VdS) of 0.05 V and 1 V, respectively. The silicon L /nm
substrate is kept grounded in all cases. It can be observed Fig. 3. Comparison of threshold voltage roll-offs among
that super-halo schemes suppresses DIBL effect more with super-halo doping, the proposed and UTB schemes.
efficiently than the step-function doping profile and UTB The gate length is from 20 nm to 100 nm. The thickness of
structure as Lg equals to 100 nm. However, when Lg equals the source/drain (TSd) equals to 20 nm. The thickness of the
to 20 nm, super-halo doping and the proposed design have silicon film for UTB devices is also 20 nm.
almost same suppressing capability to the DIBL effects. In
general, UTB structure has the worst DIBL effect. Fig. 4 illustrates the sub-threshold swings versus the
gate lengths (Lg) in the devices with super-halo doping, the
proposed and UTB schemes. It is seen that the proposed
600 -
and super-halo doping designs offer the larger (worse)
-
sub-threshold swings than the UTB ones when channels
500 - the proposed devices
- Super-halo schemes are relatively long, but start to exhibit better sub-threshold
400 -H-UTB Structure characteristics with the channel lengths scaled down to 50
E 300 nm and below. It can be easily understood that the worse
sub-threshold characteristics in the long channel cases are
200 due to the fact that the proposed devices are intrinsically
100L built on the bulk substrate. Once again, it is demonstrated
the proposed design is more preferable for extremely
scaled devices than UTB scheme. It can also be seen that
20 40 60 80 100
L 9/nm
Super-halo schemes present smaller sub-threshold swings
than the Step-function ones. Therefore, the super-halo
Fig. 2. Comparison of DIBL effects versus gate length doping profile has a better scaling down capability than the
among with super-halo, the proposed and UTB schemes. Step-function ones. However, as we see from the graph,
The gate length is from 20 nm to 100 nm. The thickness of the superiority of the super-halo doping profile is very
the source/drain (TSd) equals to 20 nm. The thickness of the small. The sub-threshold swings of the devices both with
silicon for UTB scheme is also 20 nm. the super-halo and the proposed design reach 150mV/dec
as Lg equals to 20 nm.
Fig.3 shows the threshold voltage roll-off versus the
gate lengths (Lg) in the devices with the super-halo, the Due to the existence of the insulator under source
proposed and UTB designs. The threshold voltage roll-off and drain, the SDOI structure MOSFETs must be employ
(AVt) is the deference between the threshold voltages at a the thin body to suppress the DIBL effect and SCE as the
given channel length and the 100 nm channel length, UTB SOI devices. Therefore, the thickness of source/drain
respectively, with the drain biased at 0.05V. The silicon (TSd) is the key parameter for the proposed devices. Fig. 5

684
shows the dependence of the DIBL on TSd with a 30 nm channel effect immunity and good sub-threshold
channel length. characteristics can be maintained even though Tch varies in
a wide range. It has been known that the threshold voltage
240 . of the device with the channel doped in a step-function
profile depends on the depth (TCh) of the light doping
200 -U-the proposed devices region. The proposed design makes it feasible to adjust
-*- Super-halo schemes threshold voltage through changing TCh-
UTB Structure
o
a)
160

E 120 120 -
c8 0

10>

80 1 10 R;
E

20 40 60 80 100 100 *_
*3
Lg/nm -J
m 90 *O
Fig. 4. Comparison of sub-threshold swings of Super-halo 0

schemes, the proposed devices and UTB schemes. The 80 CD


gate length is from 20 nm to lOOnm. The thickness of the
source/drain (TSd) equals to 20nm. The thickness of the 70 =

silicon for UTB is also 20 nm. Cl,

Tch -Tsd [nm]

Fig. 6. Dependences of DIBL and sub-threshold swing of


600 I the proposed devices the proposed device on the depth (TCh) of the lightly-doped
{I-- Super-halo schemes
500 - E3 UTB Structure
channel region minus the source/drain thickness (TSd).
> 400
-E
m 300 IV. PROPOSED FABRICATION PROCESS
0
200
A fabrication process to realize the proposed device
100
structure is also designed with major steps shown in Fig. 7.
. . . . . . . . .
0 5 10 15 20 25 30 35 The step-function doping profile is formed prior to the STI
Tsd/nm (shallow trench isolation) step by epitaxially depositing an
un-doped silicon layer on the heavily doped substrate as
Fig. 5. Comparison of DIBL effects versus thickness of shown in Fig. 7(a). The gate definition and nitride spacer
the source/drain (T,d) among with super-halo doping, the formation are the same as the conventional ones except for
proposed and UTB schemes. Tsd is from 5 nm to 30 nm. adding a nitride cap on the gate as shown in Fig. 7(b). A
The thickness ofthe silicon for UTB is also from Snm to 30 conventional reactive ion etching (RIE) is then performed
nm. The gate length equals to 20 nm. to remove the exposed silicon in the un-masked area till the
heavily doped regions are reached, and subsequently a
It can be observed clearly in the graph that the Vt high-selective etching solution, e.g. HF: HN03: H20 [11],
shifts of the three structures are almost same as T,d is very is used to take away the heavily doped silicon under the
small. As T,d inceases, V, shift of all of them increases. It is un-doped source/drain region, as is shown in Fig. 7(c). It
easily understood that the thinner film, the better short should be pointed out that the thickness of the un- or
channel effect. For the super-halo schemes, the lightly doped source/drain region may be reduced as
suppressing capability of the short channel effect is much required by performing an extra doping with ion
more than that of the step-function doping profile, implantation prior to the nitride spacer formation. That is,
especially as the Tsd is larger than 20nm. the source/drain thickness and the depth of the un- or
Fig. 6 shows the dependences of DIBL and lightly doped channel region can be determined
sub-threshold swing on the depth (TCh) of the lightly-doped independently. The resulted caves from the silicon
channel region minus the source/drain thickness (Tsd) with removal are then filled up with a conformal oxide
the proposed device having a 30 nm channel length. It can deposition and etching-back as shown in Fig. 7(d). After
be observed in Fig. 6 that DIBL and the sub-threshold removing the nitride spacers and cap, forming the thin
swing have weak dependences on the TCh variation over a oxide spacer and doping the source/drain and gate, the
relatively wide range, especially for the smaller process proceeds to the conventional back-end steps. Note
source/drain thicknesses (TSd). It means that strong short that the source/drain contact area can be raised using an

685
epitaxial growth right after the thin oxide spacer formation design does in the long channel region. However, as the
if it is too thin to ensure a low contact resistance. gate length scales down to 20 nm, the short channel effect
(SCE) and drain induced barrier lowering (DIBL) effect
[I Un-doped E3Heavily doped "Nitride are almost similar in both the super-halo schemes and the
proposed design. The simulated results also show the new
U Poly-Si EJOxide design provides nano-scale devices with better short
channel effect immunity and sub-threshold characteristics
than UTB schemes.

Acknowledgement
(a) This work is supported by the National Nature
Science Foundation of China (NSFC) under Grant
904070 10 and partially by the National High Technology
Research & Development Program of China under Grant
2003AAlZ1370 and the National Basic Research Program
of China under Grant 2000036500.

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