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High-Performance P-Type
Independent-Gate FinFETs
David M. Fried, Student Member, IEEE, Jon S. Duster, Member, IEEE, and Kevin T. Kornegay, Senior Member, IEEE
I. INTRODUCTION
TABLE I
SUMMARY OF EXTRACTED DEVICE PARAMETERS IN DOUBLE-GATE MODE (DG, BOTH GATES MODULATED SIMULTANEOUSLY) AND
INDEPENDENT-GATE MODE (IG, ONE GATE HELD CONSTANT WHILE OTHER GATE MODULATED)
Fig. 3. Cross section SEM showing fin capped by oxide hard mask and
surrounded by Polysilicon gates.
dition to several parameters extracted from the test data. The collected as part of this work shows statistical proof of sev-
DG mode trends show several advantages of thinner fins. Lines eral elements of double-gate and back-gate physics. Process im-
2 and 3 show a severe increase in off-current of short-channel provements are necessary for high-performance applications.
devices as a function of fin thickness. This increase is tightly Future research includes additional process enhancements and
coupled to the threshold voltage rolloff, as seen on Line 7, re- CMOS integration.
sulting in the increase in drain-induced barrier lowering (DIBL)
for these devices, as shown on Line 8. A major advantage of
thinner fins can be seen on Line 9, with the dramatic increase
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IV. CONCLUSION 2003.
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