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Impact of Process

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Impact of Process

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8, AUGUST 2008

Optimized 10-nm FinFET

Hasanur R. Khan, Student Member, IEEE, Denis Mamaluy, Member, IEEE, and

Dragica Vasileska, Senior Member, IEEE

Abstract—We examined the influence of process variation on DG MOSFETs are examined in [7]. In addition, the allowable

device performance of the optimized 10-nm FinFET device using bottom gate misalignment of very deep-submicrometer devices

a fully self-consistent quantum–mechanical transport simulator due to process variation is studied in that work. Very recently,

based on the contact block reduction method. Sensitivity of the

on-current, leakage currents, threshold voltage, drain-induced the impact of process variation on device performance and a

barrier lowering, and subthreshold swing for the optimized comparative study of process variation tolerance among bulk

FinFET to process variation at room temperature have been inves- MOSFET, FinFET, and nanowire/nanotube FETs have been

tigated. Subthreshold source-to-drain leakage current is found to presented in [8].

be the most sensitive parameter to process variation. Gate leakage In this paper, we investigate the fluctuation in performance

current has been analyzed for both poly-Si gates and gates with

the work function of 4.35 eV. For poly-Si gates, the gate leakage is due to process variation in the optimized FinFET, which we

found to influence the subthreshold swing below or at a gate oxide theoretically studied by using our fully quantum–mechanical

thickness of 1 nm. Device performance has also been analyzed at contact block reduction (CBR) simulator in [1]. In this paper,

“slow process” corner to estimate the worst case degradation in we do not include parasitic source/drain series resistance in

performance matrices of the considered nano-FinFET. our simulation. Simulation results presented here are obtained

Index Terms—Contact block reduction (CBR) method, FinFET, by using effective mass approximation and quantum ballistic

process variation, quantum transport, slow corner analysis. transport formalism with electron–electron interaction that is

taken into account by using the exchange and correlation

I. INTRODUCTION terms in LDA approximation [2]. No scattering on phonons

is accounted for in this paper. The latter approximation was

A S WE APPROACH 22-nm node technologies, different

novel device structures have been evolved to overcome

the scaling limits of conventional bulk MOSFETs. Among

necessary to perform a large number of simulations within

a reasonable time; yet, we believe that it did not introduce

these structures, FinFETs [3], [4] are expected to be in mass a significant error since in the considered ultrascaled device,

production beyond 32-nm node technology in the near future phonon scattering accounts for only about 10%–15% of the

[5]. Naturally, these ultrascaled semiconductor devices may be on-current degradation [1] (similar results were obtained in

very sensitive to process variation. Even a small decrement other recent nano-FinFET study [9]). In addition, in ultrascaled

in the gate oxide thickness can lead to such gate leakage that devices, phonon scattering seems to affect mostly the value of

is unacceptable for a well-performing device. Therefore, once on-current, without introducing any significant correction to the

the general device optimization phase is completed, it is also electron density or subthreshold current [10]. This essentially

very important to analyze the impact of process variation on allows one to perform ballistic quantum simulations, introduc-

device performance so that robust functioning of the devices ing, if necessary, the correction for phonon scattering in the

can be ensured for applications. There are already a number final values of on-current. The main purpose of this paper is

of publications focusing on the impact of process variation in to analyze on-current, leakage, etc., degradations due to the

ultrascaled devices. In [6], the effects of process variation on process variation in the FinFET’s geometry parameters.

threshold voltage, drain-induced barrier lowering (DIBL), and The nominal n-type FinFET structure considered in this

subthreshold swing and the effect of mismatch in gate oxide paper is a 10-nm DG device with a fin width of 4 nm and a

thickness on the device behavior of a 20-nm double-gate (DG) gate oxide (SiO2 ) thickness of 1 nm. Source/drain doping of

FET and FinFET have been presented by using Monte Carlo 1020 cm−3 has been used with a doping gradient of 2 nm/dec

simulation and including quantum effects by density gradient across the underlap region on each side of the gate. Uniform

method. The effects of bottom gate misalignment in symmetric dopings of 1016 and 1020 cm−3 have been assumed for the

body and gate electrodes, respectively. Note that we use a

Manuscript received September 19, 2007; revised February 20, 2008. This continuous model of doping in source/drain and gates. Here,

work was supported in part by the Office of Naval Research under Grant we investigate the sensitivity of the on-current ION (IDS at

N000140610094, by the National Science Foundation, and by the Arizona VGS = VDS = Vdd , where Vdd is the power supply voltage),

Institute of Nano-Electronics (AINE). The review of this paper was arranged

by Editor H. Jaouen. the subthreshold source-to-drain leakage Isd,leak (IDS at VGS =

The authors are with the Department of Electrical Engineering, Arizona State 0 V, VDS = Vdd ), the net gate leakage (IG = IGS + IGD )

University, Tempe, AZ 85287 USA (e-mail: mamaluy@asu.edu). currents (for electrons only), the saturation threshold voltage

Color versions of one or more of the figures in this paper are available online

at http://ieeexplore.ieee.org. Vth,sat , the DIBL, and the subthreshold swing (“swing”) in the

Digital Object Identifier 10.1109/TED.2008.925937 optimized FinFET to process variation at room temperature

KHAN et al.: SIMULATION OF THE IMPACT OF PROCESS VARIATION ON THE OPTIMIZED 10-nm FinFET 2135

TABLE I

SIMULATION RESULTS DUE TO THE PROCESS VARIATION IN FIN WIDTH

tSi AND GATE OXIDE THICKNESS tox . THE VALUES AT THE FIRST ROW

CORRESPOND TO THE NOMINAL DEVICE. GREEN COLOR (ITALIC FONT)

REPRESENTS THE IMPROVEMENT IN THE DEVICE PERFORMANCE,

RED COLOR (BOLD FONT) REPRESENTS THE DEGRADATION IN THE

PERFORMANCE, AND BLUE COLOR (UNDERSCORED FONT)

CORRESPONDS TO THE NOMINAL OR NEAR NOMINAL VALUES

width and gate-oxide-thickness variations, which give the highest value of

subthreshold source-to-drain leakage and the lowest value of on-current at

VDS = 0.8 V.

of 27 ◦ C. The device performance has also been analyzed

at slow process corner (high operating temperature and low occurs for a combination of the narrow fin width of 3.6 nm and

power supply voltage) to estimate the worst case degradation the thick gate oxide of 1.2 nm. On the other hand, a combination

in performance. of the wide fin of 4.4 nm and the thin gate oxide of 0.8 nm

results in the highest on-current value of 3864 µA/µm. The

II. PROCESS VARIATION value of on-current for all other combinations of tSi and tox

remains between these two extreme values. Note that, here, all

In order to examine and compare device performance due current values are normalized by the fin height [1] instead of

to process variation, we vary fin width tSi and gate oxide the “conventional” 2 × fin height. Table I demonstrates the fact

thickness tox as individual parameters and also as different that the best “alternative” to the nominal device would be a

combinations of both. In addition, doping gradient and gate device with even narrower fin width and gate oxide thickness.

length, along with the relative position of the gates with respect However, reducing the former inevitably causes some decrease

to source/drain, have been varied. For each case, we compare in on-current, and reducing the latter, while significantly im-

different important performance matrices. proving the device characteristics, is only possible with the use

of alternative (high-k) gate dielectric materials due to excessive

gate leakage.

A. Variation in Fin Width and Gate Oxide Thickness

Fig. 1 shows the transfer characteristics at VDS = 0.8 V for

In FinFETs, the fin width tSi plays a major role in controlling the nominal device and due to the process variation for such

the device behavior. In the simulation, tSi is varied by 10% combinations of tSi and tox , which provide the lowest ION and

from its nominal value of 4 nm. The gate oxide thickness the highest Isd,leak . Subthreshold source-to-drain leakage

tox is varied by 20% from its nominal value of 1 nm. We current Isd,leak has been reported to be more sensitive to the

think that this 20% variation due to the process variation is a fin width than to the gate oxide thickness [12], which is also in

reasonable assumption for a gate oxide thickness of 1 nm since agreement with our simulation results. For a 10% increase in

a monolayer is roughly on the order of 2 Å. Note that, in this fin width from its nominal value of 4 nm, Isd,leak increases by

paper, we are not simulating surface roughness at the Si/SiO2 77% from its nominal value of 0.75 µA/µm, whereas even for

interface to examine the impact of random local variations in a 20% increase in gate (both front and back) oxide thickness

gate oxide thickness; instead, we are concentrating on the worst from its nominal value of 1 nm, Isd,leak increases by 53% from

case scenario that might occur due to the process variation: its nominal value. However, a simultaneous combination of the

the average oxide thickness’ deviation from its nominal value. wide fin of 4.4 nm and the thick gate oxide of 1.2 nm yields

A detailed study of the impact of surface roughness on the the worst value of Isd,leak , i.e., 2.06 µA/µm, which is about an

device performance for the considered FinFET can be found in increase of 175% from the nominal value. Thus, a variation in

our previous works [1], [11]. Table I summarizes the simulation tox is also significantly affecting Isd,leak .

results for different combinations of tSi and tox due to the Due to the close proximity of gate and drain contact in

process variation, and their effect on the device performance. nanoscale devices, the DIBL plays a very important role in

For a ±10% change in the fin width and a ±20% change in controlling the device behavior. In this paper, the DIBL is

the gate oxide thickness, the device on-current tolerance win- calculated at the drain-to-source current value of 50 µA/µm. As

dow remains between +8% and −4% of its nominal value of shown in Table I, DIBL is very sensitive to the variations in both

3584 µA/µm. The lowest value of on-current (3443 µA/µm) tSi and tox for the considered FinFET. It is interesting to note

2136 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 55, NO. 8, AUGUST 2008

that changes in DIBL values due to 4-Å variation in tSi and 2-Å

variation in tox are identical or very close, as given in Table I.

This indicates that for DG devices with thin body, DIBL may

be roughly represented as a function of the physical distance

between two gates tdist = 2tox + tSi rather than the individual

contributions of tSi and tox . Thus, the effective gate control

should be at minimum for the highest values of tdist , with the

widest fin and the thickest gate oxide. This is consistent with

the worst DIBL value of 62 mV/V (Table I), which is obtained

for tSi = 4.4 nm and tox = 1.2 nm.

Threshold voltage in nanoscale devices is mainly deter-

mined by the gate work-function adjustment [13]. Besides that,

for narrow fin-width FinFETs, threshold voltage is dominated

by fin width tSi , as opposed to the conventional bulk MOSFET,

where tox plays the dominant role in determining the threshold

voltage. In this paper, the saturation threshold voltage has been Fig. 2. Net gate leakage versus gate voltage with tSi = 4.4 nm and tox =

calculated as the gate voltage for which the corresponding drain 0.8 nm for poly-Si and “adjusted” gates at VDS = 0.8 V. Voltage labels (−0.35

current reaches 50 µA/µm (or 500 nA × Wg /Lg , where Wg and 0.45) shown below the horizontal axis correspond to the applied gate

voltages for poly-Si gates.

is the height of the gate [16]) at VDS = 0.8 V. There is a

concern that in devices with very narrow fin, the threshold-

voltage variation caused by fin-width fluctuations may become case of the “adjusted” gates with ΦG = 4.35 eV, we are shifting

very significant due to quantum–mechanical effects (see, for the conduction band in the gates to comply with the chosen

example, [14] and [15]). In our previous work [1], we have gate work function. The poly-Si gates are simulated “exactly”

chosen a fin thickness of 4 nm in an attempt to minimize (within the utilized effective mass Hamiltonian description)

these fluctuations while maintaining a good gate control over since its material parameters are known.

the channel. We see in Table I that saturation threshold volt- The magnitude and trend of gate leakage for poly-Si gates

age varies by approximately 10% from its nominal value of is completely different than that for “adjusted” gates, due to

140 mV due to the process variation in tSi and tox . Thus, the the difference in gate Fermi levels with respect to source and

threshold-voltage fluctuations may not be a concern at least drain Fermi levels. Fig. 2 shows the net gate leakage current

for 4 nm and higher fin-width devices. Note that for a fixed as the gate voltage varies for a combination of tSi and tox ,

gate oxide thickness, the threshold voltage increases as the which gives the worst OFF-state gate leakage for both poly-

fin width is reduced [17]. This is caused by the energy level Si and “adjusted” gates at VDS = 0.8 V. Voltage labels (−0.35

quantization, which increases the effective energy band gap and 0.45) shown below the horizontal axis correspond to the

for narrow fin devices. In addition, Table I demonstrates that applied gate voltages for the poly-Si gates. One can see a very

for the considered device, the threshold voltage also increases significant difference (50×) in the maximum OFF-state gate

when the gate oxide thickness is reduced. This happens due to leakage current values between the poly-Si gate (with no work

a particular choice of the device gate work function. The gate function adjusted) and the gates with work function adjusted. In

work function for the nominal device [1] has been chosen to set the following, we will present gate leakage data for the device

the off-current, which puts the device into weak accumulation with “adjusted” gates only.

regime at VGS = 0 V. For a thin gate oxide, the bending of Fig. 3 shows the absolute values of OFF-state (VDS =

the conduction band at the Si/SiO2 is higher than that for a 0.8 V, VGS = 0 V) gate leakage for different combinations of

thick gate oxide. Therefore, with a thin gate oxide, one needs tSi and tox . As expected, the gate leakage increases exponen-

to apply higher gate voltage to bring the device into inversion. tially with the decrease in tox . However, it is also possible

Consequently, the threshold voltage increases with decreasing to reduce the OFF-state gate leakage by scaling down the fin

gate oxide thickness for the considered device. width (for a fixed gate oxide thickness), as shown in Fig. 3.

Gate leakage is becoming an increasingly important issue It is interesting to note that in the considered case of 10%

in optimizing device performance, as the scaling of gate oxide fin reduction, the corresponding degradation in on-current is

(SiO2 ) thickness is approaching 1 nm [18]. One of the greatest insignificant, which is less than 1% from its nominal value

advantages of the CBR method [19] is its ability to treat the of 3584 µA/µm. Therefore, to minimize the gate leakage in

gates on the same physical ground as the source and drain leads, ultrascaled devices, one should also consider, when possible,

allowing one to calculate the gate leakage current accurately the reduction of Si channel width in addition to the use of

and fully self-consistently with the rest of the device [2]. alternative (high-k) dielectrics.

The gate leakage current strongly depends on the accurate The gate-to-drain and gate-to-source leakage current compo-

description of the gate material (i.e., effective masses and nents are shown in Fig. 4 as the functions of gate voltages for

dielectric constant). Since properties of gate material with the different values of tSi with tox fixed at 1 nm. Reducing the fin

work function ΦG = 4.35 eV used for the considered FinFET thickness decreases the absolute value of the OFF-state gate-to-

[1] are still not known, in this paper, all the leakage data are drain–current (due to the increased energy level separation in

obtained by using effective masses of Si for the gates. In the the channel) and increases the ON-state gate-to-source current

KHAN et al.: SIMULATION OF THE IMPACT OF PROCESS VARIATION ON THE OPTIMIZED 10-nm FinFET 2137

affects the device turn-off behavior. Our simulations show that

the worst subthreshold swing value of 180 mV/dec is ob-

tained for a combination of tSi = 4.4 nm and tox = 0.8 nm for

poly-Si gates.

Overall, Table I shows that performance metrics of the

considered ultrascaled FinFET can be divided into two main

categories, regarding their sensitivity to the process variation in

tSi and tox , namely: 1) those that are predominantly affected

by tox fluctuations and 2) those that can be described by the

fluctuation of the “physical distance” between the gates tdist =

2tox + tSi . The oxide-thickness-sensitive parameters are the

on-current and the subthreshold swing (in the case of poly-Si

gates). The parameters that are sensitive to variations in the

physical distance are the subthreshold source-to-drain leakage

current, the DIBL, the threshold voltage, and the subthreshold

swing (in the case of “adjusted” gates).

Fig. 3. Absolute values of the OFF-state “adjusted” gate leakage current in

nanoamperes per micrometer for different combinations of tSi and tox . B. Gate Length and Its Placement Variation

One of the major advantages of FinFETs is that gates are

automatically aligned with each other and with source and drain

[20]. As a result, parasitic capacitance due to gate misalignment

is negligible, and gate capacitances are symmetric with respect

to the channel in FinFET devices. Therefore, we only investi-

gate the device performance for a ±12% variation in the phys-

ical gate length of the nominal device Lg,nom from its value

of 10 nm, assuming that the gates are perfectly aligned. We

take into account both the symmetrical and asymmetrical gate

length variations, assuming that, for the same device length, the

total change in gate length ∆Lg can be distributed on the source

side (∆Lgs ) and the drain side (∆Lgd ) so that ∆Lg = ∆Lgs +

∆Lgd and that the resulting physical gate length of the device

under process variation is Lg,pv = Lg,nom + ∆Lg . Symmet-

ric distribution (∆Lgs = ∆Lgd = ∆Lg /2), asymmetric dis-

tribution on the source side (∆Lgs = ∆Lg , ∆Lgd = 0), and

Fig. 4. Different components of gate leakage current as functions of gate

asymmetric distribution on the drain side (∆Lgs = 0, ∆Lgd =

voltage for fin widths of 3.6, 4, and 4.4 nm with a gate oxide thickness of ∆Lg ) have been examined. In this paper, the change in gate

1 nm at VDS = 0.8 V. length due to the process variation is simulated, assuming a

constant device length and fixed doping distribution and only

value (due to the increased uncertainty in the momentum). Note changing the relative position of gates.

that in OFF-state, electrons tunnel from gates to drain, whereas Table II summarizes the change in device performance due

in ON-state, electrons tunnel from source to gates. to the change in gate length and its relative position caused

The subthreshold swing in Table I is calculated at VDS = by process variation. As can be seen from simulation results,

0.8 V. It is important to mention that in calculating the sub- the device on-current varies over a range of approximately

threshold swing, we used the value of drain terminal current ±16% from its nominal value of 3584 µA/µm for a ±12%

(ID ) which consists of the drain-to-source current (IDS ) and variation in gate length, considering both the symmetrical and

the gate-to-drain leakage current (IGD ). Therefore, we evalu- asymmetrical distributions of ∆Lg . Overall, Table II shows

ated the subthreshold swing at the lowest part of the transfer that the on-current is primarily affected by the gate length

curve, where the gate-to-drain leakage is at the maximum (i.e., variation on the source side. A 12% reduction in gate length

for the lowest gate voltages). For the work-function adjusted asymmetrically distributed on the source side gives the smallest

device, the contribution of IGD is small, and the worst sub- on-current of 3053 µA/µm, whereas a gate length increase of

threshold swing value of 88 mV/dec is obtained for tSi = 12% asymmetrically distributed on the source side yields the

4.4 nm and tox = 1.2 nm due to the weakest control of gates largest on-current of 4276 µA/µm. On the other hand, the OFF-

over the channel for this combination. However, the inclusion state gate leakage is primarily affected by the variation of gate

of IGD into ID significantly changes the situation when poly- length on the drain side. The highest value of net gate leakage

Si gates are considered. In the case of poly-Si gates and when 16.75 nA/µm is obtained when the gate length is increased

the gate oxide thickness is reduced to 0.8 nm, IGD becomes by 12% on the drain side, and the lowest value of the gate

2138 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 55, NO. 8, AUGUST 2008

TABLE II

SIMULATION RESULTS DUE TO THE CHANGE IN PHYSICAL GATE LENGTH OF THE NOMINAL DEVICE Lg,nom BY ∆Lg CAUSED BY PROCESS VARIATION

TABLE III

SIMULATION RESULTS DUE TO THE CHANGE IN DOPING GRADIENT CAUSED BY PROCESS VARIATION

leakage 3.73 nA/µm corresponds to the gate length reduction C. Doping-Proﬁle Variation

by 12% on the drain side. The subthreshold source-to-drain

In this paper, a doping gradient of 2 nm/dec across the

leakage current is not sensitive to the symmetry of the gate

source/drain and the body has been adopted. We investigate

length variation; it is only affected by the resultant physical

the device performance due to the change in doping gradient

gate length. When it is larger than the nominal gate length,

on both the source and drain sides while keeping the total

it improves Isd,leak down to approximately 0.46 µA/µm, but

device length, the source/drain region lengths, and the underlap

when it is smaller than the nominal gate length, it degrades

region length constant. Simulations have been performed with

Isd,leak upto 1.28 µA/µm. DIBL follows the same trend

a 10% increase in the doping gradient across the source/drain

as Isd,leak .

and the body, which gives a doping gradient of 2.2 nm/dec.

When the gate length is reduced by ∆Lg , a part of the

Due to this variation, doping at the gate boundaries changes

channel becomes out of the direct gate control and, therefore,

to 5 × 1016 cm−3 from 1016 cm−3 for which the device charac-

introduces a lightly doped (highly resistive) region in series teristics is expected not to change significantly. Table III shows

with the channel, which may reduce the on-current. However, the performance matrices due to the change in doping profile

this addition of equivalent series resistance is only critical when caused by the process variation. The on-current increases for

added to the source side as it also reduces the overdrive voltage. all the cases but gains the highest increment by 10% for the

In this case, it increases the barrier height near the source end, source-side gradient increase. Similarly, any increase in doping

which reduces the on-current. If the additional series resistance gradient degrades Isd,leak , with the most significant degradation

is added to the drain side, it very slightly reduces the peak of the of 15% corresponding to the increment of doping gradient on

potential barrier due to the increased DIBL effect, and there- both sides. As expected, saturation threshold voltage is found

fore, the on-current somewhat increases, as shown in Table II. to be insensitive to the variation in doping gradient for the

In the case of increase in Lg,nom at the source side, the effective considered FinFET. As the entire body is very lightly doped,

gate-to-source underlap region decreases, thus improving the an increase in doping gradient by 10% does not effectively

injection rate of carriers into the channel. If the gate length is increase the charge inside the channel; therefore, the maximum

increased at the drain side, the injection rate remains the same, reduction in Vth,sat is only about 4% from its nominal value

and the on-current does not improve. of 140 mV.

KHAN et al.: SIMULATION OF THE IMPACT OF PROCESS VARIATION ON THE OPTIMIZED 10-nm FinFET 2139

TABLE IV

DEGRADATION OF THE OPTIMIZED FiNFET PERFORMANCE MATRICES DUE TO PROCESS VARIATION IN DIFFERENT DEVICE PARAMETERS. IN EACH

CELL, THE FIRST NUMBER CORRESPONDS TO THE AVERAGE DEGRADATION (0% MEANS NO SIGNIFICANT DEGRADATION ON AVERAGE).

THE SECOND NUMBER IN PARENTHESIS SHOWS THE WORST POSSIBLE DEGRADATION

III. SLOW CORNER ANALYSIS degradation. The highest value of subthreshold source-to-drain

leakage Isd,leak of 1.28 µA/µm has been obtained for the case

To verify whether the device can sustain its specified perfor- with Lg,pv = 8.8 nm, ∆Lgs = 0 nm, and ∆Lgd = −1.2 nm.

mance at the worst case operating condition, it is important to The corresponding value of Isd,leak at slow corner is found

evaluate the device performance at elevated temperatures and to be 5.06 µA/µm. The highest increase in Isd,leak due to

with reduced power supply voltage (“slow process corner”). the doping gradient variation across the source/drain and body

Usually, device performance is enhanced at low temperature has been found to be about 15% from its nominal value of

and increased power supply voltage (“fast process corner”); 0.75 µA/µm. The corresponding slow corner analysis gives

therefore, the “slow process corner” analysis is crucial to the a significant increase of approximately 200% in Isd,leak in

optimization of device performance. Generally, the definition this case.

of “slow process corner” may depend on the technology node Overall, it is evident from the simulation results that the

and the device application. In this paper, it is defined as a subthreshold source-to-drain leakage Isd,leak is the most sen-

combination of an operating temperature of 110◦ C and a 10% sitive parameter to the increase in temperature. Even for the

reduction in power supply voltage Vdd (0.72 V). The analysis nominal device, the slow corner analysis gives a five-time

has been performed with and without the process variation to increase in Isd,leak . Therefore, the slow corner analysis should

examine device behavior and to compare with “typical process be performed in the performance analysis of nanoscaled de-

corner” (an operating temperature of 27 ◦ C and a power supply vices, particularly for the devices with low leakage power

voltage of Vdd = 0.8 V). We first analyze the performance of requirements.

the FinFET due to the process variation in fin width, gate oxide

thickness, gate length, and doping profiles, and then, we define

maximum degradation in different performance matrices. After IV. CONCLUSION

that, the slow corner analysis has been performed for these spe-

cific cases so that the ultimate limits for different performance We have performed the process variation analysis in the

matrices can be defined. 10-nm gate length optimized FinFET structure, which ac-

The simulation shows that for the nominal device, the counted for the variations of fin width, gate oxide thickness,

on-current decreases by 15% in the “slow corner” case, whereas gate length and placement, and doping gradient. The essential

Isd,leak increases from its nominal value of 0.75 µA/µm to results of this analysis are summarized in Table IV. The average

a value of 3.58 µA/µm. Consequently, a significant degra- degradation is calculated from the algebraic mean value for

dation in subthreshold swing by approximately 30% is ob- different possible variations in each parameter (tSi and tox ,

served. As shown in the previous section, the worst value of Lg,nom , and doping gradient). If the average value is equal or

Isd,leak 2.06 µA/µm (in this case, it is approximately equal better than the nominal value, a 0% degradation is assumed.

to Ioﬀ ) has been obtained for tSi = 4.4 nm and tox = 1.2 nm. The “worst case” degradation corresponds to such variation

Slow corner analysis with tSi = 4.4 nm and tox = 1.2 nm in each parameter, which gives the highest possible level of

shows that Isd,leak increases to a value of 8.34 µA/µm. There- degradation.

fore, the worst case value of Ioﬀ , when considering both the The on-current (ION ) is most sensitive to the accurate

process variation and the slow process corner, is also approx- placement of the gates with respect to the source and drain

imately 8.34 µA/µm, which is significantly higher than the and to the variation in the gate length. Interestingly enough,

nominal value of 1 µA/µm. Regarding the gate length variation on average, there was no significant degradation in ION due to

due to the process variation, the lowest value of on-current the process variation within the limits considered here. Even

(3053 µA/µm) has been obtained when the nominal gate length the worst possible degradation in the on-current is within ac-

Lg,nom reduces by 12% (Lg,pv = 8.8 nm) and the change in ceptable limits. At the same time, the subthreshold source-to-

gate length ∆Lg is on the source side, i.e., ∆Lgs = −1.2 nm drain leakage current (Isd,leak ), on average, shows relatively

and ∆Lgd = 0 nm. For this case, the slow corner analysis yields strong sensitivity to all process variations considered, with the

device on-current of 2650 µA/µm, which is a further 13% worst degradation due to variations in fin width and oxide

2140 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 55, NO. 8, AUGUST 2008

thickness (tSi and tox ). Yet, Isd,leak remains, on average, within [12] S. Hasan, J. Wang, and M. Lundstrom, “Device design and manufacturing

20% of the nominal value, which still might be acceptable (un- issues for 10 nm-scale MOSFETs: A computational study,” Solid State

Electron., vol. 48, no. 6, pp. 867–875, Jun. 2004.

less the low leakage power requirements exist). However, the [13] Y. Taur, “Analytic solutions of charge and capacitance in symmetric

gate leakage IG has been found predictably to be the highest and asymmetric double-gate MOSFETs,” IEEE Trans. Electron Devices,

concern for such ultrascaled devices with SiO2 gate dielectric. vol. 48, no. 12, pp. 2861–2869, Dec. 2001.

[14] H.-S. P. Wong, D. J. Frank, and P. M. Solomon, “Device design con-

For a 20% variation in gate oxide thickness (that in worse case siderations for double-gate, ground-plane and single-gated ultra-thin SOI

corresponds to a reduction in gate oxide thickness by 2 Å) and MOSFETs at the 25 nm channel length generation,” in IEDM Tech. Dig.,

a 10% variation in fin thickness, the average degradation in the 1998, pp. 407–410.

[15] D. J. Frank, R. H. Dennard, E. Nowak, P. M. Solomon, Y. Taur, and

OFF-state gate leakage is about 200%. It is important to note H.-S. P. Wong, “Device scaling limits of Si MOSFETs and their applica-

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ACKNOWLEDGMENT

Hasanur R. Khan (S’06) was born in Dhaka,

The authors would like to thank Dr. S. Goodnick of the Bangladesh. He received the B.Sc. degree in elec-

Arizona State University for the encouragement and support of trical and electronic engineering (with honors) from

this paper through the Arizona Institute of Nano-Electronics. the Bangladesh University of Engineering and Tech-

nology (BUET), Dhaka, in 1999, and the M.S.E. and

Ph.D. degrees in electrical engineering with a major

R EFERENCES in solid-state electronics from the Arizona State Uni-

versity, Tempe, in 2002 and 2007, respectively.

[1] H. R. Khan, D. Mamaluy, and D. Vasileska, “Approaching optimal char- From 1999 to 2000, he was a Lecturer with the

acteristics of 10 nm high performance devices: A quantum transport Department of Electrical Engineering, BUET. He is

simulation study of Si FinFET,” IEEE Trans. Electron Devices, vol. 55, currently with the Department of Electrical Engi-

no. 3, pp. 743–753, Mar. 2008. neering, Arizona State University. His current research interests include simu-

[2] H. R. Khan, D. Mamaluy, and D. Vasileska, “Quantum transport simu- lation, analyses, and modeling of quantum effects in ultrascaled semiconductor

lation of experimentally fabricated nano-FinFET,” IEEE Trans. Electron devices with an emphasis on double- and trigate FinFET.

Devices, vol. 54, no. 4, pp. 784–796, Apr. 2007.

[3] D. Hisamoto, “FinFET—A self-aligned double-gate MOSFET scalable to

20 nm,” IEEE Trans. Electron Devices, vol. 47, no. 12, pp. 2320–2325,

Dec. 2000. Denis Mamaluy (M’05) was born in Kharkov,

[4] Y. Choi, T. King, and C. Hu, “Nanoscale CMOS spacer FinFET for U.S.S.R., in 1975. He received the M.S. degree in

the terabit era,” IEEE Electron Device Lett., vol. 23, no. 1, pp. 25–27, physics (with honors) from Kharkov State Univer-

Jan. 2002. sity, Kharkov, Ukraine, in 1997, the M.A. degree

[5] C. Hu, “The path of FinFET manufacturing,” Future Fab Int., vol. 23, in philosophy from the UNESCO Department,

Jul. 9, 2007. Kharkov University in 1997, and the Ph.D. degree

[6] S. Xiong and J. Bokor, “Sensitivity of double-gate and FinFET devices in physics and mathematics from B. Verkin Insti-

to process variations,” IEEE Trans. Electron Devices, vol. 50, no. 11, tute for Low Temperature Physics and Engineering,

pp. 2255–2261, Nov. 2003. Kharkov, in 2000.

[7] J. Shen, T. Y. Man, and M. Chan, “2D analysis of bottom gate mis- From 2000 to 2002, he was a Postdoctoral Fellow

alignment and process tolerant for sub-100 nm symmetric double-gate with the Walter Schottky Institute, Technische Uni-

MOSFETs,” in Proc. IEEE Electron Devices Solid-State Circuits, 2003, versität München, Munich, Germany. In 2003, he was a Faculty Research Asso-

pp. 201–204. ciate, and then, since 2006, a Research Assistant Professor with the Department

[8] B. C. Paul, S. Fujita, M. Okajima, T. H. Lee, H.-S. P. Wong, and of Electrical Engineering at Arizona State University, Tempe. He is one of the

Y. Nishi, “Impact of a process variation on nanowire and nanotube device authors of the Contact Block Reduction (CBR) Method for Efficient Quantum

performance,” IEEE Trans. Electron Devices, vol. 54, no. 9, pp. 2369– Transport Modeling in Open Nano-Systems: D. Mamaluy et al., J. App. Phys.

2376, Sep. 2007. 93, 4628 (2003) and D. Mamaluy et al., Phys. Rev. B 71, 245321 (2005). He

[9] M. M. Chowdhury, V. P. Trivedi, J. G. Fossum, and L. Mathew, “Carrier has published about 30 peer-reviewed journal papers, contributed to more than

mobility/transport in undoped-UTB DG FinFETs,” IEEE Trans. Electron 40 conference papers and presentations, and given a number of invited talks

Devices, vol. 54, no. 5, pp. 1125–1131, May 2007. on quantum transport simulation for industries and academia. His past research

[10] S. Jin, Y. J. Park, and H. S. Min, “A three-dimensional simula- interests included theory and applications of surface electromagnetic waves,

tion of quantum transport in silicon nanowire transistor in the pres- which are induced by magnetoelectric interaction. His current research interests

ence of electron–phonon interactions,” J. Appl. Phys., vol. 99, no. 12, include quantum transport in nanostructures, nanodevices, and semiconductor

pp. 123 719-1–123 719, 2006. device computer modeling.

[11] H. Khan, D. Mamaluy, and D. Vasileska, “Influence of interface roughness Dr. Mamaluy was the recipient of the Best Poster Presentation Award at

on quantum transport in nanoscale FinFET,” J. Vac. Sci. Technol. B, the 7th International Conference on Complex Media (Bianisotropics 1998),

Microelectron. Process. Phenom., vol. 25, no. 4, pp. 1437–1440, 2007. Braunschweig, Germany.

KHAN et al.: SIMULATION OF THE IMPACT OF PROCESS VARIATION ON THE OPTIMIZED 10-nm FinFET 2141

B.S.E.E. (Diploma) and M.S.E.E. degrees from

the University Sts. Cyril and Methodius, Skopje,

Macedonia, in 1985 and 1992, respectively, and the

Ph.D. degree from the Arizona State University,

Tempe, in 1995.

From 1995 to 1997, she was a Faculty Research

Associate with the Center of Solid State Electronics

Research, Arizona State University. Since the fall of

1997, she has been with the Department of Electrical

Engineering, Arizona State University, where she has

been a Full Professor since 2007. She is the author or coauthor of more than 100

journal publications and over 80 refereed papers in conference proceedings. She

has given numerous invited talks and is a coauthor of a book on computational

electronics. Her research interests include semiconductor device physics and

semiconductor device modeling, with strong emphasis on quantum transport

and Monte Carlo particle-based simulations.

Dr. Vasileska is a Senior Member of the American Physical Society. She was

the recipient of the 1998 National Science Foundation Career Award.

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