Qucs

A Report
Verilog-A compact device models for GaAs MESFETs

Mike Brinson

Copyright
c 2008 Mike Brinson <mbrin72043@yahoo.co.uk>

Permission is granted to copy, distribute and/or modify this document under the
terms of the GNU Free Documentation License, Version 1.1 or any later version
published by the Free Software Foundation. A copy of the license is included in
the section entitled ”GNU Free Documentation License”.
Introduction
A previous Qucs Report1 described a MESFET model based on an equation defined
device (EDD) representation of the level 1 Curtice model. This model evolved as
a test example during the initial Qucs EDD development phase. Today the EDD
model is popular amongst Qucs users as either a powerful non-linear component in
it’s own right or as the basis of a component prototyping system for constructing
compact Verilog-A device models, translated with ADMS to C++ code, compiled
to object code and finally linked to the main body of the Qucs program code.
Over the last year the Qucs development team has invested a significant amount
of time improving both EDD prototyping and Verilog-A compact device/circuit
model development, making the development process more transparent to anyone
interested in trying their hand at model construction. One branch of the current
Qucs modelling activities is concentrating on adding new models which fill in some
of the gaps in the Qucs released model lists. One such model in this category is
the GaAs MESFET. This report outlines the background and mathematical basis
for a number of MESFET models. These have been coded in Verilog-A and tested
using recent Qucs CVS code. They will be included in the next full release of Qucs.

The GaAs MESFET

The metal-semiconductor FET (MESFET) is a Schottky-barrier gate FET which
is normally made from Gallium Arsenide. It is a popular device for high frequency
applications because of it’s high electron mobility and usable gain at microwave
frequencies. An early simulation model for the MESFET device was developed
by Walter R. Curtice2 in 1980 at the RCA Laboratory in Princeton, New Jersey,
USA. Since Curtice published his original MEFET model a number of authors
have contributed improvements to the basic model, including for example Statz
et. al. (Raytheon)3 and TriQuint Semiconductor Inc.4 . These models form the
basis of the Qucs MESFET model described in this report.
1
M. Brinson and S. Jahn, Qucs: Compact device- circuit macromodel specification; A Curtice
level 1 MESFET model, http://qucs.sourceforge.net/docs.html
2
W.R. Curtice, 1980, A MESFET model for use in the design of GaAs integrated circuits,
IEEE Transactions on Microwave Theory and Techniques, MTT-28, pp. 448-456.
3
H. Statz, P. Newman, I.W. Smith, R.A. Pucel, and H.A. Haus, gaAs FET Device and Circuit
Simulation in SPICE, IEEE Transactions on Electron Devices, Vol. 34, pp. 160-169, Feb. 1987.
4
For example, D.H. Smith, TOM-2: An improved Model for GaAs MESFETs, TriQuint
Report, TriQuint Semiconductor, Inc Fe. 27, 1995 (11 pages).

1
The Qucs MESFET model
Parameters
Name Symbol Description Unit Default
LEVEL model selector 1
Vto Vto gate threshold voltage V −1.8
Beta β transconductance parameter A/V2 3m
Alpha α coefficient of Vds in tanh function 1/V 2.25
Gamma γ dc drain pull coefficient 0.015
Lambda λ channel length modulation parameter 1/V 0.05
B B doping profile parameter 1/V 0
Qp Qp power law exponent parameter 2.1
Delta δ power feedback parameter 1/W 0.1
Vmax V max maximum junction voltage be- V 0.5
fore cap. limiting
Vdelta1 V delta1 capacitance saturation transi- V 0.3
tion voltage
Vdelta2 V delta2 capacitance threshold transi- V 0.2
tion voltage
Nsc N sc subthreshold conductance parameter 1
Is IS diode saturation current A 10f
N N diode emission coefficient 1
Vbi V bi built-in gate potential V 1.0
Bv Bv diode breakdown voltage V 60
XTI XT I diode saturation current tem- 0
perature coefficient
TAU τ internal time delay from drain s 10p
to source
Rin Rin series resistance to Cgs Ω 1m
Fc F c forward-bias depletion capaci- 0.5
tance coefficient
Area Area area factor 1
Eg Eg bandgap voltage V 1.11
M M grading coefficient 0.5
Cgs Cgs zero-bias gate-source capacitance F 0.2p
Cgd Cgd zero-bias gate-drain capacitance F 1p
Cds Cds zero-bias drain-source capacitance F 1p
Betatc Betatc Beta temperature coefficient %/C 0
Alphatc Alphatc Alpha temperature coefficient %/C 0
Gammatc Gammatc Gamma temperature coefficient %/C 0
Ng Ng subthreshold slope gate parameter 2.65
Nd Nd subthreshold drain pull parameter −0.19

2
 Name Symbol Description Unit Default
ILEVELS ILEV ELS gate-source current equation selector 3
ILEVELD ILEV ELD drain-source current equation selector 3
QLEVELS QLEV ELS gate-source charge equation selector 2
QLEVELD QLEV ELS gate-source charge equation selector 2
QLEVELDS QLEV ELDS drain-source charge equation selector 2
Vtotc V totc Vto temperature coefficient V/C 0
Rg Rg gate series resistance Ω 5.1
Rd Rd drain series resistance Ω 1.3
Rs Rs source series resistance Ω 1.3
Rgtc Rgtc gate series resistance tempera- 1/C 0
ture coefficient
Rdtc Rdtc drain series resistance temper- 1/C 0
ature coefficient
Rstc Rstc source series resistance tem- 1/C 0
perature coefficient
Ibv Ibv gate reverse breakdown current A 1m
Rf Rf forward bias slope resistance Ω 10
R1 R1 breakdown slope resistance Ω 10
Af Af Flicker noise exponent 1.0
Kf Kf flicker noise coefficient 0.0
Gdsnoi Gdnsnoi shot noise coefficient 1.0
◦
Tnom T nom device parameter measure- C 26.85
ment temperature
◦
Temp T emp device circuit temperature C 26.85

Where parameter LEVEL selects a MESFET model listed in Table 2.

LEVEL MESFET model type

1 Quadratic Curtice - basic form
2 Quadratic Curtice - basic plus subthreshold properties
3 Statz et. al. (Raytheon) - same as SPICE 3f5
4 TriQuint - TOM 1 model
5 TriQuint - TOM 2 model
Table 2: Qucs MESFET model types

MESFET gate current equations can be selected by setting parameters ILEVELS

and ILEVELD. Table 3 lists the available options.
MESFET charge equations can be selected by setting parameters QLEVELS,
QLEVELD and QLEVELDS. Table 4 lists the available options. Although it

3
 ILEVELS - ILEVELD Gate-source current Gate-drain current
0 Igs=0 Igd=0
1 Linear no reverse breakdown Linear no reverse breakdown
2 Linear with reverse breakdown Linear with reverse breakdown
3 Diode no reverse breakdown Diode no reverse breakdown
4 Diode with reverse breakdown Diode with reverse breakdown
Table 3: Qucs MESFET gate current model types

is possible to mix the five basic MESFET models with different gate current and
charge equation models the common default models are the ones listed in Table 5.

QLEVELS QLEVELD QLEVELDS

0 Qgs=0 0 Qgd=0 0 Qds=0
1 Constant cap. 1 Constant cap. 1 Constant cap.
2 Diode 2 Diode 2 Constant cap.+ transit
3 Statz 3 Statz
Table 4: Qucs MESFET charge equation types

Model LEVEL ILEVELS ILEVELD QLEVELS QLEVELD QLEVELDS

Curtice L1 1 0 to 4 0 to 4 0 to 2 0 to 2 0 to 2
Curtice (Adv.) 2 0 to 4 0 to 4 0 to 2 0 to 2 0 to 2
Statz-Raytheon 3 4 4 3 3 2
TOM 1 4 4 4 3 3 2
TOM 2 5 4 4 3 3 2
Table 5: Qucs MESET default selection parameters

The Qucs MESFET simulation model

The large signal equivalent circuit for the Qucs MESFET model is illustrated in
Fig. 1. The currents flowing in each of the circuit branches are given by the Verilog-
A code fragment shown in Fig. 1. The Verilog-A HDL code for the entire Qucs
MESFET model is available from the Qucs CVS archive5 . In order to simulate
5
http://qucs.sourceforge.net/

4
the operation of an MESFET, equations based on the physical operation of the
device are required for all the current contribution components in Fig. 1. These
equations are presented in the remaining sections of this report. Examples are also
introduced to demonstrate the simulation performance of each model.

MESFET gate current equations

• ILEVELS = 0: Igs = 0 A

• ILEVELS = 1: if (V (b1) > V bi)

V (b1) − V bi
Igs = (1)
Rf
else Igs = −Area · Is + GM IN · V (b1)

• ILEVELS = 2: if (V (b1) > V bi)

V (b1) − V bi
Igs1 = (2)
Rf
else Igs1 = −Area · Is + GM IN · V (b1)
if V (b1) < −Bv)
V (b1) − V bi
Igs2 = (3)
R1
Igs = Igs1 + Igs2 (4)

• ILEVELS = 3: if (V (b1) > V bi)

   
V (b1)
Igs = Is T 2 · limexp − 1.0 + GM IN · V (b1) (5)
N ·V t T2

else Igs = −Is T 2 + GM IN · V (b1)

• ILEVELS = 4: if (V (b1) > −5 · N · V t T 2)

   
V (b1)
Igs1 = Area · Is T 2 · limexp − 1.0 + GM IN · V (b1) (6)
N ·V t T2
else Igs1 = 0
if ((−Bv < V (b1)) and (V (b1) < −5 · N · V t T 2))

Igs2 = −Area · Is T 2 + GM IN · V (b1) (7)

5
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else Igs2 = 0
if (V (b1) == −Bv)
Igs3 = −Ibv (8)
else Igs3 = 0
if (V (b1) < −Bv)
   
−(Bv + V (b1)) Bv
Igs4 = −Area · Is T 2 · limexp − 1.0 + (9)
V t T2 V t T2

else Igs4 = 0
Igs = Igs1 + Igs2 + Igs3 + Igs4 (10)

Where xx T2 indicates the values of temperature dependent parameters at circuit

temperature T2. See later sections of this report for more details. The gate to
drain current equations are identical except Igs is replaced by Igd, Igsx by Igdx,
and V(b1) by V(b2). More details can be found in the Verilog-A listing given in
the Qucs CVS code held at the Qucs Sourceforge site.

MESFET charge equations QLEVELS 0 to 2

• QLEVELS = 0: [NO charge]:

6
 Qgs = 0 (11)

• QLEVELS = 1: [Fixed capacitor charge]

Qgs = Area · Cgs · V (b4) (12)

• QLEVELS = 2: [Diode charge]

if (V (b4) < (F c · V bi))
(  1−M )
Cgs T 2 · V bi T 2 V (b4)
Qgs1 = · 1− 1− (13)
(1 − M ) V bi T 2

if (V (b4) >= (F c · V bi))

M
H1 = · (V (b4) · V (b4) − (F c · F c · V bi T 2 · V bi T 2)) (14)
2 · V bi T 2
 
1
Qgs2 = Cgs T 2 · F 1 + · {F 3 · (V (b4) − F c · V bi T 2) + H1} (15)
F2
Where,
V bi T 2 n o
F1 = · 1 − (1 − F c)1−M , (16)
1−M
F 2 = (1 − F c)1+M , (17)

and

F 3 = 1 − F c · (1 + M ) . (18)

Again xx T2 indicates the values of temperature dependent parameters at circuit

temperature T2. See a later section of this report for more details. The gate to
drain charge equations (types 0 to 2) are identical except Qgs is replaced by Qgd,
Qgsx by Qgdx, and V(b4) by V(b6). More details can be found in the Qucs CVS
code held at the Qucs Sourceforge site.

MESFET charge equations QLEVELDS 0 to 2

• QLEVELDS = 0: [NO charge]:

Qds = 0 (19)

7
 • QLEVELDS = 1: [Fixed capacitor charge]

Qds = Area · Cds · V (b3) (20)

• QLEVELS = 2: [Fixed capacitor plus transit charge]

Qds = Area · Cds · V (b3) + T au · Ids (21)

Curtice hyperbolic tangent model: LEVEL = 1

if (V (b1) − V to T 2) > 0

Ids = Beta T 2 · (V (b1) − V to T 2)2 · {1 + Lambda · V (b3)} · tanh(Alpha · V (b3))

(22)
else Ids = 0.

8
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9
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10
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11
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12
Curtice hyperbolic tangent model with subthresh-
old modification: LEVEL = 2
Ids = Beta T 2 · V f 2 · {1 + Lambda · V (b3)} · tanh(Alpha · V (b3)) (23)
Where
1
Vf = · ln {1 + exp (Ah · (V (b1) − V to T 2))} (24)
Ah
and
1
Ah = (25)
2 · N sc · V t T 2
When V (b2) > V to T 2, V f =⇒ V (b2) − V to T 2. Otherwise, V f approaches zero
asymptotically. This modification to the basic Curtice model provides an improved
match to channel gradual pinch-off and MESFET subthreshold conduction.

13
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subthreshold conduction modification

14
Statz et. al. (Raytheon) model: LEVEL = 3
if (V (b1) − V to T 2) > 0
3
if (0 < V (b3)) and (V (b3) < )
Alpha
begin  3
Alpha · V (b3)
1− 1−
3
H1 = (26)
1 + B · (V (b1) − V to T 2)
Ids = Beta T 2 · {1 + Lambda · V (b3)} · (V (b1) − V to T 2)2 · H1 (27)
end
3
if (V (b3) > )
Alpha
Beta T 2 · {1 + Lambda · V (b3)} · (V (b1) − V to T 2)2
Ids = (28)
1 + B · (V (b1) − V to T 2)
else Ids = 0.

MESFET charge equations QLEVELS = 3 and QLEVELD

=3
QLEVELS = 3 : Statz et. al. charge equations

V max = min(F c · V bi, V max) (29)

n p o
V ef f 1 = 0.5 · V (b4) + V (b6) + (V (b6) − V (b4))2 + V delta12 (30)
n p o
V new = 0.5 · V ef f 1 + V to T 2 + (V ef f 1 − V to T 2)2 + V delta22 (31)

if (V new > V max)

 

 r ! 

 V max V new − V max 
Qgs = Cgs T 2 · 2 · V bi T 2 1 − 1− + r (32)
 V bi T 2 V max 
1−

 

V bi T 2
if (V new <= V max)
( r )
V new
Qgs = Cgs T 2 · 2 · V bi T 2 · 1− 1− (33)
V bi T 2

15
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Figure 7: Statz et. al. LEVEL 3 DC test circuit and Ids-Vds characteristics

QLEVELD = 3 : Statz et. al. charge equations

n p o
V ef f 2 = 0.5 · V (b4) + V (b6) − (V (b4) − V (b6))2 + V delta12 (34)

Qds = Cgd T 2 · V ef f 2 (35)

During simulation gate charge must be partitioned between gate-source and gate-
drain branches. The Qucs implementation of the Statz et. al. MESFET model
uses the procedure adopted by Divehar 6 .

6
D. Divehar, Comments on GaAs FET device and circuit simulation in SPICE,IEEE Trans-
actions on Electronic Devices, Vol. ED-34, pp 2564-2565, Dec. 1987

16
 Id
s
E
F
M
SE
T
1 V2
d
s
=
V
U1
g
sV
=
V E
L
V
L
1
t
o
=
$
3
e
a
B
l
h
p3
=
8
.
3
e
$
2
2
5
=
. U
V
a
Pr
a
m
et
e
rPar
a
m
et
e
r A
b
d
a
m
L
9
1
e
=
$
B
m
a
x
=
V
C
d
g0
a
=
0
5
.
2
e
$0
5
.
2
1
w
s
W
S
i
me
p
1
W
=
S2w
s
W
S
ime
p
2
D
C
1
= 1
s
=
C
d
5
g
=
.
R
d
3
12
1
e
$
1
T
p
y
a
r
P
t
S
ol
i
e
n
a
m
=
V
1
t
p
=d
sT
y
a
P
t
Sp
r
ol
i
e
n
a
m
=
V
3
t
$
0
p
=g
s s
=
.
R c
d
D
Ci
m
s
1l
i
t
a
uo
n
in
P6P
t
s
= in
4
t
s
=100
1
.
0
)
A
(0
1
. )
A
(3
1
e
$
4
1
5
e
$
6
s
d
I0 I1 s
d1
7
e
$
8
9
1
e
$
0
1
3
$2
$.52
$
$
g
V1
5
.
(
)
s1
$$
V V0
5
.0 e
$
$32
5
$
.2
$1
5
$
.
(
g
s
V1
$
)0
5
$
.0
Figure 8: Statz et. al. LEVEL 3 DC test circuit and Ids-Vgs characteristics

17
 Id
s
E
M
SF
E
T1V2
5
=
V
U1
=g
s
V IgV L
V
t
o
=
e
a
B
l
h
pE
3
=
L
8
1
'
.
3
e
'
2
=
.3
2
5 U
a
r
a
P t
m
ee
r a
r
Pa
m
et
e
r A
a
m
L
1
=
B
m
a
V
C
d
gb
d
a
=
9
e
'
0
x
=
.
2
e0
0
5
.
5
2
1
'
e
w
s
W
1
S
i
m
=Dp
C
1 e
w
s
W
2
S
i
mp
W
1
=
S s
C
d
I
E
L
V1
1
e
=
'
E
L
S
D2
3
= il
i
t
p
e
y
T
a
r
a
P
t
t
S
o
pm
=l
i
n
g
=
V
0
6
.
1s p
e
y
T
a
r
a
P
t
S
o
pl
i
n
m
e
=
T
0
1
t
'
=m
p g
=
R
d
s
=
R5
1
.
3
1
. c
d
s
D
C
1m
uao
n
01
.i
n
Pt
s2
1
= i
n
P6
t
s
= e
m
Tp
e
=
Tm
p
)
A1
e
'
1
e
'3
4
5
(
Ig
1
e
'6
7
8
1
e
'
1
1
e9
0
'0
.6
0.6
50
.70
.7
5
V0
8
.
(
g
s
V 0
8
.
)50
9
.0
9
.51
Figure 9: Statz et. al. LEVEL 3 DC test circuit and Ig-Vgs characteristics

18
 dD iw
li1am
csSPC
sW P
N
Z
tr1em
m1
u 5m u0 =
O
a1
h
mX
11
V
0
=
U
M
ip1etronALt E
oV S F
< E
L
.T
=
8 1
3 X
2
2
V
=
U
Sd
s
parmt
e2
P
m
u
N
0
5
Z
r2
=
O
h
m
V
CB
Le
d l
g
d pm
e
s a
h=b
t a
1d
1e
2
2 0
=
e
<5
.32s
T
S
Pi
m
1
P
p
e
y
t
a
r
o
i
n u
=
sl
g
k
G
0
3
5i
o
n
H
z
1
TSPytaoprine==Ss25lPi0n6VdsQ LgdsLE=EV5V.31LLSD
IR =S3=2
][S1,1.26frequncy][S2,1.3frequncy
]S[21,frequnc0y.50.10.15]S 2[1, frequn2cy468
Figure 10: Statz et. al. LEVEL 3 S parameter test circuit and characteristics
19
TriQuint Semiconductor TOM 1 model: LEVEL
=4
if (V (b1) − V to T 2) > 0
3
if (0 < V (b3)) and (V (b3) < )
Alpha
begin
(  3 )
n
Qp
o Alpha · V (b3)
Ids1 = Beta T 2 · (V (b1) − V to T 2) · 1− 1− (36)
3

Ids1 · {1 + Lambda · V (b3)}

Ids = (37)
1 + Delta · V (b3) · Ids1
end
3
if (V (b3) > )
Alpha

Ids1 = Beta T 2 · (V (b1) − V to T 2)Qp (38)

Ids1 · {1 + Lambda · V (b3)}

Ids = (39)
1 + Delta · (V (b3) · Ids1
else Ids = 0.

20
 Id
s
E
F
M
SE
T
1 2
V
=d
sc
s
di
mul
i
t
a
on
1
V
=
Ug
sV
V E
L
V
L
1
t
o
=
+
e
a
B
l
h
p4
=
8
.
3
3
e
+
2
2
=
.5 U
V C
1
D
A
b
d
a
m
L
1
e
=
+
B
2
p
.
Q
l
t
e
a
=0
a
=
9
0
10
5
.P
sa
r
a
e
wt
m
e
pe
r P
s
wa
r
a
m
ee
pt
e
r
)
A
(0
0
1
. D
m
x
V
d
l
t
e
a
V
a
m
m.
0
5
0
1
=
2
0
a3
.
2
0
1
5S
TW
1
i
m
=
D
p
e
yC
1
l
i
n W
S
i
T
y2
m
=
S
l
p
eW
1
i
n
Is
d0 G
C
d
0
g
=
1
s
C
d
=
E
Q
L
V
=
2
e
+
.
2
1
e
+
E
L
S
.
2
1
3
=P
S
Pa
r
a
m
t
t
o
p
=
i
t
n
sd
=
V
0
1
0
1
=s
1 a
P
t
S
Pr
a
m
t
+
0
o
p
=
i
t
n
sg
=
V
5
2
1
=s
0 24
d
Vs)8
6
(
V 105
g
=
.
R
d
1
s
=
.
RD
1
3
d
D
Ci
c
m
s
1ul
ai
t
o
n I
d
s
E
MF
SE
T
1 V2
d
=s
E4 UV
Figure 11: TOM1 LEVEL 4 DC test circuit and Ids-Vds characteristics

V
U1
g
sV
=
V L
t
e
B
l
AV
L
1
o
=
$
3
a
h
p
==
8
.
3
e
$
2
2
5
.
a
P
wr
a
m
e
e
pte
ra
P
w r
a
et
m
e
p a
L
=
B
p
e
r
Q
D
eb
d
m
9
1
e
$
2
0
.
l
t
a
=0
a
=
.
1
.0
5
s
W
S
i
m
T
p
y1
W
=
S
l
i
e
n2 s
W
S
i
m
T
yp2
=
eD
C
1
l
i
n m
V
d
V
a
Gx
l
t
e
a
m
m0
5
0
3
1
=
.
2
2
0
a
=
.0
1
5
a
r
P
t
S
oa
m
=
V
1
t
p
=
ind
6P
t
s sa
P
t
Sr
oa
m
t
p
=
in
tg
=
V
3
$
0
4
1
ssC
g
C
d
Q
Ld
0
=
1
s
=
E
E
V2
1
e
$
.
2
1
e
$
=
L
S2
3
P= = g
R
d
s5
1
=
.
3
1
=
.D
0
0
.
1
e1
3
)
A
(0
0
1
.
s R)
A
(
s1
e$
4
5
$
6
d
I0 d1
e
I1
1
e
17
$
8
9
$
0
3
$2
$.52
$
$
g
V1
.5
s 1
)$
(
V $00$
.5 e
$32
.5
$$2
$
g
V1
.5
s 1
)$
(
V 00
.5
$
Figure 12: TOM1 LEVEL 4 DC test circuit and Ids-Vgs characteristics

21
 Id
sV 2 E
M
S
E
L
V
t
o
=
V
e
a
BF
E
T
4
=
L
8
1
'
.
3
e
'1
3
V
U1
=g
s
V I
g 5
=
U l
h
p
A
a
m
L
1
e
=
B
2
p
Q2
=
.
b
d
a
=
9
'
0
.2
5
0
0
5
.
a
r
a t
m
ee
rara
m
et
e
r il
i
t D
l
t
e
a
m
V
d
l
e
V1
=
.
0
x
1
t
a
=
25
0
3
.
2
P
e
w
s
W
1
S
i
mDp
C
1 P
w
s
W
S
ie
2
mp
W
1 d
Dc
s
C
1m
uao
n a
m
G
C
d
g
=
s
C
d
=m
a
=
0
2
e
.
1
1
e
'0
0
1
5
.
2
1
'
2
=
p
e
y
T
a
r
a
P
t
t
Sm
=l
i
n
g
=
V
0
6
.
1sy
T
a
P
t
Sp
e
r
a=
S
l
i
n
m
e
=
T
0
1
t
'm
p I
E
L
V
E
Q
LE
L
S
D
E
V
L
S3
=
2
=
D
3
01o
p
i
n
Pt
s2
1
= Po
p
i
n=
6
t
s
= 5
g
=
R
d
1
s
=
R
e
m1
.
3
.
p
em
p
1
e
'.
3 T=
T
)
A
(1
e
'4
5
6
Ig
1
e
'
1
e
'7
8
9
1
1
e0
'0
.6
0.6
50
.70
.7
50
8
.
(
g
s 0
8
.
)50
9
.09
5
.1
VV
Figure 13: TOM1 LEVEL 4 DC test circuit and Ig-Vgs characteristics

22
 dD iw
li1am
csSPC
sW P
N
Z 1
u
tr1em
m 5m 0 =
O1hm X
ip1etron TS
u a 1
1
V
0
=
U X
2
2
V
=
Ud
s
p
a
rm
e2
P
m
u
N
5
Z
t
r=
02
O
h M
m
A
Q
VL
B
L
Dt
e
e l E
o
pV
m=S
a
h
taF
=
b
x.L
3
dE
1.T
=
8
e
2 1
4
0
=
55
= S P i
s
P
y
t
S
Pl
m
u
1
p
e
=
a
r
o
i
n
si
o
g
k
H
z
G
0
3
5
1n G
N
C
N d a
s
g
d m
c
d
= l
=
2
0 1
06 2
a
.5 0
=
e
=
2.3
215
TSPytaoprine=s25li0n6Vds Q LgdsLE=EV5V.31LLSD
IR =S3=2
][S1, frequncy ][S2, requncy
]S[21, 0.50.10.15][S21, 0.50.10.15 f
frequncy frequncy
Figure 14: TOM1 LEVEL 4 S parameter test circuit and characteristics

23
TriQuint Semiconductor TOM 2 model: LEVEL
=5
if (V (b1) − V to T 2) > 0
begin
N st = N g + N d · V (b3) (40)
if (N st < 1.0)N st = 1.0

V st = N st · V t T 2 (41)
   
V (b1) − V to T 2 + Gamma T 2 · V (b3)
V g = Qp · V st · ln exp +1 (42)
Qp · V st
Al = Alpha T 2 · V (b3) (43)
Al
Fd = √ (44)
1 + Al · Al
Ids1 = Beta T 2 · V g Qp · F d (45)
1 + Lambda · V (b3)
Ids = Ids1 · (46)
1 + Delta · V (b3) · Ids1
end
else Ids = 0

24
 Id
s
E
F
M
SE
T
1 2
V
d
=sc
s
di
m
ul
i
t
ao
n
1
V
g
sV
=
U
V E
L
V
L
1
t
o
=
+
e
a
B
l
h
p5
=
8
.
3
3
e
+
2
2
5
=
. U
V C
1
D
0
0
2
. A
b
d
a
m
L
9
1
e
=
+
B
2
p
.
Q
l
t
e
a
=0
a
=
0
10
5
.P
sa
r
a
e
wt
m
e
pe
rP
sa
r
a
e
wt
m
e
pe
r
)
A
(0
0
1
. D
m
x
V
d
l
t
e
a
V
a
m
m.
0
5
0
1
=
.
2
0
a3
2
0
1
5S
TW
1
i
m
=
D
p
e
yC
1
l
i
n S
T
yW
2
i
m
=
S
p
eW
1
l
i
n
Is
d0 G
C
d
0
g
=
1
s
C
d
=
2
g
.
N
d
1
=
2
e
+
.
2
1
e
+
6
5
9
1
.
2
1P
S
Pa
r
a
m
t
t
o
p
=
i
t
n
sd
=
V
0
1
0
1
=s
1P
S
Pa
r
a
m
t
t
o
p
=
i
t
n
sg
=
V
5
+
0
2
1
=s
0 2
4
V6
d
(
s
V8
)Q0
1=
+
E
L
V
5
g
=
.
Re
+
E
=
L
S
D
13
d
1
s
=
.
R3
Figure 15: TOM2 LEVEL 5 DC test circuit and Ids-Vds characteristics

25
 ci
ml
t
a
ui
o
n I
d
s E
F
M
S
E
L
V
t
o
=
+
V
e
a
BE
T
1
5
=
L
8
1
.
3
3
e
+
d
s
C
1
D 1
V
=
Ug
s
V 2
V
=
Ud
s
Vl
h
p
A
b
a
m
L
1
e
=
B
2
p2
2
=
.
d
0
a
=
9
+
0
.5
0
5
.
Q
l
t
e
a
D
m
x
V
d
l
t
e1
=
.
0
5
0
1
a
=
23
.
2
a
r
a
P
e
w
s
W
1t
m
e
pe
r a
r
a
P
e
w
s
W
2t
m
e
pe
r V
a
m
m
G
C
d
g
=
s
C
d
=0
a
=
0
2
e
.
1
1
e
+0
1
5
.
2
1
+
2
S
i
m
=
S
T
p
e
y
a
r
a
m
P
t
tW
2
l
i
n
d
=
V
1s S
i
m
=
D
T
p
e
y
a
r
a
m
P
t
tC
1
l
i
n
g
=
V
3
+s 1
g
N
d
0
=
+
E
Q
L
V9
1
.
E
L
S3
=
00
2 S
o
p
=
i
t
n
s
P6
= S
o
p
=
i
t
n
s
P0
4
1
= 5
g
=
R
d
1
s
=
RD
1
.
3
.
)
A. 0
1
1
)
A0
1
.
3
e
+
4
5
e
+
0
(
s
d0
1
.
I0 I1 (
s
1
d
16
7
e
+
8
9
e
+
3
+2
+ 2
.5
+1
+
g
s
V5
.
(
)1
+0
5
+
.
V V0e0
1
+
3
++2
5
.2
+1
5
+
.
(
)
g
s
V1
+0
5
+
.0
Figure 16: TOM2 LEVEL 5 DC test circuit and Ids-Vgs characteristics

26
 Id
sV 2 E
M
S
E
L
V
t
o
=
V
e
a
BF
E
T
5
=
L
8
1
'
.
3
e
'1
3
V
U1
=g
s
V I
g 5
=
U l
h
p
A
a
m
L
1
e
=
B
2
p
Q2
=
.
b
d
a
=
9
'
1
.2
5
0
0
5
.
a
r
a t
m
ee
rara
m
et
e
r il
i
t D
l
t
e
a
m
V
d
l
e
V0
1
=
.
x
1
t
a
=
25
0
3
.
2
P
e
w
s
W
1
S
i
mDp
C
1 P
w
s
W
S
ie
2
mp
W
1 d
Dc
s
C
1m
uao
n a
m
G
C
d
g
=
s
C
d
=m
a
=
0
2
e
.
1
1
e
'0
0
1
5
.
2
1
'
2
=
p
e
y
T
a
r
a
P
t
t
Sm
=l
i
n
g
=
V
0
6
.
1sy
T
a
P
t
Sp
e
r
a=
S
l
i
n
m
e
=
T
0
1
t
'm
p 2
g
N
d
=
'
I
E
L
V6
5
.
0
9
1
E
L
S
D3
=
01o
p
i
n
Pt
s2
1
= Po
p
i
n=
6
t
s
= E
Q
L
5
g
=
R
d
1E
V
L
S
1
.
32
=
D
3
1
e
'.
3
4 s
=
R
e
m
T.
p
e
=
Tm
p
)
A
(1
e
'
Ig
1
e
'5
6
7
1
e
'
18
9
0
1
e
'0
.6
0.6
50
.70
.7
5
V0
8
.
(
g
s
V 0
8
.
)50
9
.09
5
.1
Figure 17: TOM2 LEVEL 5 DC test circuit and Ig-Vgs characteristics

27
 cdD P
N
Z
iW
lw
ssSPCir1em
ti1am 1
mu 5m u0 =
O1
ahmoX
n 1
1
V
0
=
U X
2
2
V
=
U
S dp s
a r mZ
t
e2
P
m
u
N
0
5
r2
=
O
h
mM
L
t
e
B
l
A
L
Q
e
D
V E
o
pV
mS
a
h
=
taF
<
b
x.L
3
dE
.1
T
5
=
8
e
2
=
10 5
i
s
P m1 u l i
o
n
tTSPytaopre==S25lPi0nV1dsr TSPytaopirne=s03kg5G
p e H
z
1 d
G
a
s
N
C
g
N
d m
c
d
= l
=
2
0 1
062
a
.=
e
50
3
.
2
<
215
ins6 R I
L
Q E V LS
D3
=
Lds=E5V.31LS=2
g
][S1, frequncy ][S2, requncy
]S[21, 0.50.10.15][S21, 0.50.10.15 f
frequncy frequncy
Figure 18: TOM2 LEVEL 5 S parameter test circuit and characteristics

28
Temperature scaling relations
T1=Tnom+273.15;
T2=Temp+273.15;
Tr=T2/T1;
con1=pow(Tr, 1.5);
Rg_T2=Rg*(1+Rgtc*(T2-T1));
Rd_T2=Rd*(1+Rdtc*(T2-T1));
Rs_T2=Rs*(1+Rstc*(T2-T1));
Beta_T2=Area*Beta*pow(1.01, Betatc*(T2-T1));
Vt_T2=$vt;
Eg_T1=Eg-7.02e-4*T1*T1/(1108+T1);
Eg_T2=Eg-7.02e-4*T2*T2/(1108+T2);
Vbi_T2=(Tr*Vbi)-(2*Vt_T2*ln(con1)) - ( Tr*Eg_T1-Eg_T2);
Is_T2=Area*Is*pow( Tr, (Xti/N))*limexp(-(‘P_Q*Eg_T1)*(1-Tr)/(‘P_K*T2));
Cgs_T2=Area*Cgs*(1+M*(400e-6*(T2-T1)-(Vbi_T2-Vbi)/Vbi));
Cgd_T2=Area*Cgd*(1+M*(400e-6*(T2-T1)-(Vbi_T2-Vbi)/Vbi));
Vto_T2=Vto+Vtotc*(T2-T1);
Gamma_T2=Gamma*(1+Gammatc*(T2-T1));
Alpha_T2=Alpha*( pow( 1.01, Alphatc*(T2-T1)));

MESFET noise
Main components
• Thermal noise: generated by resistors Rg, Rd and Rs.

• Channel noise: 1. Linear region: essentially thermal noise; 2. Saturation

region: diffusion noise.

• Gate noise: Mainly channel noise induced in the gate (via the channel to gate
capacitance) The resulting noise is amplified by the MESFET. The capacitive
coupling causes the gate noise to have a power spectral density proportional
to frequency.

• Flicker noise: Due to random carrier generation-recombination in the lattice

1
imperfections or contaminating impurities. Flicker noise power has a n
f
behavior, with n ≈ 1.

A typical plot of GaAs MESFET Ids noise current is shown in Fig. 19, where the

29
 l[oIgdsncale]FlickernoiseChanelnoiseG
atenoise
1kHz10M Hz1GHz10GHzFrequncy
Figure 19: Typical GaAS MESFET Ids noise characteristic

device drain to source noise current is given by

Idsn = channel-thermal-noise-current + flicker-noise-current (47)

To a first approximation:
s
1 + α + α2
 
7 8·K ·T
• Channel-thermal-noise-current = · gm · · Gdsnoi
3 1+α
∂Ids
Where gm = ,
∂V gs
V ds 3
and α = 1 − , when V ds < – Linear region of operation
V gs − V to Alpha
3
Or α = 0, when V ds >= – Saturation region of operation
Alpha
s
Kf · IdsAf
• flicker-noise-current =
f
r r
4·K ·T 4·K ·T
• Resister thermal noise equations IRgn = , IRdn = ,
r Rg Rd
4·K ·T
and IRsn =
Rs

30
IG 5 D 1
iateR=3=bR7gg_nn1b4CQg
I d b
6 D
2ri
a
nnR3b 1
=
8 2
I
d
i
2C=g=sn1gdRb4=5innI4b=13dQd
n
=
R
_ t
a
Ge SD r
oda u i n
M
r c E
e F
T
S 1
1 3
I
i
sd
s
n
=
_3
C
d
=
Qn
s
b
W
I( x
b h 4 1
2
3=e) n
b
< r
+ a I
QD2IbSRbo2=9ursceiI4=Rs_nfII(doRbsug589676r)kn<t+=flA g c s
d n
th ;
( Q m
e
b
u
)
s r s
;589*)hT/Ri2(tfedsiln6c;nkoirs6ep(Aw
g
r=Vd4iIc(.b0kbe9873e*7a)r*P̀/<VR6n+d(obKw
Valuesfortherm al6pwrandflicker6pwraeSivenitex. h
t
r
m
1
,
.
*l
a
w
p
"
i
0
6
f
o
u"
t
r
,
k
c
/
g
R
d
6h
e
r
m
)
T
2
,l
"
)
a
+
h
t
e
r
ml
"
)
a
Figure 20: Typical GaAS MESFET equivalent circuit illustrating noise current
components

MESFET equivalent circuit with noise current components

Curtice hyperbolic tangent model: LEVEL = 1 or 2: Noise
equations
1. Verilog-A equations

fourkt=4.0*‘P_K*T2;
gm=2*Beta_T2*(V(b1)-Vto_T2)*(1+Lambda*V(b3))*tanh(Alpha_T2*V(b3));
if ( V(b3) < 3/Alpha ) begin An=1-V(b3)/(V(b1)-Vto_T2);
thermal_pwr= (8*‘P_K*T2*gm/3)*((1+An+An*An)/(1+An))*Gdsnoi;
end
else
thermal_pwr=(8*‘P_K*T2*gm/3)*Gdsnoi;
I(b3)<+white_noise(thermal_pwr,"thermal"); flicker_pwr = Kf*pow(Ids,Af);
I(b3)<+flicker_noise(flicker_pwr,1.0,"flicker");
end
I(b7) <+ white_noise(Area*fourkt/Rg_T2, "thermal");
I(b8) <+ white_noise(Area*fourkt/Rd_T2, "thermal");
7
Tsivids and Yanis, Operation and modeling of the MOS transistor, McGraw-HIll 1987, p340

31
 Id
sV
I(b9) <+ white_noise(Area*fourkt/Rs_T2, "thermal");

1 2
=
Ud
s
V
2. Typical noise simulation results

V
0
=
U
3I
g M
L
t
VE
S
F
E
V
L
1
o
=
E
T
1
=
8
.
V
1
=
UV
c
di
s
m
ul
t
ai
o
nB
A
a
Le
a
l
h
p
b
d
m
l
t
e
a
=3
3
e

2
2
5
=
.
0
a
=
0
10
5
.a
P
s
w
S
Wr
a
m
e
p
1t
e
er
a
ci
s
mC
D
l
a
u1
i
t
o
n D
K
Gf
1
e
=

d
s
n
o.
2
i
1
= i
m
T
y
a
PC
=
A
l
i
p
e
r
a
m
=1
n
d
s
V
C
A
T
y
S
t1
l
p
e
o
=
1
t
a
r
o
pg
H
z
k
H
0z S
t
o
P1
t
=
6
p
i
t
n
s
=3
8
1P
o
N=
i
t
n
s
=
s
e
yG
2
0
e
s
)
fe

(
t
r
q
s
M
A9
1
e

(
n
I
s
d0
1
1
e

I1
1
e

e31
4
e 1
5
eF6
1
e
r
qe
n
u1
7
e
H
c
yz8
1
e 1
e90
1
1
e
Figure 21: Typical LEVEL 1 (or 2) GaAS MESFET Ids noise characteristic

Statz et. al. (Raytheon) model: LEVEL = 3: Noise equa-

tions
1. Verilog-A equations

if ( V(b3) < 3/Alpha )begin

32
 H1=(1-(1-(Alpha*V(b3))/3))/(1+B*(V(b1)-Vto_T2));
gm=2*Beta_T2*(V(b1)-Vto_T2)*(1+Lambda*V(b3))*H1+(Beta_T2*
(1+Lambda*V(b3))*pow((V(b1)-Vto_T2),2))*B*H1/(1+B*(V(b1)-Vto_T2));
An=1-V(b3)/(V(b1)-Vto_T2);
thermal_pwr= (8*‘P_K*T2*gm/3)*((1+An+An*An)/(1+An))*Gdsnoi;
end
else begin
gm=2*Beta_T2*(V(b1)-Vto_T2)*(1+Lambda*V(b3))/(1+B*(V(b1)-Vto_T2))+
(Beta_T2*(1+Lambda*V(b3))*pow((V(b1)-Vto_T2),2))
*B/pow( (1+B*(V(b1)-Vto_T2)),2);
thermal_pwr=(8*‘P_K*T2*gm/3)*Gdsnoi;
end
I(b3) <+ white_noise(thermal_pwr, "thermal");
flicker_pwr = Kf*pow(Ids,Af);
I(b3) <+ flicker_noise(flicker_pwr,1.0, "flicker");
I(b7) <+ white_noise(Area*fourkt/Rg_T2, "thermal");
I(b8) <+ white_noise(Area*fourkt/Rd_T2, "thermal");
I(b9) <+ white_noise(Area*fourkt/Rs_T2, "thermal");

2. Typical noise simulation results

TriQuint Semiconductor TOM 1 model: LEVEL = 4: Noise

equations
1. Verilog-A equations

if ( V(b3) < 3/Alpha )begin

Ids1=(Beta_T2*pow( (V(b1)-Vto_T2), Qp) )*(1-pow( (1-Alpha*V(b3)/3), 3));
gm1=Qp*Beta_T2*pow( V(b1)-Vto_T2, Qp-1)*(1-(1-pow(Alpha*V(b3)/3, 3)));
gm=(gm1*(1+Lambda*V(b3))/(1+Delta*V(b1)*Ids1))*(1+(Delta*V(b3)*Ids1)/
(1+Delta*V(b3)*Ids1));
An=1-V(b3)/(V(b1)-Vto_T2);
thermal_pwr= (8*‘P_K*T2*gm/3)*((1+An+An*An)/(1+An))*Gdsnoi;
end
else begin
Ids1=(Beta_T2*pow( (V(b1)-Vto_T2), Qp) );
gm1=Qp*Beta_T2*pow( V(b1)-Vto_T2, Qp-1);
gm=(gm1*(1+Lambda*V(b3))/(1+Delta*V(b1)*Ids1))*(1+(Delta*V(b3)*Ids1)/
(1+Delta*V(b3)*Ids1));
thermal_pwr=(8*‘P_K*T2*gm/3)*Gdsnoi;
end

33
 Id
sV 2
=d
sa
P
s
wr
a
m
e
pt
e
er
1
V
0
=
UI
g M
LE
S
F
E
V
LE
=T
1
3 U
V S
W
i
m
T
y1
C
=
A
l
i
p
e1
n
3
V
1
=
U
Vc
si
m
ul
i
t
ao
nt
V
B
A
a1
o
=
3
e
a
l
h
p
b
d
m.
e
=
a8
3
2
2
5
.
0
0
=
.a
c
C
5
A
Ti
s
m
1
ll
a
ui
t
o
na
P
S
t
o
Pr
a
m
=
1
t
=
6
p
i
t
n
s
=d
s
V
3
d
DC
1G L
D
Kl
t
e
a
=
f
1
e
=
d
s
n
o01
.
2
i=
1y
S
t
a
Pp
e
o
=
1
t
r
o
p
=
i
t
n
s
=g
H
z
k
H
0
G
2
0z
19 o
Ns
e
ye
s
)
f
(
te
r
q
s
M
A
(1
e
n
I
Is
d 0
1
1
e1
e3
1
e415
e1
F6
e
r
qe
n
c
uy1
7
e
H
z 8
1
e 9
1
e10
1
e
Figure 22: Typical LEVEL 3 GaAS MESFET Ids noise characteristic

I(b3) <+ white_noise(thermal_pwr, "thermal");

flicker_pwr = Kf*pow(Ids,Af);
I(b3) <+ flicker_noise(flicker_pwr,1.0, "flicker");
I(b7) <+ white_noise(Area*fourkt/Rg_T2, "thermal");
I(b8) <+ white_noise(Area*fourkt/Rd_T2, "thermal");
I(b9) <+ white_noise(Area*fourkt/Rs_T2, "thermal");

2. Typical noise simulation results

TriQuint Semiconductor TOM 2 model: LEVEL = 5

1. Verilog-A equations

if ( V(b3) < 3/Alpha )begin

Nst=Ng+Nd*V(b3);
if ( Nst < 1.0) Nst=1.0;
Vst=Nst*Vt_T2;
Vg=Qp*Vst*ln( exp( (V(b1)-Vto_T2+Gamma_T2*V(b3)) / (Qp*Vst) ) + 1);

34
 I
d
s
E
S
MF
E
T
1 2
V
=d
sr
P
a
a
s
e
wt
m
e
pe
r
1
V
=
U0
c
aI
g
i
s
ml
u
ai
t
o
n L
V
t
o
=
V
e
a
B
l
pE
4
=
L
8
1

.
3
3
e

h
2
2
=5 U
V S
W
1
i
m
=
A
T
p
e
yC
1
l
i
n
3
V
=
UC
1
A
T
V
y
S
t1
l
p
e
o
=
1
t
a
rg
H
z
k A
a
m
L
l
t
e
D
f
=
K
d
s.
b
d
0
a
=
0
1
a
=
.
2
1
e

i
1
n
o0
5
.
ci
s
ml
i
t
uo
na
r
a
m
P
S
t
t
o
p
=
i
t
n
s
Pd
=
V
1
6
3
=s
8
1
eP
o
No
p
=
i
t
n
s
=
s
e
yH
0
G
2
0
e
sz G=d
C
1
D a
)
f
(
t
r
q
s
M
A
(9
1
e

n
I
s
d0
1
1
e

I1
1
e

e31
4
e 1
5
eF6
1
e
r
q
e
n
u1
7
e
H
c
y
z 8
1
e19
e1
1
e0
Figure 23: Typical LEVEL 4 GaAS MESFET Ids noise characteristic

Al= Alpha_T2*V(b3); Fd=Al/sqrt( 1.0+(Al*Al) );

Ids1=Beta_T2*pow( Vg, Qp)*Fd;
gm1=(Ids1/Vg)*Qp/(exp(-((V(b1)-Vto_T2+Delta*V(b3))/(Qp*Vst)))+1);
gm=gm1/pow( (1+Delta*V(b3)*Ids1),2);
An=1-V(b3)/(V(b1)-Vto_T2);
thermal_pwr= (8*‘P_K*T2*gm/3)*((1+An+An*An)/(1+An))*Gdsnoi;
end
else begin
Nst=Ng+Nd*V(b3); if ( Nst < 1.0) Nst=1.0;
Vst=Nst*Vt_T2;
Vg=Qp*Vst*ln( exp( (V(b1)-Vto_T2+Gamma_T2*V(b3)) / (Qp*Vst) ) + 1);
Al= Alpha_T2*V(b3); Fd=Al/sqrt( 1.0+(Al*Al) );
Ids1=Beta_T2*pow( Vg, Qp)*Fd;
gm1=(Ids1/Vg)*Qp/(exp(-((V(b1)-Vto_T2+Delta*V(b3))/(Qp*Vst)))+1);
gm=gm1/pow( (1+Delta*V(b3)*Ids1),2);
thermal_pwr=(8*‘P_K*T2*gm/3)*Gdsnoi;
end
I(b3) <+ white_noise(thermal_pwr, "thermal");

35
 flicker_pwr = Kf*pow(Ids,Af);
I(b3) <+ flicker_noise(flicker_pwr,1.0, "flicker");
I(b7) <+ white_noise(Area*fourkt/Rg_T2, "thermal");
I(b8) <+ white_noise(Area*fourkt/Rd_T2, "thermal");

I
d
s
I(b9) <+ white_noise(Area*fourkt/Rs_T2, "thermal");

1
V0I
g E
M
S
L
VF
E
1
T
5
=
L
8
1 2
V
=
U
Vd
sr
P
a
a
s
e
wt
m
e
pe
r
2. Typical noise simulation results

E W
1
=
U
3
Vc
a
Ci
s
m
1l
u
ai
t
o
n t
o
=
V
e
a
B
l
p
A
a
m
L8
.
3
3
e
8
h
2
2
=
.
b
d
0
a
=5
0
5
. S
i
m
=
A
p
e
y
T
a
r
a
m
P
t
tC
1
l
i
n
d
=
V
1s
=
U1
A
V
y
T
t
Sl
p
e
o
=
1
t
a
r
o
p
=
i
tg
H
z
k
G
H
0
2
0z l
t
e
D
f
=
K
G
d
s0
1
a
=
.
2
1
e
8
i
1
n
o
=c
di
s
ml
i
t
u
ao
nS
o
p
=
i
t
n
s
P6
3
=
8
1
e
8P
o
Nn
s
=
s
e
ye
s C
1
D
)
f
(
tr
q
s
M9
1
e
8
A
(n
Is
d 0
I1
1
e
8
1
1
e
8
e31
4
e 1
5
eF6
1
e
r
q
e
n
u1
7
e
H
c
y
z 8
1
e19
e1
1
e0
Figure 24: Typical LEVEL 5 GaAS MESFET Ids noise characteristic

Adding external passive components to the MES-

FET models
The Curtice model outlined in the first Qucs report on MESFETs included lead
inductance in each of the device signal paths. These inductances were not included
in the Verilog-A models described in this report, mainly to simplify the model code.
If required they can be added as external components. The test circuit shown in
Fig. 25 indicates how this can be done and illustrates the effect such components
have on the Curtice S parameter characteristics.

36
 1dDCc1sPZNiaur5m
P
=sw0m
lTSyW O h m 1
XV
1
0
U M L E g
= S 1 0
F n T H s
L
=d
L
=
H
0
1
n
VsVah=bt=dL1.e82SD3e025.33TSsSytPiaom
tSlPipnedionrAVCIBLLtegdlEopm
aair1e=m 2
X
i5GH1ozentr
pi1rnpeau=srl03kgm V
2
0
1
=
U2
P
u
N
5
Zm
=
O
h
0
m
S]1,Ptops10=LQRgds=5.31=2]2,
S[frequncy S[frequncy
]S[21,frequn0c.2y40.68][S21, frequnc2y46
Figure 25: S parameter simulated characteristics for test circuit shown in Fig. 5
that has external inductance added

37
End note
MESFETs are important high frequency devices which have been missing from
the range of active component models supplied with Qucs. While developing the
models described in this report I have attempted to make them as flexible as
possible so as to allow users the opportunity to select which model, or indeed
the make-up of the components of a model, they would like to try for a specific
simulation. The work described in this report is very much work in progress,
mainly because there are a number of other published MESFET models that have
not been included. My intention has simply been to provide a number of practical
models which were not previously available to Qucs users. Also knowing that
many Qucs users have an interest in high frequency circuit design and simulation,
the work would be of direct relevance to making Qucs more “universal“. The
procedures employed for model development are another example of the work being
undertaken by the Qucs team in response to Qucs being adopted by the wider
modelling community as part of the Verilog-A compact device standardization
project. Overall the simulation results from the models described here show a
high degree of consistency from DC to the high frequency S parameter domain.
The noise results are particularly interesting as they are based on mix of available
theories and extensions introduced especially for Qucs. Some readers will probably
have spotted one area where there appears to be differences in the simulation
results from the different models; look at the S[1,2] and S[2,1] characterstics for
each model. Here there are noticeable difference which are possibly due to the
lack of symmetry in some of the model charge equations? MESFET modelling
is a complex subject, suggesting that there are likely to be errors /bugs in the
models. If you find an error/bug please inform the Qucs development team so
that we can correct problems as they are found. In the future, particularly if the
response to this group of models is positive, I will attempt to add more MESFET
models to Qucs. Once again a special thanks to Stefan Jahn for all his help and
encouragement over the period that I have been developing the Qucs MESFET
models and writing the report which outlines their physical and mathematical
fundamentals.

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