You are on page 1of 8

# The university of Danang

## University of Science and Technology

HOMEWORK 2

Course: EE471
Lecturer: Hồ Viết Việt
Group: Nguyễn Viết Khánh Linh
Members: Nguyễn Viết Khánh Linh
Trần Ngọc Quốc
Nguyễn Duy Hoàng Giang

## Danang, September 18th, 2018

1) For the following C statement, what is the corresponding MIPS assembly
code? Assume that the variables i and j are assigned to registers \$s0 and
\$s1, respectively. Assume that the base address of the arrays A and B are
in registers \$s6 and \$s7, respectively.
B[8] = A[i-j];
Solution:
sub \$t0, \$s0, \$s1
sll \$t0, \$t0,2
lw \$t1, 0(\$t0)
sw \$t1, 32(\$s7)
2) For the following MIPS assembly instructions, what is the corresponding
C statement? Assume that the variables f and g are assigned to registers
\$s0 and \$s1, respectively. Assume that the base address of the arrays A
and B are in registers \$s6 and \$s7, respectively.

## sll \$t0, \$s0, 2 # \$t0 = f * 4

add \$t0, \$s6, \$t0 # \$t0 = &A[f]
sll \$t1, \$s1, 2 # \$t1 = g * 4
add \$t1, \$s7, \$t1 # \$t1 = &B[g]
lw \$s0, 0(\$t0) # f = A[f]
#1 word = 4 bytes
lw \$t0, 0(\$t2) #\$t0=A[f+1]
add \$t0, \$t0, \$s0 #\$t0= A[f+1] +A[f]
sw \$t0, 0(\$t1) #B[g]= A[f+1] +A[f]
Corresponding C statement: B[g] = A[f+1] + A[f]
3) For the MIPS assembly instructions in Exercise 2, rewrite the assembly
code to minimize the number if MIPS instructions (if possible) needed to
carry out the same function.
Solution:
sll \$t0, \$s0, 2
sll \$t1, \$s1, 2
lw \$s0, 4(\$t0)
lw \$t0, 0(\$t2)
sw \$t0, 0(\$t1)

## 4) Translate the following MIPS code to machine language:

 sw \$t1, 0(\$t0)
 lw \$t0, 0(\$t0)
Solution:
We have: the instruction addi rt, rs, imm
Opcode rs rt Immediate
(6-bit) (5-bit) (5-bit) (16-bit)
8hex \$s6 \$t0 4
001000 10110 01000 0000 0000 0000
0100
Machine code: 001000 10110 01000 0000000000000100
So Assembler language in hexa is : 0x22c80004
We have: the instruction add rd,rs,rt
Opcode rs rt rd shamt funct
(6-bit) (5-bit) (5-bit) (5-bit) (5-bit) (6-bit)
0 \$s6 \$0 \$t1 0 20hex
000000 10110 00000 01001 00000 100000
Machine code: 000000 10110 00000 01001 00000 100000
So Assembler language in hexa is : 0x02c04820
 sw \$t1, 0(\$t0)
We have: the instruction sw rt, offset(rs)
Opcode rs rt offset
(6-bit) (5-bit) (5-bit) (16-bit)
2bhex \$t0 \$t1 0
101011 01000 01001 0000 0000 0000
0000
Machine code: 101011 01000 01001 0000000000000000
So Assembler language in hexa is : 0xad090000
 lw \$t0, 0(\$t0)
We have: The instruction lw rt, offset(rs)
Opcode rs rt offset
(6-bit) (5-bit) (5-bit) (16-bit)
23hex \$t0 \$t0 0
100011 01000 01000 0000 0000 0000
0000
Machine code: 100011 01000 01000 0000000000000000
So Assembler language in hexa is 0x8d080000
We have: the instruction add rd,rs,rt
Opcode rs rt rd shamt funct
(6-bit) (5-bit) (5-bit) (5-bit) (5-bit) (6-bit)
0 \$t1 \$t0 \$s0 0 20hex
000000 01001 01000 10000 00000 100000
Machine code: 000000 01001 01000 10000 00000 100000
So Assembler language in hexa is 0x01288020
5) Translate the following C code to MIPS assembly code. Use a minimum
number of instructions. Assume that the values of a, b, i, and j are in
registers \$s0, \$s1, \$t0, and \$t1, respectively. Also, assume that register
\$s2 holds the base address of the array D.
for(i=0; i<a; i++)
for(j=0; j<b; j++)
D[4*j] = i + j;
Solution:
LOOP1: addi \$t0, \$t0, 1 #i+=1
slt \$t2, \$t0, \$s0 #i<a
beq \$t2, \$0, EXIT #if \$t2 == 0, go to EXIT
and \$t1, \$t1, \$0 #j=0
LOOP2: slt \$t2, \$t1, \$s1 #j<b
beq \$t2, \$0, LOOP1 #if \$t2 == 0, branch to LOOP1
add \$t2, \$t0, \$t1 #\$t2= i+j
sll \$t4, \$t1, 4 #\$t4= 4*j
add \$t3, \$s2, \$t4 #\$t3 = SD[4*j]
sw \$t2, 0(\$t3) #store \$s2 point by \$t3
EXIT:

## 6) Convert the following machine code program to assembly for MIPS

00011010010000000000000000000011
00100000000000000000000000000000
10101110001010110000000000000000
10101110001010100000000000000010
00100001001010010000000000001000
Solution:
 Machine code: 00011010010000000000000000000011
We have: From the opcode => I-type format
Opcode rs rt Immediate
(6-bit) (5-bit) (5-bit) (16-bit)
000110 10010 00000 0000 0000 0000 0011
6 18 0 3
blez \$s2 \$0 3
Assembly for MIPS: blez \$s2, 3
 Machine code: 00100000000000000000000000000000
We have: From the opcode => I-type format
Opcode rs rt Immediate
(6-bit) (5-bit) (5-bit) (16-bit)
001000 00000 00000 0000 0000 0000 0000
8 0 0 0
Assembly for MIPS: addi \$0, \$0, 0
 Machine code: 10101110001010110000000000000000
We have: From the opcode => I-type format
Opcode rs rt offset
(6-bit) (5-bit) (5-bit) (16-bit)
101011 10001 01011 0000 0000 0000 0000
2bhex 17 11 0
sw \$s1 \$t3 0
Assembly for MIPS: sw \$t3, 0(\$s1)
 Machine code: 10101110001010100000000000000010
We have: From the opcode => I-type format
Opcode rs rt offset
(6-bit) (5-bit) (5-bit) (16-bit)
101011 10001 01010 0000 0000 0000 0010
2bhex 17 10 2
sw \$s1 \$t2 0
Assembly for MIPS: sw \$t2, 2(\$s1)
 Machine code: 00100001001010010000000000001000
We have: From the opcode => I-type format
Opcode rs rt Immediate
(6-bit) (5-bit) (5-bit) (16-bit)
001000 01001 00000 0000 0000 0000 1000
8 9 9 8
Assembly for MIPS: addi \$t1, \$t1, 8
7) Pseudo-instructions are not part of the MIPS instruction set but often
appear in MIPS programs. The assembler then has to convert them into a
small set of real MIPS instructions. For each of the following pseudo-
instructions, convert them to a very short equivalent sequence of real
MIPS instructions. If you need a temporary register, you should use \$at.

Note that “small” is a constant that fits in 16 bits (i.e. small enough for the
immediate field of an instruction), and “big” is a constant that is 32 bits (i.e.
too long for the immediate field).
Solution:
Pseudo instruction What it solution
accomplishes
li \$t2, big \$t2 = big lui \$t2, upper(big)
ori \$t2, \$t2, lower(big)

## move \$t1, \$t2 \$t1 = \$t2 add \$t1, \$t2, \$0

beq \$t1, small, L if (\$t1 = small) go addi \$t0, \$0, small
to L beq \$t1, \$t0, L

ble \$t3, \$t4, L if (\$t3 <= \$t4) go to slt \$t0, \$t4, \$t3
L beq \$t0, \$0, L

addi \$t0, \$t2, big \$t0 = \$t2 + big lui \$t1, upper(big)
ori \$t1, \$t1, lower(big)

8) Assume that we would like to expand the MIPS register file to 128
registers
and expand the instruction set to contain four times as many instructions.
a. How this would this affect the size of each of the bit fields in the R-type
instructions?
b. How this would this affect the size of each of the bit fields in
the I-type instructions?
Solution:
Expand the register file to 128 registers. For 128 registers, we need 7 bits
number to recognize one.
a) The size of rs, rt, and rd in R-type instructions should be increased to 7 bits
each. Also, the instruction set is expanded 4 times, the opcode should
contain 8 bits.
b) The size of rt, and rd in I-type instructions should be 7 bits each. The opcode
should be 8 bits as the instruction set is expanded 4 times.
9) Find the shortest sequence of MIPS instructions that extracts bits 16 down
to 11 from register \$t0 and uses the value of this field to replace bits 31
down to 26 in register \$t1 without changing the other 26 bits of register
\$t1.
Solution:
srl \$t2,\$t0,11 # Shift \$t0 11 bits to the right
sll \$t2,\$t2,26 # Shift \$t2 26 bits to the left, bits 0-25 will be zero
sll \$t1,\$t1,6 # Shift \$t1 6 bits to the left
srl \$t1,\$t1,6 # Shift \$t1 6 bits to the right, bit 26-31 will be zero