Ahblit

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 11:25:01 07/26/2018
// Design Name:
// Module Name: ahblit
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module ahblit(hdatain,hclk,hrst,hwrite,hsize,hburst,htrans,hready,haddr1,hresp,out1
);
input [2:0]hburst;
input [2:0]hsize;
input [31:0]hdatain;
input [31:0]haddr1;
output reg [1:0]htrans;
input hwrite,hrst,hclk;
output reg hresp;
output reg hready;
//output reg [31:0] dataout;

//output reg [31:0]hrdata;
reg[31:0] ram1[255:0];
//reg[31:0] ram2[255:0];
//reg[31:0] ram3[255:0];
output reg[31:0] out1;
//reg[31:0] out2;
//reg[31:0] out3;
reg[31:0] addr_reg1;
//reg[31:0] addr_reg2;
//reg[31:0] addr_reg3;
parameter single=3'b000;
parameter undefined=3'b001;
parameter wrap4=3'b010;
parameter incr4=3'b011; //hburst
parameter incr8=3'b101;
parameter incr16=3'b111;
parameter BYTE=3'b000;
parameter HALFWORD=3'b001;
parameter WORD=3'b010; //hsize
parameter doubleword=3'b011;
parameter word4=3'b100;
integer i;
always @(posedge hclk)
begin
case(hsize)
BYTE:
begin
case(hburst)
single:begin
if(hwrite==1)
begin
$display("welcome to single state");
hresp<=0;
hready<=1;
htrans<=2'b10;
ram1[haddr1]<=hdatain;
end
else
begin
hresp<=0;
hready<=1;
htrans<=2'b11;
out1<=ram1[haddr1];
end
end
undefined:begin
if(hwrite==1)
begin
$display("welcome to undefined state");
hresp<=1;
hready<=0;
htrans<=2'b10;
addr_reg1<=haddr1;
end
else
begin
for(i=0;i<=4;i=i+1)
hresp<=0;
hready<=1;
htrans<=2'b11;
addr_reg1<={addr_reg1[31:0]+1'b1};
ram1[addr_reg1]<=hdatain;
out1<=ram1[haddr1];
end
end
incr4:begin
if(hwrite==1)
begin
$display("welcome to incr4 state");
hresp<=0;
hready<=0;
htrans<=2'b10;
addr_reg1<=haddr1;
end
else
begin
for(i=0;i<=4;i=i+1)
begin
hresp<=0;
hready<=1;
htrans<=2'b11;
ram1[haddr1]<=addr_reg1;
out1<=ram1[haddr1];
end
end
end
wrap4:begin
if(hwrite==1)
begin
$display("welcome to wrap4 state");
hresp<=0;
hready<=0;
htrans<=2'b10;
addr_reg1<=haddr1;
end
else
begin
hresp<=0;
hready<=1;
htrans<=2'b11;
addr_reg1<={addr_reg1[31:2],addr_reg1[1:0]+1'b1};
out1<=ram1[addr_reg1];
end
end
incr8:begin
if(hwrite==1)
begin

hresp<=0;
hready<=0;
htrans<=2'b10;
addr_reg1<=haddr1;
end
else
begin
hresp<=0;
hready<=1;
htrans<=2'b11;
out1<=ram1[haddr1];
end
end
wrap8:begin
if(hwrite==1)
begin
hresp<=0;
hready<=0;
htrans<=2'b10;
addr_reg1<=haddr1;
end
else
begin
hresp<=0;
hready<=1;
htrans<=2'b11;
end
end
incr16:begin
if(hwrite==1)
begin
hresp<=0;
hready<=0;
htrans<=2'b10;
addr_reg1<=haddr1;
end
else
begin
hresp<=0;
hready<=1;
htrans<=2'b11;
out1<=ram1[haddr1];
end
end
wrap16:begin
if(hwrite==1)
begin
hresp<=0;
hready<=0;
htrans<=2'b10;
addr_reg1<=haddr1;
end
else
begin
hresp<=0;
hready<=1;
htrans<=2'b11;
end
end
endcase //ending for hburst
end //ending for byte
HALFWORD:begin
case(hburst)
undefined:begin
if(hwrite==1)
begin
hresp<=1;
hready<=0;
htrans<=2'b10;
addr_reg1<=haddr1;
end
else
begin
hresp<=0;
hready<=1;
htrans<=2'b11;
out1<=ram1[haddr1];
end
end
incr4:begin
if(hwrite==1)
begin
hresp<=0;
hready<=0;
htrans<=2'b10;
addr_reg1<=haddr1;
end
else
begin
begin
hresp<=0;
hready<=1;
htrans<=2'b11;
out1<=ram1[haddr1];
end
end
end
wrap4:begin
if(hwrite==1)
begin
hresp<=0;
hready<=0;
htrans<=2'b10;
addr_reg1<=haddr1;
end
else
begin
hresp<=0;
hready<=1;
htrans<=2'b11;
end
end
incr8:begin
if(hwrite==1)
begin
hresp<=0;
hready<=0;
htrans<=2'b10;
addr_reg1<=haddr1;
end
else
begin
hresp<=0;
hready<=1;
htrans<=2'b11;
out1<=ram1[haddr1];
end
end
wrap8:begin
if(hwrite==1)
begin
hresp<=0;
hready<=0;
htrans<=2'b10;
addr_reg1<=haddr1;
end
else
begin
hresp<=0;
hready<=1;
htrans<=2'b11;
end
end
incr16:begin
if(hwrite==1)
begin
hresp<=0;
hready<=0;
htrans<=2'b10;
addr_reg1<=haddr1;
end
else
begin
hresp<=0;
hready<=1;
htrans<=2'b11;
out1<=ram1[haddr1];
end
end
wrap16:begin
if(hwrite==1)
begin
hresp<=0;
hready<=0;
htrans<=2'b10;
addr_reg1<=haddr1;
end
else
begin
hresp<=0;
hready<=1;
htrans<=2'b11;
end
end
end //ending for halfword
WORD:begin
case(hburst)
undefined:begin
if(hwrite==1)
begin
hresp<=1;
hready<=0;
htrans<=2'b10;
addr_reg1<=haddr1;
end
else
begin
hresp<=0;
hready<=1;
htrans<=2'b11;
out1<=ram1[haddr1];
end
end
incr4:begin
if(hwrite==1)
begin
hresp<=0;
hready<=0;
htrans<=2'b10;
addr_reg1<=haddr1;
end
else
begin
hresp<=0;
hready<=1;
htrans<=2'b11;
out1<=ram1[haddr1];
end
end
wrap4:begin
if(hwrite==1)
begin
hresp<=0;
hready<=0;
htrans<=2'b10;
addr_reg1<=haddr1;
end
else
begin
hresp<=0;
hready<=1;
htrans<=2'b11;
end
end
incr8:begin
if(hwrite==1)
begin
hresp<=0;
hready<=0;
htrans<=2'b10;
addr_reg1<=haddr1;
end
else
begin
hresp<=0;
hready<=1;
htrans<=2'b11;
out1<=ram1[haddr1];
end
end
wrap8:begin
if(hwrite==1)
begin
hresp<=0;
hready<=0;
htrans<=2'b10;
addr_reg1<=haddr1;
end
else
begin
hresp<=0;
hready<=1;
htrans<=2'b11;
end
end
incr16:begin
if(hwrite==1)
begin
hresp<=0;
hready<=0;
htrans<=2'b10;
addr_reg1<=haddr1;
end
else
begin
hresp<=0;
hready<=1;
htrans<=2'b11;
out1<=ram1[haddr1];
end
end
wrap16:begin
if(hwrite==1)
begin
hresp<=0;
hready<=0;
htrans<=2'b10;
addr_reg1<=haddr1;
end
else
begin
hresp<=0;
hready<=1;
htrans<=2'b11;
end
end
end //ending for word
endcase //ending for hsize
end //ending for always
endmodule

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Ahblit

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Доступные форматы

`timescale 1ns / 1ps

// Create Date: 11:25:01 07/26/2018

// Module Name: ahblit

// Revision 0.01 - File Created

output reg [1:0]htrans;

output reg hresp;

output reg hready;

//output reg [31:0] dataout;

output reg[31:0] out1;

parameter incr4=3'b011; //hburst

parameter WORD=3'b010; //hsize

$display("welcome to single state");

$display("welcome to undefined state");

$display("welcome to incr4 state");

$display("welcome to wrap4 state");

$display("welcome to incr8 state");

$display("welcome to wrap8 state");

$display("welcome to incr16 state");

$display("welcome to wrap16 state");

endcase //ending for hburst

end //ending for byte

$display("welcome to undefined state");

$display("welcome to incr4 state");

$display("welcome to wrap4 state");

$display("welcome to incr8 state");

$display("welcome to wrap8 state");

$display("welcome to incr16 state");

$display("welcome to wrap16 state");

endcase //ending for hburst

end //ending for halfword

$display("welcome to undefined state");

$display("welcome to incr4 state");

$display("welcome to wrap4 state");

$display("welcome to incr8 state");

$display("welcome to wrap8 state");

$display("welcome to incr16 state");

$display("welcome to wrap16 state");

endcase //ending for hburst

end //ending for word

endcase //ending for hsize

end //ending for always

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