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Image processing has opened the gateway for efficient B. Algorithm for edge detection
transmission of images through several different modules. The image is considered as a matrix of pixel intensity
Implementation of such techniques is a major task for values of size NxM, ‘N’ representing the number of rows and
successful output. This paper brings the two emerging ‘M’ representing number of columns. Edges of the image are
modules into one platform for performing edge detection on detected using sliding kernel matrix horizontally and vertically
the given image. There are already few existing working on the input image matrix. The sliding kernel matrix is defined
models for edge detection using beagle board and A field- by horizontal and vertical as shown in Fig 1 and Fig 2.
programmable gate array separately. The paper mainly focuses
on the connectivity between the beagle board, FPGA through -1 -2 -1
I2C; algorithm for edge detection and process for the
transmission of the transformed image.
0 0 0
1 2 1
Edges are boundaries between different textures. Edge also
can be defined as discontinuities in image intensity from one
pixel to another. The edges for an image are always the Fig. 1. Horizontal kernel matrix
important characteristics that offer an indication for a higher
frequency. Detection of edges for an image may help for -1 0 1
image segmentation, data compression, and also help for well -2 0 2
matching, such as image reconstruction [4].
-1 0 1
Field-programmable gate array are programmable digital
logic chips. A field-programmable gate array (FPGA) is Fig. 2. Vertical kernel matrix
an integrated circuit designed to be configured by a customer
or a designer after manufacturing. The FPGA configuration is The sliding kernel matrix is considered of size 3x3 which
generally specified using a hardware description is slided over the 3x3 matrices of NxM image matrix. The
language (HDL), similar to that used for an application- matrices of horizontal with image matrix are multiplied with
specific integrated circuit (ASIC). output1 and multiplication of vertical matrix with image
matrix resulting in output2. These two outputs are compared
Section 2 in the present paper deals with the process, and the maximum value is considered as the edge that is
Section 3 and 4 presents the hardware and software detected and the minimum value is neglected in the output
implementation. Section 5 illustrates the results and section 5 image. This process is shown in the form of a flow diagram as
concludes the work. shown in Fig 3.
yes
no
OH > OV
A. Beagle Board
Beagle board is an open source software development
system with OMAP3530 system-on-a-chip. The board has
several specifications and features which makes the board
more flexible and user-friendly [1]. It also has expansion
block for other peripheral devices to be connected. The board
with specifications is as shown in Fig 4. Fig. 4. Beagle board with specifications
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B. FPGA I2C plays a major role in the interface between the beagle
FPGA is cost effective board using the specifications to board and FPGA. The bus is drawn with DS1307 interface and
reduce the system complexity and power consumption. Its a microcontroller for reading and writing the data onto the
compatibility with image processing is comparatively device peripherally connected [2]. This interface section with
effective compared to other boards. The data is transmitted in I2C bus is as shown in Fig 7.
bit stream downloaded through PC with supporting Xilinx
software run on PC.
C. I2C
I2C is a bus which works under a protocol for the
transmission of bits in synchronous or asynchronous format.
This bus is specified with two lines: SCL (serial clock) and
SDA (serial data). SCL provides the necessary clock for the
start and stop of the bit transmission and the bit transmission is
done using SDA signal [3]. The start and stop condition is as
shown in Fig 5 and Fig 6
SDA
SCL
PC
xilinx
SDA
FPGA SCL Display
(I2C Bus Beagle board
Master) Bus interface
SDA SCL
OUT
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V. OUTPUT & SIMULATION RESULTS
IV. SOFTWARE IMPLEMENTATION
A. Software required
• The Xilinx – performing edge detection
algorithm on PC and dumping the bitstream on to
the FPGA
• Keil C – to run on the microcontroller interface
and bus interface.
• Linux – support beagle board in reading through
SCL, SDA signals by I2C port and writing on to
the display through the port.
B. Working methodology
The input image is taken from the PC connected to FPGA
and algorithm is run using Xilinx software. The bitstream is
downloaded on to FPGA and by the interface unit, it is
transmitted to beagle board though I2C. With the help of
microcontroller interface, FPGA acts as I2C bus which
generates SCL and SDA. At the start condition of SCL, the bit
stream is transmitted through SDA and at the stop condition of
SCL, transmission stops. This transformed image is then read
by beagle board and the resultant image is displayed on the
display. The connectivity between the devices is as shown in
Fig 9.
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The transformed image on the display is depicted in Fig 12. VI. CONCLUSION
Though several systems exists performing the edge
detection using FPGA, the proposed work gives the module of
edge detection using FPGA with beagle board connected
through I2C protocol. This system is effective in terms of the
efficiency of transmission, size of image transmitted and rate
of transmission. It is also cost effective reducing the
complexity in hardware by replacing multiple interface units
used for other modules.
References
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