1/3 inch NTSC/PAL CMOS Image Sensor with

720 X 480 Pixel array

PC1089K

6th Floor, Gyeonggi R&DB Center, 906-5 Iui-dong, Yeongtong-gu,

Suwon-si, Gyeonggi-do, 443-766, Korea
Tel : 82-31-888-5300, FAX : 82-31-888-5398

Copyright ⓒ 2010, Pixelplus Co.,Ltd

ALL RIGHTS RESERVED
 PC1089K
1/3 inch NTSC/PAL CMOS Image Sensor with
720 X 480 Pixel array

VSYNC

HSYNC
AGND

HGND
AVDD

HVDD
RSTB
▶ Features

ISIN

D9
D8
D7
D6
D5
D4

D3
D2
42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27
▷ 728 x 488 effective pixel array with
STDBY 43 26 SCL
RGB Bayer color filters and micro-lens CADD1 44 25 SDA
▷ Power supply CADD0 45 24 DGND

AVDD : 3.3V, HVDD : 3.3V, CVDD : 3.3V LED 46 23 HGND

TE 47 22 HVDD
▷ Output formats GENI 48
Effective Pixel Array
21 DVDD
(Notch : Bottom)
◆ Composite Output mode GENO 49 20 SCK
MIRS0 50 19 MISO
- CVBS (NTSC/PAL)
MIRS1 51 18 MOSI
◆ Digital Output mode IRIS0 52 17 CSB
- max. D1 (720x480) YCbCr422/RGB565/ IRIS1 53 16 D1

RGB444 (progressive, 60 fps @ 54Mhz) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

AVDD1
AGND1
CN
CP
CVDD
CGND
REXT
D0
PCLK
DVDD
HVDD
HGND
DGND
X1
X2
- max. D1 (720x480) Bayer
(progressive, 60 fps @ 27Mhz)
◆ Analog/Digital Output mode
[Fig. 1] PIN Description
- ITU-R. BT656 (720x240/288)
(interlaced, 60 fields @ 27Mhz)
- CVBS (30 fps @ 27Mhz) Effective Pixel Array 728(H) x 488(V)
▷ Image processing on chip
Pixel Size 6.35 um x 7.4 um
Lens shading, Gamma/Defect/Color correction,
Low pass filter, Color interpolation, Saturation, Effective Image Area 4622.8 um x 3611.2 um
Edge enhancement, Brightness, Contrast, Optical Format 1/3 inch
Special effects, Auto black level, Auto white
Max. Clock frequency 54 MHz
balance, Auto exposure control and Back light
compensation 60 fps @ 720x480, YCbCr, 54Mhz
▷ Frame size, window size and position can 60 fps @ 720x480, Bayer, 27Mhz
Max. Frame Rate 60 field @ 720x240(288), YCbCr,
be programmed through a 2-wire serial
27Mhz
interface bus 30 fps @ CVBS, 27Mhz
▷ VGA / QVGA / QQVGA / CIF / QCIF Scaling
Dark Signal 33.3 [mV/sec] @ 60°C
▷ High Image Quality and Ultra low light
performance Sensitivity 13.8 [V/Lux.sec]
▷ I2C master include Analog : 3.3V
▷ Motion detection support Power Supply HVDD : 3.3V
▷ Alarm mode, Privacy mode support CVDD : 3.3V
▷ Artificial Intelligence power save mode
334.3 [mW] @ Dynamic
▷ Chip Address Selection PADs Power Consumption
▷ Horizontal / Vertical mirroring 670.6 [uW] @ Standby
▷ 50Hz, 60Hz flicker automatic cancellation
Operating Temp. - 40 ~ 105 [°C] @ AT
▷ Software Reset
(Fully Functional Temp.) - 30 ~ 80 [°C] @ CT
▷ External Sync (Gen. Lock) support
▷ Off-chip IR-LED control Dynamic Range 63.7 [dB]
▷ Crystal input support
SNR 46.4 [dB]
▷ On chip regulator for DVDD
▷ CSP/CLCC/PLCC Package type supports [Table 1] Typical Parameters

Rev 0.6 2/3 CrystalImage & ImagingInnovation

 PC1089K
1/3 inch NTSC/PAL CMOS Image Sensor with
720 X 480 Pixel array

▶ Signal Environment
PC1089K don’t have tolerant Input pads. The input signal must be equal to HVDD for stable operation.
If the power of input signal is higher than recommended, it may flow leakage current by shot circuit path
in the input PADs.

▶ Chip Architecture
PC1089K has 728 x 488 effective pixel array and column/row driver circuits to read out the pixel data
progressively. CDS circuit reduces noise signals generated from various sources mainly resulting from
process variations. Pixel output is compared with the reset level of its own and only the difference signal is
sampled, thus reducing fixed error signal level. Each of R, G, B pixel output can be multiplied by different
gain factors to balance the color of images in various light conditions. The analog signals are converted to
digital forms one line at a time and 1 line data are streamed out column by column. The Bayer RGB data are
passed through a sequence of image signal processing blocks to finally produce YCbCr 4:2:2 output data.
Image signal processing includes such operations as gamma correction, defect correction, low pass filter,
color interpolation, edge enhancement, color correction, contrast stretch, color saturation, white balance,
exposure control and back light compensation. Internal functions and output signal timing can be
programmed simply by modifying the register files through 2-wire serial interface.

Effective Pixel Array

728 x 488 Bayer Image Signal Output
Parallel
& Processing Processing Format
Output
Sensor Core

BT656 TV Composite
Timing Generator AE/AWB FIFO DAC
Enc. Enc. Output

2-wire Serial Interface (slave) Serial Interface (master)

RSTB x1 STDBY

[Fig. 2] Block Diagram

Rev 0.6 3/3 CrystalImage & ImagingInnovation