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fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TIE.2017.2701770, IEEE
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Quasi Cascaded H-Bridge Five-Level

Boost Inverter
Minh-Khai Nguyen, Member, IEEE, and Tan-Tai Tran


Abstract—Latterly, multilevel inverters have become
more attractive for researchers due to low total harmonic
distortion (THD) in the output voltage and low
electromagnetic interference (EMI). This paper proposes a
novel single-stage quasi-cascaded H-bridge five-level
boost inverter (qCHB-FLBI). The proposed five-level
inverter has the advantages over the cascaded H-bridge
quasi-Z-source inverter (CHB-qZSI) in cutting down
passive components. Consequently, size, cost, and weight
of the proposed inverter are reduced. Additionally, the
proposed qCHB-FLBI can work in the shoot-though state.
A capacitor with low voltage rating is added to the
proposed topology to remove an offset voltage of the
output AC voltage when the input voltages of two modules
are unbalanced. Besides, a simple PID controller is used to
control the capacitor voltage of each module. This paper
presents circuit analysis, the operating principles, and
simulation results of the proposed qCHB-FLBI. A 1.2-kVA (a)
laboratory prototype was constructed based on a DSP
TMS320F28335 to validate the operating principle of the
proposed inverter.

Index Terms—Cascaded H-bridge inverter, five-level

inverter, quasi-Z-source inverter, boost inverter,
shoot-through state.

I. INTRODUCTION

M ultilevel inverters have recently received many attentions

from researchers due to their advantages over the
conventional three-level pulse-width modulation (PWM)
inverters. The advantages of the multilevel inverters are as
follows: improved quality output waveforms with lower total
harmonic distortion (THD), smaller filter size and lower
electromagnetic interface (EMI) [1]. Three general multilevel
inverter topologies are: flying capacitors, neutral point clamped
(NPC), and cascaded H-bridge (CHB) inverters. Among these
topologies, the CHB inverter has unique advantages in (b)
modularity and its contribution of high power. These Fig. 1. Conventional CHB five-level inverters based on (a) DC-DC boost
converter and (b) qZS network.
advantages make the CHB inverter an attractive option for
many applications such as uninterruptible power supplies
(UPS), grid-connected system, StatCom system, motor drive,
etc. [2]–[11]. However, the traditional CHB multilevel inverter
Manuscript received January 18, 2017; revised April 04, 2017; is a buck DC-AC power conversion, where the peak AC output
accepted April 23, 2017.
M. K. Nguyen is with the Department of Electrical Engineering, voltage is limited by the total DC source voltages. In [12] and
Chosun University, Gwangju 61452, South Korea (e-mail: [13], an additional DC-DC boost converter is demanded for
nmkhai00@gmail.com; nmkhai@chosun.ac.kr). each module in the CHB topology to achieve the high AC
T. T. Tran is with the Department of Electrical and Electronics
Engineering, Ho Chi Minh City University of Technology and Education, output voltage when the DC input voltages are low. Adding
Ho Chi Minh City 70000, Viet Nam (e-mail: trantantaikdd@gmail.com). DC-DC boost power converter results in low efficiency and

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high cost. Fig. 1(a) shows the conventional two-stage CHB L1 P1

boost-five-level inverter (CHB-BFLI) [12]. Two capacitors, Db1
two boost inductors, two diodes, ten switches, one filter S3 S1
Vdc1
inductor and a resistive load are utilized in the conventional
Lf io
CHB-BFLI. The boost DC-DC converter is used to control the b a
C1 VC1
DC-link voltage on each H-bridge circuit. As shown in Fig.
S4 S2
1(a), both the top and bottom switches in the same leg cannot be
switched on simultaneously because the DC-link capacitor is N1 Da1
connected to each leg in parallel. And a dead-time between two
switches in the leg must be used to avoid short circuit in the DC vo
L2 P2 R
source [14]. Db2
A CHB quasi-Z-source inverter (qZSI) with single-stage S7 S5
power conversion was proposed in [15] and [16]. Fig. 1(b) Vdc2
shows the CHB five-level qZSI [15], where a qZS network with
c
two capacitors and two inductors is connected to each H-bridge b C2 VC2
circuit. In the CHB-qZSI, a shoot-through (ST) state is used to S8 S6
boost voltage without any damages in the power circuit. In one Da2
N2
switching period, the number of the ST states in the
single-phase qSBI is two. Therefore, the operating frequency of Fig. 2. Proposed qCHB-FLBI topology.
the inductors is twofold the switching frequency. In the
iin1 L1 iin1 L1 iin1 L1
CHB-qZSI, the input DC current is continuous with low ripple. iPN1
vL1 vL1 vL1
Each module in the CHB qZSI can produce the same DC-link Db1 Db1
Db1
vPN1
Vdc1 Vdc1
voltage by control the ST duty cycle. An effective control vPN1 Vdc1

method, including system-level control and PWM for C1

vPN1
C1 C1
Vc1
Vc1 VC1
single-phase CHB-qZSI based grid-tie photovoltaic (PV) Da1 Da1 Da1
power system is presented in [17]. Three-phase CHB-qZSI’s
(a) (b) (c)
control is proposed and demonstrated in [18] for application to
iin1 L1 iin1 L1 iin1 L1
PV power systems. A qZS modular cascaded converter is iPN1 iPN1
vL1 vL1 vL1
addressed in [19] for dc integration of high-power PV systems. Db1
vPN1
Db1
vPN1
Db1
Vdc1 Vdc1 Vdc1
Energy stored CHB-qZSI based PV power generation system is
iPN1
proposed in [20]. Fault-tolerant CHB inverters using Z-sourced Vc1
C1
Vc1
C1
Vc1
C1
network are investigated in [21] and [22]. A cascaded Da1 Da1
vPN1
Da1
transformer-based multilevel inverter using single Z-source
(d) (e) (f)
network is presented in [23]. An active-front-end (AFE) CHB
Fig. 3. Operating states of module 1. (a) ST state 1, (b) ST state 2,
multilevel inverter based on dual-boost/buck converter is (c) NST state 1, (d) NST state 2, (e) NST state 3 and (f) NST state 4.
proposed in [24]. Like the CHB-qZSI, the AFE-CHB inverter
also has the shoot-through immunity and buck/boost voltage.
However, the CHB-qZSI in [15]-[23] and the AFE-CHB II. PROPOSED TOPOLOGY
inverter in [24] use a large number of passive elements with
raising the size, cost, and weight of the power cascaded system. The configuration of the proposed single-stage qCHB-FLBI
A quasi-switched boost (qSB) network in [25]-[27] is used to is illustrated in Fig. 2. The proposed inverter consists of two
replace the qZS network. In comparison to the qZS network, separate DC sources, two quasi-boost inverter (qBI) modules
the qSB network uses one less capacitor, one less inductor, one and an inductor filter connected to the resistive load in series.
more diode and one more switch in front of the main H-bridge Each qBI module contains one capacitor, one boost inductor,
circuit. An isolated high step-up DC-DC converter is proposed four switches and two diodes. The output voltage of the
in [27] based on the qSB network. In this paper, a new proposed qCHB-FLBI has five levels.
single-stage quasi-cascaded H-bridge five-level boost inverter A. Operating Principles
(qCHB-FLBI) is proposed. In the proposed qCHB-FLBI, the
Assuming that two qBI modules have the same parameters,
qSB network as presented in [27] is used in each module. The
the qBI module 1 in the proposed system is used to analyze the
main features of the proposed qCHB-FLBI are five-level output
operating principle. Fig. 3 shows the operating modes of the
voltage with boost voltage ability, reduction in a number of
qBI module 1 in the proposed inverter.
passive components and shoot-through immunity. Section II
In the shoot-through (ST) state 1, as shown in Fig. 3(a), both
presents the proposed cascaded topology. Comparison with the
S1 and S2 are turned on. Da1 is conducting, while Db1 is blocking.
conventional CHB five-level inverters is addressed in Section
If S3 is turned on, the output voltage of the qBI module 1 is –
III. Simulation results are shown in Section IV. The
VC1. Else, it equals zero. The inductor L1 is charged from the
experimental results are presented in Section V.
source. We have:
di L
L1 = V dc 1 .
1
(1)
dt

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In the ST state 2, S3 and S4 are turned on as shown in Fig. 3(b).

Da1 is blocking, while Db1 is conducting. If S2 are turned on, the
output voltage of the qBI module 1 is –VC1. Else, it equals zero.
The inductor L1 is also charged in this state, and its voltage is
calculated as (1).
In the non-shoot-through (NST) state 1, as shown in Fig. 3(c),
both S1 and S3 are turned on. In the NST state 4, as shown in
Fig. 3(f), both S2 and S4 are turned on. The output voltage of the
qBI module 1 in both NST states 1 and 4 is zero.
In the NST state 2, as shown in Fig. 3(d), both S2 and S3 are
turned on. The output voltage of the qBI module 1 is –VC1.
In the NST state 3, as shown in Fig. 3(e), both S1 and S4 are
turned on. The output voltage of the qBI module 1 is VC1.
During the non-shoot-through (NST) states as shown in Figs.
3(c)–3(f), Da1 and Db1 are conducting. The capacitor C1 is
charged from Vdc, while the inductor L1 transfers energy from
the DC voltage source to the main circuit. The H-bridge circuit
is equivalent as a current source, iPN1. We get:
diL
L1 = Vdc1 - VC1 .
1
(2)
dt
In one switching period, T, each leg has twice short circuits
alternatively. From (1) and (2), the average inductor voltage is
æ T ö T
V L1 = çç1 - 2 0 ÷÷(Vdc1 - VC 1 ) + 2 0 Vdc1 , (3)
çè T ÷ø T
where T0/T = D1 is a ST duty ratio in each leg of module 1; T0 is
total ST time intervals in one leg.
In a steady state, the average inductor voltage should be zero.
We get:
1 1 (4)
VC1  Vdc1  Vdc1 .
1  2T0 / T 1  2 D1
Similarly, we also obtain the capacitor voltage on the module
2 as
1 (5)
VC 2  Vdc 2 .
1  2 D2 Fig. 4. PWM scheme for the proposed qCHB-FLBI.
B. PWM Scheme for the Proposed Inverter
Fig. 4 shows a phase-shifted sinusoidal pulse-width Because the number of the ST states in the proposed
modulation (PS-SPWM) strategy for the proposed qCHB-FLBI in one switching period is four as shown in Fig. 4,
qCHB-FLBI. For module 1, two control voltages, -v con tr ol and the operating frequency of the inductors in the proposed
v con trol are compared to a high-frequency triangle voltage, V tr i1 , inverter is fourfold the switching frequency. In the CHB-qZSI,
to produce control signals for the S 1 and S 2 switches. Two DC the operating frequency of the inductors is twofold the
voltages, V SH and -V SH , are compared to V tr i1 to produce the switching frequency. Therefore, the high-frequency current
S 0 a control signal. Then S 0 a is added to the control signals of ripple on inductors of the proposed qCHB-FLBI is a half that of
switches S 1 and S 2 to produce the ST states. Likewise, the V tr i1 the CHB-qZSI.
is shifted in 90° to create another high-frequency triangle
C. Solving Unbalanced DC Source Problem in the
voltage, V tri2 . v con trol and -v con trol are compared to V tr i2 to
Proposed Inverter
produce control signals for the S 3 and S 4 switches. V SH and
-V SH are compared to the V tr i2 to produce a S 0 b control signal. In order to achieve a good quality of the output voltage as
The S 0b is then added to the control signals of switches S 3 and shown in Fig. 4, the capacitor voltage in each module must be
S 4 to produce the ST states. As a result, the output voltage vab of the same. From (4) and (5), the ST duty cycles D1 and D2 in
H-bridge module 1 has three levels. each module are used to control the capacitor voltages VC1 and
Similar for the second H-bridge module, two control voltages VC2, respectively. When the DC input voltage in each module is
(v contr ol and -v con tr ol ) are shifted in 180° to produce the output unbalanced, D1 is different from D2 to keep VC1 = VC2. The
voltage vcb of the H-bridge module 2. The output voltage vac of difference between D1 and D2 results in generating the DC
the cascaded system is a subtraction of vab and vcb. Therefore, offset at the output voltage. To remove the DC offset of the
the output voltage of the proposed qCHB-FLBI produces five output voltage, a capacitor Cd is added to the output of the
levels as shown in Fig. 4. proposed inverter. Fig. 5 shows the proposed inverter under
unbalanced DC source condition, where the capacitor Cd is

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L1 P1 TABLE I
Db1 COMPARISON BETWEEN THE PROPOSED QCHB-FLBI AND THE
CONVENTIONAL FIVE-LEVEL INVERTERS
S3 S1 qCHB-FLBI CHB-qZSI CHB-BFLI
Vdc1
Number of inductors 2 4 2
Lf io Number of capacitors 3 4 2
b1 a
C1 VC1 Number of diodes 12 10 12
S4 S2 Number of switches 8 8 10
Shoot-through immunity Yes Yes No
N1 Da1 Input current Continuous Continuous Continuous
Inductor frequency 4fs 2fs fB
where fs and fB are the switching frequency of the H-bridge circuit and the
Cd Vcd R vo switching frequency of the boost DC-DC converter, respectively.

L2 P2 TABLE II
Db2 VOLTAGE STRESSES OF THE PROPOSED QCHB-FLBI AND CHB-qZSI
Proposed inverter CHB-qZSI
S7 S5
Vdc2 1 1- D1
VC1 Vdc1 Vdc1
1- 2D1 1- 2D1
c
b2 C2 VC2 1 D1
VC2 Vdc 2 Vdc1
S8 S6 1- 2D2 1- 2D1
Capacitor voltage 1- D2
N2 Da2 VC3 Not appear Vdc 2
1- 2D2
Fig. 5. Proposed qCHB-FLBI with filter capacitor. D2
VC4 Not appear Vdc 2
1- 2D2
connected between b1 and b2 nodes to filter the DC component VCd ( D1 - D2 ).VC Not appear
at the output. Assuming Vc = VC1 = VC2, the DC offset voltage is 1 1
calculated as Diode voltage stress Vdc Vdc
1- 2D 1- 2D
D1 D2
Vcd = Vdc1 - Vdc 2 = ( D1 - D2 )⋅VC . (6) 1
Vdc1
1
Vdc1
1 - 2 D1 1 - 2 D2 S1-S4
Switch voltage 1- 2D1 1- 2D1
Because the subtraction between D1 and D2 is too small, the stress 1 1
voltage stress on Cd is very low. Therefore, the effect the size S5 - S8 Vdc 2 Vdc 2
1- 2D2 1- 2D2
and cost of the capacitor Cd to overall cascaded system is
trivial. Note that the current rating of capacitor Cd should carry TABLE III
the entire load current during operation of the circuit. SIMULATION AND EXPERIMENT PARAMETERS
Parameters Values
III. COMPARISION WITH CONVENTIONAL CHB INVERTERS Power rating 1.2 kVA
Inverter output voltage 110 Vrms
Table I compares the passive and active components of the Output frequency 50 Hz
CHB-qZSI, the cascaded H-bridge boost-five-level inverter Inductors (L1, L2 ) 2 mH
(CHB-BFLI) and the proposed qCHB-FLBI. In comparison C1, C2 4.4 mF/ 200 V
Capacitors
Cd 4.7 mF/ 25 V
with the CHB-qZSI [15] as shown in Fig. 1(b), the proposed Inductor (Lf) 3 mH
qCHB-FLBI in Fig. 5 uses one less capacitor, two less load
Resistor (R) 40 Ω
inductors, and two more diodes. Compared with the CHB-BFLI Switching frequency (fs) 10 KHz
[12] as shown in Fig. 1(a), the proposed inverter uses two less
switches and one more capacitor. However, the CHB-BFLI has
a shoot-through problem. The operating frequency of the IV. SIMULATION RESULTS
inductors in the proposed inverter is fourfold the switching
In order to test the operating principle of the proposed
frequency of the H-bridge circuit, while it is twofold in the
qCHB-FLBI as shown in Fig. 5, PSIM simulation is used. Table
CHB-qZSI. Therefore, the high-frequency current ripple on
III provides a list of the simulation parameters for the proposed
inductors of the proposed qCHB-FLBI is a half that of the
qCHB-FLBI. The ON-resistance of all switches is set to 0.27 Ω
CHB-qZSI.
in the simulation.
Because the CHB-qZSI has the same feature in shoot-through
Fist, we set Vdc1 = Vdc2 = 50 V to confirm the properties of the
immunity as the proposed qCHB-FLBI, the voltage stress
proposed inverter under balanced DC-source condition. Fig. 6
comparison between two inverters is addressed. Table II
shows the simulation results for the proposed qCHB-FLBI
compares the governing equations of the proposed qCHB-FLBI
when both input voltages are the same. As shown in Fig. 6(a),
to the CHB-qZSI. As shown in Table II, the capacitor voltages
the output voltage of the proposed inverter has five levels; and
of the proposed inverter are higher than those of the CHB-qZSI.
the load voltage is 110 Vrms. From Fig. 6(a), we can see that
However, total capacitor voltage stresses in each module of
both the capacitor C1 and C2 voltages are boosted to 116 V in
both inverters are the same. The voltage stress on diodes and
the steady state and the peak-to-peak voltage on C1 and C2
switches of the proposed inverter equals to that of the
CHB-qZSI.

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(a) (b)
(c) (d)
Fig. 6. Simulation results when Vdc1 = Vdc2 = 50 V. From top to bottom:
(a) five-level output voltage, load and inductor currents, VC1, VC2, Vdc1
and Vdc2, (b) inductor currents, capacitor voltages, DC-link and diode
Da1 voltages of module 1, DC-link and diode Da2 voltages of module 2,
(c) harmonic spectrum of five-level output voltage, and (d) harmonic
spectrum of load current.
capacitors is 9 V. The DC-link voltage of each module is the
square waveform as shown in Fig. 6(b).
Next, we increase the input voltage of module 2 (Vdc2) to 60V,
while Vdc1 = 50V to test the properties of the proposed inverter
under unbalanced DC-source condition. Fig. 7 shows the
simulation results for the proposed qCHB-FLBI when Vdc1 = 50
V and Vdc2 = 60 V. As shown in Fig. 7(a), the output voltage of
the proposed inverter has five levels and the load voltage is 110
Vrms. From Fig. 7(a), we can see that both the capacitor C1 and
C2 voltages are also boosted to 116 V in the steady state, and the
peak-to-peak voltage on C1 and C2 capacitors are 9 V. As
shown in Fig. 7(a), the average value of the capacitor Cd filter
voltage is very low, about 6 V. Therefore, the size of capacitor
filter Cd is pretty small and it does not affect the total size and
weight of proposed inverter. The dc-link voltage of each
module is the square waveform as shown in Fig. 7(b). Because
the ST duty cycle of module 1 is higher than that of module 2,
the five-level output voltage has a high distortion in the positive
half cycle as shown in Fig. 7(a). On the contrary, the five-level
output voltage has a high distortion in the negative half cycle
when the ST duty cycle of module 1 is lower than that of
module 2.
Table IV compares the simulated THD of the output current
between the CHB-qZSI and the proposed qCHB-FLBI. The
same parameters as the proposed inverter were used to simulate
the CHB-qZSI. From Table IV, we can observe that the THD of
the output current of the proposed inverter is lower than that of
the CHB-qZSI.
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(a) (b)
(c) (d)
Fig. 7. Simulation results when Vdc1 = 50 V and Vdc2 = 60 V. From top to
bottom: (a) five-level output voltage, load and inductor currents, VC1,
VC2, Vdc1, Vdc2 and VCd, (b) five-level output voltage, inductor currents,
capacitor voltages, DC-link and diode Da1 voltages of module 1, DC-link
and diode Da2 voltages of module 2, (c) harmonic spectrum of five-level
output voltage, and (d) harmonic spectrum of load current.
TABLE IV
THD OF OUTPUT CURRENT
Simulated qCHB-FLBI
CHB-qZSI Sim. Exp.
THDio when Vdc1 = Vdc2 = 50 V 3.1% 1.0% 1.5%
THDio when Vdc1 = 50 V, Vdc2 = 60 V 2.5% 1.1% 1.8%
Similar to the single-phase inverters in [15], [16] and [26], the
proposed single-phase qCHB-FLBI also introduces the
low-frequency ripples in the capacitor voltage and inductor
current as shown in Figs. 6 and 7. The low-frequency
oscillation at the DC side can be efficiently mitigated by using a
current feedback control method as presented in [28], [29].
V. EXPERIMENTAL RESULTS
A 1.2-kVA prototype was constructed in the laboratory to
verify the properties of the proposed qCHB-FLBI in Fig. 5. Fig.
8 shows an implementation photo of the proposed inverter. Fig.
9 shows a gating signal generation circuit based on
TMS320F28335 DSP. Eight IRFP460 MOSFETs were
controlled by insulated TLP250 amplifiers. Four DSEI60-06A
diodes were used in the proposed inverter. The inductance of L1
and L2 is 2 mH. Two 200-V/2200-µF capacitors are connected
in parallel to obtain 4400-µF capacitance of capacitors C1 and
C2 as shown in Fig. 8, while the Cd capacitor is 4.7 mF/ 25 V.
The filter inductor is 3 mH, and the resistor load is 40 Ω. The
switching frequency is 10 kHz. The Vdc1 and Vdc2 input voltages
are varied from 50 V to 60 V, while the AC output voltage is
110 V in RMS. Two separate sources (Vdc1 and Vdc2) were
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Fig. 8. Implementation photo of the proposed inverter.

S1
Card DSP OR
TMS28F335 NOT
‐Vsh1
S2
OR
OR

+Vsh1

Mi
0
-Mi
180° delay
1 S3
0 OR
-1 T
90° delay NOT
‐Vsh1
S4
OR
OR

+Vsh1

S5
180° delay OR
NOT
‐Vsh2
S6
OR
OR

+Vsh2
Fig. 10. Experimental results of the proposed inverter when Vdc1 = Vdc2
S7 = 50 V. From top to bottom; (a) five-level output voltage and load
OR current; (b) VC2, VC1, Vdc2, and Vdc1; (c)(e) inductor currents; (d) DC-link
90° delay NOT voltage of module 1, diode Da1 voltage of module 1, DC-link voltage of
‐Vsh2 module 2 and diode Da2 voltage of module 2; and (f)-(h) harmonic
S8 spectrum at the output.
OR
OR

+Vsh2
VC1 1 +Vsh1 A. Case 1: Vdc1 = Vdc2 = 50 V
VC_ref D1
PID ‐1 ‐Vsh1 Fig. 10 shows the experimental results for the proposed
D2
Limiter
qCHB-FLBI when both input voltages are the same. The output
PID ‐1 ‐Vsh2
voltage of the proposed qCHB-FLBI has five levels and the
VC2 Limiter 1 +Vsh2
measured load voltage is 110 Vrms. In the steady state, the
Fig. 9. Gating signal generation circuit with capacitor voltage controller. measured capacitor C1, C2 and Cd voltages are 129 V, 129 V and
0 V, respectively. The peak-to-peak voltages on capacitor C1
and C2 are 8 V. The dc-link voltage of each module is the
generated as follows. A three-phase step-down transformer was square waveform as shown in Fig. 10(d). The measured THD
connected to a 220/380-V utility grid. Two of three output values of the output voltage and current are 1.2% and 1.5%,
voltages of the transformer were used to generate two separate respectively.
DC voltages through a single-phase diode rectifier and a filter
capacitor. The experiment parameters are also shown in Table B. Case 2: Vdc1 = 50 V and Vdc2 = 60 V
III. Fig. 11 shows the experimental results of the proposed
Experiment results are measured on the TPS 2024B and qCHB-FLBI under unbalanced DC source condition (Vdc1 = 50
MSO2024B Tektronix electronic oscilloscopes, and Hioki V and Vdc2 = 60 V). The proposed qCHB-FLBI produces
3197 power quality analyzer. The current waveforms are five-level voltage at the output, and the measured load voltage
measured through the current transducer (LEM LA 25-P). is 110 Vrms. In the steady state, the measured capacitor C1, C2
and Cd voltages are 129 V, 129 V and 7 V, respectively. The
peak-to-peak voltages on capacitor C1 and C2 are 8 V. The

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Fig. 12. Experimental results of the proposed inverter when (a),(b) Vdc2
Fig. 11. Experimental results of the proposed inverter when Vdc1 = 50V is changed from 50 V to 60 V, and (c) Vdc1 is changed from 50 V to 60 V.
and Vdc2 = 60V. From top to bottom; (a) VC2, VC1, Vdc2, and Vdc1; (b)
DC-link voltage of module 1, diode Da1 voltage of module 1, DC-link
voltage of module 2 and diode Da2 voltage of module 2; (c) capacitor Cd
voltage; (d) five-level output voltage and load current; (e)-(f) inductor
currents; and (g)-(i) harmonic spectrum at the output.

DC-link voltage of each module is the square waveform as

shown in Fig. 11(d). The measured THD values of the output
voltage and current are 1.3% and 1.8%, respectively. The
results in the experiment are identical to those in the simulation.
Table IV also shows the comparison between the simulated
and measured THD values of the output current. The
experimented THD of the output current is higher than
simulated value. Note that the THD value of the output voltage
and current in Figs. 10(f) and 11(g) is measured upto 50th
hamonics by Hioki 3197 power quality analyzer.
C. Dynamic Response
A simple proportional–integral–derivative (PID) controller is
Fig. 13.Experimental results of the proposed inverter with (a) resistor
used to control the capacitor voltage of each module. A block load change from 12 Ω to 22 Ω, and (b) resistor load change from 40 Ω
diagram of the capacitor voltage controller is shown in Fig. 9. to 12 Ω.
The sensing capacitor voltage of each module is compared to
the reference value. The output error of the comparator is
entered into the PID controller. Then, the PID controller output can see from Fig. 12(a) that the capacitor C2 voltage of module
produces the control value of shoot-through duty cycle. A 2 is kept constant at 129 V when Vdc1 = 50 V and the input
limiter is used to ensure the shoot-through duty cycle in range voltage of module 2 suddenly changes from 50 V to 60 V. From
of [0.2, 0.35]. The modulation index is fixed at 0.65. Figs. 12(b) and 12 (c), the output current is unchanged, despite
Fig. 12 shows the dynamic response of the proposed system the change in the input voltages.
with input voltage change. In Figs. 12 (a) and 12(b), the input Fig. 13(a) shows the dynamic response of the proposed
voltage of module 2 is changed from 50 V to 60 V, while the system when the resistor load is changed from 12 Ω to 22 Ω.
input voltage of module 1 is maintained at 50 V. In Fig. 12 (c), Fig. 13(b) shows the dynamic response of the proposed system
the input voltage of module 1 is changed from 50 V to 60 V, when the resistor load is changed from 40 Ω to 12 Ω. As shown
while the input voltage of module 2 is maintained at 50 V. We in Fig. 13, the output voltage and the capacitor voltages are

0278-0046 (c) 2016 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TIE.2017.2701770, IEEE
Transactions on Industrial Electronics
IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS
Fig. 14. Experimental results of the proposed inverter with (a) RL load
of 20 Ω and 40 mH, and (b) non-linear load of 100 Ω and 1000 µF.
(a) (b)
Fig. 15. (a) Power loss comparison at 1 kW and (b) calculated
efficiency comparison at the different power level between the
CHB-qZSI and the proposed inverter when Vdc1 = Vdc2 = 50 V.
respectively maintained almost constant at 110 Vrms and 129 V
during the load step change.
Fig. 14(a) shows the experimental results of the proposed
inverter with a RL load (R = 20 Ω and Lf = 40 mH). Fig. 14(b)
shows the experimental results of the proposed inverter with a
non-linear load. The non-linear load is a combination of a
full-bridge diode rectifier, a capacitor of 1000 µF and a resistor
of 100 Ω.
Fig. 15 (a) compares the loss breakdown in the components
between the CHB-qZSI and the proposed inverter when Vdc1 =
Vdc2 = 50 V, Po = 1 kW, fs = 10 kHz and Vo = 110 VRMS. The
power loss calculation of both inverters follows as [16]. Table
V shows the parameters of the CHB-qZSI and the proposed
qCHB-FLBI for the power loss calculation. Because the
CHB-qZSI uses four inductors, the core and copper losses of
the inductor in the CHB-qZSI are significant. Fig. 15(b) shows
the calculated efficiency comparison at the different power
level between the CHB-qZSI and the proposed inverter when
Vdc1 = Vdc2 = 50 V, fs = 10 kHz and Vo = 110 VRMS. As shown in
Fig. 15, the efficiency of the proposed qCHB-FLBI is higher
than that of the CHB-qZSI.
0278-0046 (c) 2016 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
TABLE V
PARAMETERS FOR POWER LOSS CALCULATION
CHB-qZSI Proposed Inverter
Diodes STPS60SM200C 200 V, 30 A, rD = 10 mΩ
MOSFETs IRFP4668PbF 200 V, 130 A, rS = 8 mΩ
Parasitic resistance of inductors 0.12 Ω
Inductor core CM778125 (178 nH/N2)
ESR of C1-2 capacitors at 200VDC 22 mΩ (4400 µF)
ESR of Cd capacitor at 25VDC – 0.12 Ω (4.7 mF)
Output voltages 110 VRMS
Output power 1 kW
VI. CONCLUSION
A new single-phase single-stage CHB five-level inverter with
boost voltage ability has been proposed in this paper. The
proposed inverter has the following main features as: five-level
output voltage, reduction in number of passive components and
shoot-through immunity. With the simple PID controller, a
constant capacitor voltage can be achieved with an excellent
transient performance which enhances the rejection of
disturbance, including the input voltage and load current
variations. Also, circuit analysis and PWM control strategy for
the proposed system are shown. Simulation and experimental
results are shown to verify the validity of the proposed
qCHB-FLBI.
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IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS

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