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REPORT
ON
Dual Edge Triggered D Flip Flop using C²MOS
(VLSI Design Project)
Under the guidance
Of
Mr. Kavindra Kandpal

Submitted by:
1. Abhilash Rai
M.E Microelectronics
ID: 2018H1230242P
2. Avinash Baldi
M.E Communication
ID: 2018H1240097P
3. Piyush Ahuja
M.E Microelectronics
ID: 2018H1230248P
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Table of Content
Problem Statement
Introduction
Timing and Characteristics of Flip Flop
Dual Edge Triggered D Flip Flop using C2MOS
Schematics and Simulation
Timing and Power Analysis
Static Power Calculations
Simulation Graph
Setup Time Graph
Application of D Flip Flop
Schematic of Application
SISO Timing Analysis
References
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List of Figures
1.Symbol of D Flip Flop
2.Truth Table of D Flip Flop
3. Setup and Hold Time
4. Propagation Delay
5. Dual Edge Triggered D Flip Flop using C2MOS
7. Delay Calculation for ss
8. Delay Calculation for ff
9. Delay Calculation for tt
10. Setup time for ss
11. Setup time for ff
12. Setup time for tt
13. SISO Shift Register
14. Schematic of SISO
15. SISO Timing Graph
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PROBLEM STATEMENT
Implement C2MOS Dual Edge Triggered D Flip Flop. Compute its Set up and Hold
Time. Optimize the design for minimum delay.
Abstract
In this design TSMC 180nm technology is used. This report comprises of analysis of
Dual Edge Triggered D Flip Flop with C2MOS, with their application in Shift
Registers.
The report mainly focuses mainly on Time Delay parameter.

TOOL USED
Cadence virtuoso tool.
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Introduction
Flip Flops or the data storage elements are almost an essential component of every
sequential circuitry. Among various flip-flops, D flip-flop is commonly used. It
captures the value of the D input at a particular predefined portion of the clock
pulse (rising or falling edge of the clock) and its output is not affected at other parts
of the clock. From the timing perspective, delay produced by flip-flops consumes a
large part of the cycle time while the operating frequency increases. The ‘D’ in D
flip flop stands for "data". This flip-flop stores a 1 bit value that is on the data line.
It can be thought of as a basic memory unit. D flip-flop can be built using NAND
gates or with NOR gates. The major applications of D flip-flop are to introduce
delay in timing circuits, as a buffer and as building blocks for shift registers.
The symbol of a D flip flop is shown in Figure 1.1.

Figure 1: Symbol of a D flip flop

The truth table of a D flip flop is shown in Figure 1.2.

Figure 2: Truth table of a D flip flop.

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The operation of the D type flip-flop is as follows: Any input appearing (present
state) at the input D, will be produced at the output Q in time t+1 (next state) on
encountering either the positive edge or negative edge of the clock as per the
design. The D-flip flop just transfers the input to the output on the ACTIVE
(positive/negative) edge of the clock.

This report investigates delay characteristics of dual edge triggered D Flip Flop
using C²MOS in Master Slave configuration. A dual edge-triggered (DET) flip-
flop has half the clock frequency and twice the activity factor, so the energy
consumed in the flip-flop is unchanged.
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TIMING CHARACTERISTICS OF FLIP FLOPS

A common feature among clocked registers is the use of a common synchronizing
signal, namely the clock signal, to control the timing of the data storage process.
Data is successfully stored within a register if the following timing constraints
between the input data signal and the clock signal are satisfied:

A. Setup time:
This determines the minimum time that the value of the data signal should be
valid before the arrival of a latching clock signal.
B. Hold time:
That specifies the minimum time that the data signal should remain at a constant
value after data storage is enabled by the clock signal.

Figure 3: Setup and Hold Time

C. Propagation delay:
It is defined as the delay between a latching event of the clock signal and the
time of latched data is available at the output Q/QN of a register.

Figure 4: Propagation delay

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Dual Edge Triggered D FF using C²MOS:

When clock is high, the positive latch composed of transistors M1-M4 is sampling
the inverted D input on node X. Node Y is held stable, since devices M9 and M10
are turned off. On the falling edge of the clock, the top slave latch M5-M8 turns on,
and drives the inverted value of X to the Q output. During the low phase, the bottom
master latch (M1, M4, M9, M10) is turned on, sampling the inverted D input on
node Y. Note that the devices M1 and M4 are reused, reducing the load on the D
input. On the rising edge, the bottom slave latch conducts, and drives the inverted
version of Y on node Q. Data hence changes on both edges. Note that the slave
latches operate in a complementary fashion i.e. only one of them is turned on during
each phase of the clock.

Figure 5: Dual Edge Triggered D FF using C²MOS

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Schematic and Simulation

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Timing and Power Analysis

Clock Period: 1.5µs
1. ss

Timing Characteristics Time(in nanoseconds)

Setup Time 160
Hold Time 0
tPHL 8.2
tPLH 8.7
Delay Time((tPLH +tPHL)/2) 8.45
Dynamic Power Dissipation: 0.2044µW

2. ff

Timing Characteristics Time(in nanoseconds)

Setup Time 120
Hold Time 0
tPHL 6.8
tPLH 7
Delay Time((tPLH +tPHL)/2) 6.9
Dynamic Power Dissipation: 0.19876µW

3. tt

Timing Characteristics Time(in nanoseconds)

Setup Time 150
Hold Time 0
tPHL 7.5
tPLH 7
Delay Time((tPLH +tPHL)/2) 7.25
Dynamic Power Dissipation: 0.2030µW
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Satic power Calculations

The static power is calculated at each of the 4 possible stable states of

operation(namely at CLK=0 D=0, CLK=0 D=1, CLK=1 D=0 and CLK=1 D=1) of
the D-flip flop.

D Input Clk Static Power(in nanowatts)

0 0 2.86
0 1 2.53
1 0 4.2984
1 1 5.292
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Simulation Graphs

Figure 7: Delay calculation for ss

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Figure 8: Delay calculation for ff

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Figure 9: Delay calculation for tt

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Setup Time Graphs

Figure 10: Setup time for ss

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Figure 11: Setup time for ff

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Figure 12: Setup time for tt

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Application of Dual Edge triggered D Flip Flop

SHIFT REGISTER
A shift register is a cascade of flip flops, sharing the same clock, in which the
output of each flip-flop is connected to the 'data' input of the next flip-flop in the
chain, resulting in a circuit that shifts by one position the 'bit array' stored in it,
'shifting in' the data present at its input and 'shifting out' the last bit in the array, at
each transition of the clock input.

Shift registers can have both parallel and serial inputs and outputs.
 Serial-in to Parallel-out (SIPO) - the register is loaded with serial data, one
bit at a time, with the stored data being available at the output in parallel form.
 Serial-in to Serial-out (SISO) - the data is shifted serially “IN” and “OUT”
of the register, one bit at a time in either a left or right direction under clock
control.
 Parallel-in to Serial-out (PISO) - the parallel data is loaded into the register
simultaneously and is shifted out of the register serially one bit at a time under
clock control.
 Parallel-in to Parallel-out (PIPO) - the parallel data is loaded
simultaneously into the register, and transferred together to their respective
outputs by the same clock pulse

We had made SISO Application using Dual Edge triggered D Flip Flop.

Figure 13: SISO Shift Register

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Schematic of Application

Figure 14: Schematic for SISO

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SISO Timing Analysis

Figure 15: SISO Timing Analysis

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References

1. Digital Integrated Circuits: A Design Perspective Author: Jan Rabey , Prentice Hall, 2005.
2. CMOS Digital Integrated Circuit, Analysis and Design, Sung-Mo Kang and Yusuf Leblebici,
Publisher: McGraw- Hill Companies, Inc.2003.
3. J. Yuan and C. Svensson, “High-speed CMOS circuit techniques,” IEEE J. Solid-State
Circuits, vol. 24, no.1, pp. 62–70, Feb. 1989.
4. https://www.tme.eu/en/details/74vhct573aftbe/latches/toshiba/74vhct573aftbe/
5. Comparative Analysis of D Flip-Flops in Terms of Delay and its Variability, IEEE(no. 7359339)
https://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=7359339