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SCAS285AA – MARCH 1993 – REVISED JUNE 2015

SNx4LVC14A Hex Schmitt-Trigger Inverters

1

Features

1

Operate From 1.65 V to 3.6 V V CC

Specified From – 40° C to 85 ° C, –40° C to 125 ° C, and –55° C to 125 ° C

Inputs Accept Voltages to 5.5 V

Max t pd of 6.4 ns at 3.3 V

Typical V OLP (Output Ground Bounce) <0.8 V at V CC = 3.3 V, T A = 25 ° C

Typical V OHV (Output V OH Undershoot) >2 V at V CC = 3.3 V, T A = 25 ° C

I off Support Live Insertion,

Partial-Power-Down

Mode and Back Drive protection

On Products Compliant to MIL-PRF-38535, All Parameters Are Tested Unless Otherwise Noted. On All Other Products, Production Processing Does Not Necessarily Include Testing of All Parameters.

Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II

ESD Protection Exceeds JESD 22

– 2000-V Human-Body Model (A114-A)

– 200-V Machine Model (A115-A)

– 1000-V Charged-Device Model (C101)

2

Applications

Barcode Scanner

Cable Solutions

E-Books

Embedded PCs

Field Transmitter: Temperature or Pressure Sensors

Fingerprint Biometrics

HVAC: Heating, Ventilating, and Air Conditioning

Network-Attached Storage (NAS)

Server Motherboard and PSU

Software Defined Radio (SDR)

TV: High Definition (HDTV), LCD, and Digital

Video Communications Systems

Wireless Data Access Cards, Headsets, Keyboards, Mice, and LAN Cards

1

3 Description

The SN54LVC14A hex Schmitt-trigger inverter is designed for 2.7-V to 3.6-V V CC operation, and the SN74LVC14A hex Schmitt-trigger inverter is designed for 1.65-V to 3.6-V V CC operation.

The devices contain six independent inverters and perform the Boolean function Y = A.

Inputs can be driven from either 3.3-V or 5-V devices.

This feature

allows the use of these devices as

translators

in

a

mixed

3.3-V

or

5-V system

environment.

Device Information (1)

PART NUMBER

PACKAGE

BODY SIZE (NOM)

 

LCCC (20)

8.90

mm × 8.90 mm

SN54LVC14A

CDIP (14)

20.00

mm × 7.00 mm

CFP (14)

9.21

mm × 6.30 mm

 

SO (14)

10.20

mm × 5.30 mm

SOIC (14)

8.65

mm × 6.00 mm

SSOP (14)

6.20

mm × 5.30 mm

SN74LVC14A

TSSOP (14)

5.00

mm × 4.40 mm

TVSOP (14)

4.40

mm × 3.60 mm

VQFN (14)

3.50

mm × 3.50 mm

(1) For all available packages, see the orderable addendum at the end of the data sheet.

Logic Diagram (Positive Logic)

A

the end of the data sheet. Logic Diagram (Positive Logic) A Y An IMPORTANT NOTICE at
the end of the data sheet. Logic Diagram (Positive Logic) A Y An IMPORTANT NOTICE at

Y

SCAS285AA – MARCH 1993 – REVISED JUNE 2015

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SN54LVC14A , SN74LVC14A SCAS285AA – MARCH 1993 – REVISED JUNE 2015 www.ti.com

1

Features

Table of Contents

1

9 Detailed Description

11

 

2 Applications

1

9.1 Overview

11

3 Description

1

9.2 Functional Block Diagram

11

4 Revision History

2

9.3 Feature Description

11

5 Device Options

3

9.4 Device Functional Modes

11

6 Pin Configuration and Functions

4

10

Application and Implementation

12

7 Specifications

5

10.1

12

7.1 Absolute Maximum Ratings

5

11

10.2

Application Information Typical Application

Power Supply Recommendations Layout

12

14

7.2 ESD Ratings

5

7.3 Recommended Operating Conditions, SN54LVC14A

12

14

 

5

12.1

Layout Guidelines

14

 

7.4 Recommended Operating Conditions, SN74LVC14A

 

12.2

Layout Examples

14

 

6

13

Device and Documentation Support

15

 

7.5 Thermal Information

6

13.1

Related Links Community Resources Trademarks Electrostatic Discharge Caution Glossary

15

7.6 Electrical Characteristics, SN54LVC14A

6

13.2

15

7.7 Electrical Characteristics, SN74LVC14A

7

13.3

15

7.8 Switching Characteristics, SN54LVC14A

8

13.4

15

7.9 Switching Characteristics, SN74LVC14A

8

13.5

15

7.10 Operating Characteristics

9

14

Mechanical, Packaging, and Orderable Information

7.11 Typical Characteristics

9

15

8 Parameter Measurement Information

10

4

Revision History

 

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

 

Changes from Revision Z (January 2014) to Revision AA

 

Page

• Added Applications, Device Information table, Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional Modes , Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section

1

• Moved T stg to Absolute Maximum Ratings

 

5

Changes from Revision Y (October 2010) to Revision Z

 

Page

Updated document to new TI data sheet

 

1

Updated

Features

1

Added Military Disclaimer to Features list

 

1

2

Copyright © 1993– 2015, Texas Instruments Incorporated

Product Folder Links: SN54LVC14A SN74LVC14A

www.ti.com SN54LVC14A , SN74LVC14A SCAS285AA – MARCH 1993 – REVISED JUNE 2015
www.ti.com SN54LVC14A , SN74LVC14A SCAS285AA – MARCH 1993 – REVISED JUNE 2015

SCAS285AA – MARCH 1993 – REVISED JUNE 2015

5 Device Options

PART NUMBER

PACKAGE

 

BODY SIZE (NOM)

SN54LVC14AFK

LCCC (20)

8.90

mm × 8.90 mm

SN54LVC14AJ

CDIP (14)

20.00

mm × 7.00 mm

SN54LVC14AW

CFP (14)

9.21

mm × 6.30 mm

SN74LVC14ANSR

SO (14)

10.20

mm × 5.30 mm

SN74LVC14ADR

   

SN74LVC14ADT

SOIC (14)

8.65

mm × 6.00 mm

SN74LVC14ADBR

SSOP (14)

6.20

mm × 5.30 mm

SN74LVC14APWR

   

SN74LVC14APWT

TSSOP (14)

5.00

mm × 4.40 mm

SN74LVC14ADGVR

TVSOP (14)

4.40

mm × 3.60 mm

SN74LVC14ARGYR

VQFN (14)

3.50

mm × 3.50 mm

Copyright © 1993– 2015, Texas Instruments Incorporated

Product Folder Links: SN54LVC14A SN74LVC14A

3

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V CC

1A

4Y

GND

V CC

1A
NC

6A

1Y

4A

4Y

3Y

NC

GND

6 Pin Configuration and Functions

D, DB, DGV, NS, J, W, or PW Package 14-Pin SOIC, TVSOP, SSOP, SOP, CDIP, or TSSOP Top View

1A

1Y

2A

2Y

3A

3Y

GND

1 14 2 13 3 12 4 11 5 10 6 9 7 8
1 14
2 13
3 12
4 11
5 10
6 9
7 8

V CC

6A

6Y

5A

5Y

4A

4Y

FK Package

20-Pin LCCC

Top View

2A

NC

2Y

NC

3A

3 2 1 20 19 18 17 16 15 14 9 10 11 12 13
3
2
1
20 19
18
17
16
15
14
9
10
11 12
13

4 6Y

5 NC

6 5A

7 NC

8 5Y

Pin Functions

RGY Package

14-Pin VQFN

Top View

   

1

14

 

1Y

2 13

 

6A

2A

3 12

6Y

2Y

4 11

5A

3A

5 10

5Y

3Y

6 9

4A

7

8

 

PIN

   
 

SOIC, TVSOP,

 

NAME

 

SSOP, SOP,

LCCC

I/O

DESCRIPTION

CDIP, TSSOP,

 

VQFN

 

1A

 

1

2

I

Data Input

2A

 

3

4

I

Data Input

3A

 

5

8

I

Data Input

4A

 

9

13

I

Data Input

5A

 

11

16

I

Data Input

6A

 

13

19

I

Data Input

GND

 

7

10

Ground

V

CC

14

20

Power

1Y

 

2

3

O

Data Output

2Y

 

4

6

O

Data Output

3Y

 

6

9

O

Data Output

4Y

 

8

12

O

Data Output

5Y

 

10

14

O

Data Output

6Y

 

12

18

O

Data Output

4

 

Copyright © 1993– 2015, Texas Instruments Incorporated

Product Folder Links: SN54LVC14A SN74LVC14A

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SCAS285AA – MARCH 1993 – REVISED JUNE 2015

Pin Functions (continued)

PIN SOIC, TVSOP, I/O DESCRIPTION SSOP, SOP, NAME LCCC CDIP, TSSOP, VQFN
PIN
SOIC, TVSOP,
I/O
DESCRIPTION
SSOP, SOP,
NAME
LCCC
CDIP, TSSOP,
VQFN

1

5

7

NC

11

No Connect

15

17

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) (1)

 

MIN

MAX

UNIT

V CC

Supply voltage

–0.5

6.5

 

V

V I

Input voltage (2)

–0.5

6.5

 

V

V O

Output voltage (2) (3)

–0.5

V CC + 0.5

 

V

I IK

Input clamp current

V I < 0

 

–50

mA

I OK

Output clamp current

V O < 0

 

–50

mA

I O

Continuous output current

 

±50

mA

 

Continuous current through V CC or GND

 

±100

mA

P tot

Power dissipation

T A = – 40 ° C to 125 ° C (4) (5)

 

500

mW

T stg

Storage temperature

 

–65

150

°

C

(1)

Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

(2)

only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.

(3)

The value of V CC is provided in the Recommended Operating Conditions table.

(4)

For the D package: above 70° C, the value of P tot derates linearly with 8 mW/K.

(5)

For the DB, DGV, NS, and PW packages: above 60° C, the value of P tot derates linearly with 5.5 mW/K.

7.2 ESD Ratings

 

VALUE

UNIT

 

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)

+2000

 

V (ESD)

Electrostatic

Charged-device model (CDM), per JEDEC specification JESD22-C101, all pins (2)

+1000

V

discharge

 

Machine Model

200

 

(1)

JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2)

JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions, SN54LVC14A (1)

 

SN54LVC14A

 

–55 TO 125 ° C

UNIT

MIN

MAX

 

Operating

2

3.6

 

V CC

Supply voltage

   

V

Data retention only

1.5

V I

Input voltage

0

5.5

V

V O

Output voltage

0

V CC

V

(1) All unused inputs of the device must be held at V CC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs , literature number SCBA004 .

Copyright © 1993– 2015, Texas Instruments Incorporated

Product Folder Links: SN54LVC14A SN74LVC14A

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Recommended Operating Conditions, SN54LVC14A (1) (continued)

 

SN54LVC14A

 

–55 TO 125 ° C

 

UNIT

 

MIN

 

MAX

 
   

V CC = 2.7 V

   

–12

 

I OH

High-level output current

V CC = 3 V

   

–24

 

mA

   

V CC = 2.7 V

   

12

 

I OL

Low-level output current

V CC = 3 V

   

24

 

mA

7.4

Recommended Operating Conditions, SN74LVC14A (1)

 
   

SN74LVC14A

   

T A = 25 °C

–40 TO 85 ° C

–40 TO 125°C

   

UNIT

MIN

MAX

MIN

 

MAX

 

MIN

MAX

 
   

Operating

 

1.65

3.6

1.65

 

3.6

 

1.65

3.6

 

V CC

Supply voltage

Data retention only

 

1.5

 

1.5

   

1.5

 

V

V I

Input voltage

0

5.5

 

0

5.5

 

0

5.5

 

V

V O

Output voltage

0

V CC

 

0

V CC

 

0

V CC

 

V

 

V CC = 1.65 V

   

–4

 

–4

 

–4

 
   

V CC = 2.3 V

   

–8

 

–8

 

–8

I OH

High-level output current

V CC = 2.7 V

   

–12

 

–12

 

–12

 

mA

 

V CC = 3 V

   

–24

 

–24

 

–24

 
 

V CC = 1.65 V

   

4

 

4

 

4

 
   

V CC = 2.3 V

   

8

 

8

 

8

I OL

Low-level output current

V CC = 2.7 V

   

12

 

12

 

12

 

mA

 

V CC = 3 V

   

24

 

24

 

24

 

(1) All unused inputs of the device must be held at V CC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs , literature number SCBA004 .

 

7.5

Thermal Information

   

SNx4LVC257A

   
 

THERMAL METRIC (1)

D (SOIC)

DB (SSOP)

DGV (TVSOP)

 

NS (SO)

PW (TSSOP)

 

RGY (LCCC)

 

UNIT

   

14 PINS

   

20 PINS

 

R

 

Junction-to-ambient thermal

86

 

96

 

127

 

76

   

113

   

47

 

°

C/W

θJA

resistance

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

7.6 Electrical Characteristics, SN54LVC14A

over operating free-air temperature range (unless otherwise noted)

       

SN54LVC14A

 
 

PARAMETER

TEST CONDITIONS

V CC

 

–55 TO 125 ° C

UNIT

 

MIN

TYP

MAX

   

2.7

V

0.8

2

 

V T+

Positive-going

3

V

0.9

 

2

V

threshold

 

3.6 V

1.1

2

 
   

2.7 V

0.4

1.4

 

V T–

Negative-going

3

V

0.6

 

1.5

V

threshold

 

3.6

V

0.8

1.7

 

Copyright © 1993– 2015, Texas Instruments Incorporated

Product Folder Links: SN54LVC14A SN74LVC14A

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SCAS285AA – MARCH 1993 – REVISED JUNE 2015

Electrical Characteristics, SN54LVC14A (continued)

over operating free-air temperature range (unless otherwise noted)

     

SN54LVC14A

 
 

PARAMETER

   

TEST CONDITIONS

 

V

CC

 

–55 TO 125 ° C

UNIT

     

MIN

TYP

MAX

     

2.7

V

0.3

1.1

 

ΔV T

Hysteresis (V T+ – V T- )

   

3

V

0.3

1.2

V

   

3.6

V

0.3

1.2

 

I OH = – 100 μA

 

2.7

V to 3.6 V

V CC

 

0.2

V OH

     

2.7

V

2.2

V

V OL

 

I

I

2.4

I CC

   

3

V

2.2

 

I OL = 100 μA

 

2.7

V to 3.6 V

 

0.2

 

ΔI CC

C i

 

2.7

V

 

0.4

V

I OL = 24 mA

   

3

V

 

0.55

 

V I = 5.5 V or GND

   

3.6

V

 

±5

μA

 

V I = V CC or GND, I O = 0

   

3.6

V

 

10

μA

 

One input at V CC – 0.6 V, Other inputs at V CC or GND

2.7

V to 3.6 V

 

500

μA

 

V I = V CC or GND

   

3.3

V

 

5 (1)

pF

(1) T A = 25° C

 

7.7

Electrical Characteristics, SN74LVC14A

 

over operating free-air temperature range (unless otherwise noted)

 
       

SN74LVC14A

   

PARAMETER

 

TEST

 

V

T A = 25° C

   

–40 TO 85 ° C

–40 TO 125 ° C

UNIT

CONDITIONS

CC

     

MIN

TYP

MAX

 

MIN

MAX

MIN

MAX

 
   

1.65

V

0.4

1.3

 

0.4

1.3

0.4

1.3

 

1.95

V

0.6

1.5

 

0.6

1.5

0.6

1.5

 

Positive-

2.3

V

0.8

1.7

 

0.8

1.7

0.8

1.7

V T+

going

2.5

V

0.8

1.7

 

0.8

1.7

0.8

1.7

V

threshold

2.7

V

0.8

2

 

0.8

2

0.8

2

   

3

V

0.9

2

 

0.9

2

0.9

2

3.6

V

1.1

2

 

1.1

2

1.1

2

   

1.65

V

0.15

0.85

 

0.15

0.85

0.15

0.85

 

1.95

V

0.25

0.95

 

0.25

0.95

0.25

0.95

 

Negative-

2.3

V

0.4

1.2

 

0.4

1.2

0.4

1.2

       

V T

going

2.5

V

0.4

1.2

 

0.4

1.2

0.4

1.2

V

threshold

2.7

V

0.4

1.4

 

0.4

1.4

0.4

1.4

   

3

V

0.6

1.5

 

0.6

1.5

0.6

1.5

3.6

V

0.8

1.7

 

0.8

1.7

0.8

1.7

   

1.65

V

0.1

1.15

 

0.1

1.15

0.1

1.15

 

1.95

V

0.15

1.25

 

0.15

1.25

0.15

1.25

2.3

V

0.25

1.3

 

0.25

1.3

0.25

1.3

ΔV T

Hysteresis (V T+ – V T- )

2.5

V

0.25

1.3

 

0.25

1.3

0.25

1.3

V

       
 

2.7

V

0.3

1.1

 

0.3

1.1

0.3

1.1

 

3

V

0.3

1.2

 

0.3

1.2

0.3

1.2

3.6

V

0.3

1.2

 

0.3

1.2

0.3

1.2

Copyright © 1993– 2015, Texas Instruments Incorporated

Product Folder Links: SN54LVC14A SN74LVC14A

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Electrical Characteristics, SN74LVC14A (continued)

over operating free-air temperature range (unless otherwise noted)

       

SN74LVC14A

 
 

PARAMETER

TEST

V

 

T A = 25° C

 

–40 TO 85 ° C

 

–40 TO 125 ° C

UNIT

CONDITIONS

CC

 

MIN

TYP

MAX

MIN

MAX

MIN

MAX

 
 

I OH = – 100 μA

1.65

V to

V CC

V CC – 0.2

 

V CC – 0.3

   

3.6

V

0.2

I OH = – 4 mA

1.65

V

1.29

1.2

1.05

V

OH

I OH = – 8 mA

2.3

V

1.9

1.7

1.65

V

   

2.7

V

2.2

2.2

2.05

I OH = – 12 mA

3

V

2.4

2.4

2.25

I OH = – 24 mA

3

V

2.3

2.2

2

   

1.65

V to

       

I OL = 100 μA

3.6

V

 

0.1

 

0.2

 

0.3

I OL = 4 mA

1.65

V

 

0.24

 

0.45

 

0.6

V

OL

I OL = 8 mA

2.3

V

 

0.3

 

0.7

 

0.75

V

 

I OL = 12 mA

2.7

V

 

0.4

 

0.4

 

0.6

I OL = 24 mA

3

V

 

0.55

 

0.55

 

0.8

I

I

V I = 5.5 V or GND

3.6

V

 

±1

 

±5

 

±20

μA

I

CC

V I = V CC or GND, I O = 0

3.6

V

 

1

 

10

 

40

μA

ΔI CC

One input at V CC – 0.6 V, Other inputs at V CC or GND

2.7 V to

 

500

 

500

 

5000

μA

3.6

V

     

C

i

V I = V CC or GND

3.3

V

 

5

   

pF

7.8 Switching Characteristics, SN54LVC14A

over operating free-air temperature range (unless otherwise noted) (see Figure 2)

         

SN54LVC14A

 
 

PARAMETER

 

FROM

   

TO

   

V

 

–55 TO 125 ° C

UNIT

(INPUT)

(OUTPUT)

CC

     

MIN

MAX

 
       

2.7 V

   

7.5

 

t

pd

 

A

 

Y

3.3 V ± 0.3 V

 

1

6.4

ns

7.9

Switching Characteristics, SN74LVC14A

 

over operating free-air temperature range (unless otherwise noted) (see Figure 2)

 
         

SN74LVC14A

   
 

PARAMETER

FROM

TO

 

V CC

T A = 25° C

 

–40 TO 85 ° C

–40 TO 125 ° C

UNIT

(INPUT)

 

(OUTPUT)

           
   

MIN

TYP

MAX

 

MIN

MAX

MIN

MAX

       

1.8 V ± 0.15 V

1

5

10.5

 

1

11

 

1

13

 
 

2.5

V ± 0.2 V

1

3.4

7.3

 

1

7.8

 

1

10

t

pd

A

Y

 

2.7 V

1

3.6

7.3

 

1

7.5

 

1

9.5

ns

   

3.3

V ± 0.3 V

1

3.2

6.2

 

1

6.4

 

1

8

t

sk(o)

     

3.3

V ± 0.3 V

 

1

 

1

 

1.5

ns

8

Copyright © 1993– 2015, Texas Instruments Incorporated

Product Folder Links: SN54LVC14A SN74LVC14A

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SCAS285AA – MARCH 1993 – REVISED JUNE 2015

7.10 Operating Characteristics

T A = 25° C

 

TEST

V CC = 1.8 V

V CC = 2.5 V

V CC = 3.3 V

 
 

PARAMETER

CONDITIONS

TYP

TYP

TYP

UNIT

C pd

Power dissipation capacitance

f = 10 MHz

11

12

15

pF

7.11 Typical Characteristics

16 15 14 13 12 11 Typical Characteristics 10 1.5 1.7 1.9 2.1 2.3 2.5
16
15
14
13
12
11
Typical
Characteristics
10
1.5
1.7
1.9
2.1
2.3
2.5
2.7
2.9
3.1
3.3
3.5
Power Supply Voltage [V CC ] (V)
C001
Power Dissipation Capacitance (C pd )

Figure 1. Power Dissipation Capacitance vs. Power Supply Voltage

Copyright © 1993– 2015, Texas Instruments Incorporated

Product Folder Links: SN54LVC14A SN74LVC14A

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8 Parameter Measurement Information

V LOAD S1 R Open L From Output Under Test GND C L R L
V
LOAD
S1
R
Open
L
From Output
Under Test
GND
C
L
R
L
(see Note A)

LOAD CIRCUIT

TEST PHZ / t S1 V LOAD GND t PLH / t t t PLZ

TEST

PHZ /t

S1

V LOAD

GND

t PLH /t

t

t

PLZ /t

PHL

PZL

PZH

Open

INPUTS V V V C R V CC M LOAD L L D V t
INPUTS
V
V
V
C
R
V
CC
M
LOAD
L
L
D
V
t
I
r /t f
1.8 V ± 0.15 V
V
≤2 ns
V
/2
2
30
pF
1 kW
0.15
V
CC
CC
× V CC
2.5
V
± 0.2 V
V
≤2 ns
V
/2
2
30
pF
500
W
0.15
V
CC
CC
× V CC
2.7 V
2.7
V
≤2.5 ns
1.5
V
6
V
50
pF
500
W
0.3
V
3.3
V
± 0.3 V
2.7
V
≤2.5 ns
1.5
V
6
V
50
pF
500
W
0.3
V

Input

t w V M V M VOLTAGE WAVEFORMS PULSE DURATION
t w
V M
V M
VOLTAGE WAVEFORMS
PULSE DURATION

V I

0 V

Input

Output

Output

V M V M
V M
V M

t PLH

V
V

M

t PHL V M
t PHL
V M
t PHL
t PHL
t V M
t
V
M

PLH

V
V

M

V I

0 V

V

V

V

V

OH

OL

OH

OL

VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS

Timing Input

Data Input

Output

Control

Output Waveform 1 S1 at V LOAD (see Note B)

Output

Waveform 2 S1 at GND (see Note B)

V I V M 0 V t t su h V I V V M
V
I
V
M
0
V
t
t
su
h
V
I
V
V
M
M
0
V

VOLTAGE WAVEFORMS SETUP AND HOLD TIMES

V M V M
V M
V M
t PZL V M
t PZL
V M
V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES V M V M t PZL V M t

t PLZ

WAVEFORMS SETUP AND HOLD TIMES V M V M t PZL V M t PLZ V

V OL + V D

t PHZ

t PZH V M
t PZH
V M
M t PZL V M t PLZ V O L + V D t PHZ t
M t PZL V M t PLZ V O L + V D t PHZ t

V OH - V D

V I

0 V

V

V

LOAD /2

OL

V

OH

0 V

VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING

NOTES:

A.

C L includes probe and jig capacitance.

B.

Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.

C.

All input pulses are supplied by generators having the following characteristics: PRR10 MHz, Z O = 50 W.

D.

The outputs are measured one at a time, with one transition per measurement.

E.

t PLZ and t PHZ are the same as t dis .

F.

t PZL and t PZH are the same as t en .

G.

t PLH and t PHL are the same as t pd .

H.

All parameters and waveforms are not applicable to all devices.

Figure 2. Load Circuit and Voltage Waveforms

Copyright © 1993– 2015, Texas Instruments Incorporated

Product Folder Links: SN54LVC14A SN74LVC14A

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SCAS285AA – MARCH 1993 – REVISED JUNE 2015

9 Detailed Description

9.1 Overview

The SN54LVC14A hex Schmitt-trigger inverter is designed for 2.7-V to 3.6-V V CC operation, and the SN74LVC14A hex Schmitt-trigger inverter is designed for 1.65-V to 3.6-V V CC operation.

The devices contain six independent inverters and perform the Boolean function Y = A.

Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators in a mixed 3.3-V or 5-V system environment.

9.2 Functional Block Diagram

A Y
A
Y

Figure 3. Logic Diagram, Each Inverter (Positive Logic)

9.3 Feature Description

The SN54LVC14A hex Schmitt-trigger inverter is designed for 2.7-V to 3.6-V V CC operation, and the SN74LVC14A hex Schmitt-trigger inverter is designed for 1.65-V to 3.6-V V CC operation.

The devices contain six independent inverters and perform the Boolean function Y = A.

Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators in a mixed 3.3-V or 5-V system environment.

9.4 Device Functional Modes

Table 1 lists the functional modes for the SN54LVC14A and SN74LVC14A devices.

Table 1. Function Table (Each Inverter)

INPUT

OUTPUT

A

Y

H

L

L

H

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10 Application and Implementation

NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI ’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

10.1 Application Information

Physically interactive interface elements like push buttons or rotary knobs offer simple and easy ways to interact with an electronic system. Many of these physical interface elements often have issues with bouncing, or where the physical conductive contact can connect and disconnect multiple times during a button push or release. This bouncing can cause one or more faulty transient signals to be passed during this transitional period. These faulty signals can be observed in many common applications: for example, a television remote with bouncing error can adjust the TV channel multiple times despite the button being pushed only once. In order to mitigate these faulty signals, we can use a Schmitt-trigger, or a device with hysteresis, to remove these faulty signals. Hysteresis allows a device to "remember" its history, and in this case, the LVC14A uses this memory to debounce the physical element's signal, or filter the faulty transient signals and pass only the valid signal each time the element is used. In this example, we show a push button signal passed through an LVC14A that is debounced and inverted to the MCU for push detection.

10.2 Typical Application

The signal effects of the debounce circuit can be seen when comparing Figure 5 and Figure 6. In Figure 5 , the input is a very poor quality signal due to the error in the physical push button. If the MCU attempts to sample this input to detect a push, there is high probability that multiple push events will be falsely detected. Once the debounce circuit has been implemented, the input is cleaned up, and the MCU can perform push detection without any error, as seen in Figure 6 .

GND V CC

GND

V CC

GND V CC
without any error, as seen in Figure 6 . GND V CC LVC14A (x6) 1A 1Y

LVC14A

(x6)

1A 1Y
1A
1Y

V

V CC = 5 V

= 5 V

CC

MCU

(MSP43x)

Push Button

1Y V V C C = 5 V = 5 V CC MCU (MSP43x) Push Button

Figure 4. Debouncer Application Diagram

10.2.1 Design Requirements

The SN74LVC14A device uses CMOS technology and has balanced output drive. Take care to avoid bus contention because it can drive currents that would exceed maximum limits.

The SN74LVC14A allows for performing logical Boolean functions with hysteresis using digital signals. All input signals should remain as close as possible to either 0 V or V CC for optimal operation.