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Microcontroller Systems

Engineering Science
2nd year A2 Lectures

Prof David Murray

david.murray@eng.ox.ac.uk
www.robots.ox.ac.uk/∼dwm/Courses/2CO

Michaelmas 2014
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Introduction
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Introduction

The development of the the digital computer must rank as one of the
two engineering achievements that have had the most profound
impact on the progress of the 20th century.

Open up the box on any computer, and one is likely to be impressed


but also daunted by the sheer complexity — even of what one can
see.

You’re looking at the cumulative wizardry of, say, 106 to 107


engineer-years of development.

* Not surprising if you personally could not reproduce it tomorrow.


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Introduction
But computers are so commonplace in office and domestic settings
that when asked
“how does a computer work?”
you — even as engineers — probably start thinking along the “IT”
lines of the sketch

That is — what peripheral plugs into what socket, etc.

Dull, dull, dull


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Much more interesting and relevant is ...


How do computers function in an engineered system?

Short answer is that they provide

on the input side


a means of high-bandwidth data acquisition from sensors
⇒A2 Signal Conditioning Lectures

internally
a flexible firmware tool for real-time data analysis
⇒these lectures

on the output side


a means to control a plant
⇒A2 Control Lectures
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Changing nature ...


The ability to sense, compute, and actuate in real time allows you
literally to change nature.
Control engineers work to turn naughty transfer functionsinto
well-behaved, predictable, stable, engineered on

Plant’s
Transfer Function

Badly behaved

Engineered transfer function

Plant’s
Controller Transfer Function

Sensing

Well behaved
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Changing nature ...


Simple compensators can use analogue, but more sophistication,
flexibility, etc created using a digital compensator.
Engineered transfer function

Plant’s
Controller Transfer Function

Sensing

Well behaved

S&H
+
ADC DAC
Plant’s
Computer then Transfer Function
S&H ZOH
+
ADC

Sensing

Computer Controlled

That is, a computer surrounded


on the input side by a Sample-and-Hold and an ADC
on the output side by a DAC and Zero-order-Hold
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Computers as part of the engineered machine


Planes, trains and automobiles, for sure ...

... but also Civil engineering – Taipei 101 – huge, scary, but simple
Servo Valve

K1 Fluid

M1 M2

c1
Sensors

Controller
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Microcontroller systems
These four lectures are NOT about control, but will introduce you to
how a simple computer does its job in hardware.

Our focus is on simple computers which, though general purpose, are


programmed to perform a particular set of tasks.

Such microcontrollers are often


bundled together with input/output
devices and memory into a single
multi-pin package, costing £1-5.

They get embedded in a huge va-


riety of machinery ranging in com-
plexity from central heating boilers
to nuclear power stations, etc
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Microcontrollers

Some bad news — “simple” in this area is all relative. Excluding


memory, 8-bit microcontroller contains ∼ 0.1 × 106 transistors
Sounds substantial, until you compare with your desktop ...

Clock Processor Year Millions of Process


Speed transistors nm
0.03 80486 1989 1 1000
0.07 Pentium 1993 3 800
0.2 Pentium II 1997 8 500
0.5 Pentium III 1999 10 250
2.2 Pentium IV 2000 40 180
3.0 CoreDuo 2006 290 65
3.6 Core i7 2008 780 45
3.8 Core i7 2011 2270 32
? Itanium 2012 3100 32
? Xeon Phi 2012 5000 22
? Xbox One 2013 5000 28
> 3.6 Sparc M7 2014 10000 20
GPU Nvidia NV3 1997 4 350
GPU Nvidia GK110 2012 7080 28
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Microcontrollers

Yes, but even 105 transistors sounds daunting!!

The good news is ...


Strip away the froth, and the principles turn out to be
straightforward, and applicable to all scales.

Even more good news ...


the P2 course has provided everything you need to start.
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Reading

There is no one book that sits comfortably alongside this (very) short
course, but I have found several helpful for different parts.

Hill & Peterson “Digital Logic and Microprocessors” Wiley –


revision of basic logic components and for RTL.

Clements “Principles of Computer Architecture” OUP. Very clear


on components of the CPU.
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Course WWW Pages


Pdf copies of
the notes (including colour and larger print versions)
copies of these lecture slides
the tutorial sheets, plus any corrections and updates
hints, FAQs etc,
will be accessible from

www.robots.ox.ac.uk/∼dwm/Courses/2CO

(Only the notes and the tute sheets get put on weblearn.)

If you get really really stuck, email me.


If the answer is a useful one, it will get put into the FAQs
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Lecture Content

1 From Sequential Logic to a simple Central Processing Unit

2 Registers and Register Transfers in the CPU: how to fetch and


execute instructions

3 The Control Unit, the ALU, and Memory. Memory addressing.

4 I/0, Interfacing and Applications


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Lecture 1
From Sequential Logic to a simple CPU
What is a computation?
Finite state machines
Separating control from data
Register Transfer Language
Data, Control and the Central Processing Unit
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What is a computation?
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What is a computation?
Before getting embroiled in the detail of hardware and so on, it is
worth asking
what is meant by a computation?

A computation is the evaluation of some output O from some input I,


where these are collections of symbols of some sort.
You can think of the computation as a digital transfer function f

O = f (I)

... one which can be broken down into elemental steps fi

O1 = f1 (I) O2 = f2 (O1 ) ... O = fn (On−1 ) .

In a binary computer the symbols are likely to be 0’s and 1’s.


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What is a computation?
Now, you could imagine building different hardware for each fi
separately...
Input Output Input Output
f Transfer fi
function
selector

... but the idea of a general purpose computer is to reconfigure the


same piece of hardware to perform different tasks. That piece of
hardware is the central processing unit
Thoughts ...
We need a second input to select the transfer function.
We also need memory units, so that the Output can be stored
before changing the transfer function and passing it through the
Input again.
This is nothing other than a finite state machine.
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You knew that already!


The P2 Digital Logic course pre-
sented a diagram describing how Inputs Outputs
a sequential finite state machine
Combinational
could be built using combinational
Logic
logic and flip-flops.
Delay/storage
The flip-flops provided a delay so flip−flops
that the clock pulse would move
the system on to the next state.
The lectures ended with the following:
The concept of finite state machines is as the heart of the theory of the
computer ...

... If we introduce a branching capability which allows the sequence of states


to change according to an input condition ...

we have most elements required for understanding how a computer works ...
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Finite State Machines


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Branching using discrete combinational logic


Here is a simple example of introducing branching ...

♣ Problem: Using D-type flip-flops, design a modulo-4 counter that


counts upwards (0,1,2,3,0,...) if input x = 0 but downwards if x = 1.
A flag Z output should be set if the count output is zero.

A Solution: We can represent the state diagram as


x=0
x=0 x=0 x=0
A/0 B/1 C/2 D/3
x=1 x=1 x=1
x=1

Four states are labelled with name/output; transitions with the input.

Derive the output bits from Q0 and Q1 of two D-types.


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/ctd
Write down the D-type’s truth and transition tables, then determine
the values of D1,0 required to generate the sequences of Q1,0 ...
Transition For x =0 For x =1
Truth t
Q →Q t+1 t
D Q1 Q0 D1 D0 Q1 Q0 D1 D0
Dt Q t+1 0→0 0 0 0 0 1 0 0 1 1
⇒ &
0 0 1→0 0 0 1 1 0 1 1 1 0
1 1 0→1 1 1 0 1 1 1 0 0 1
1→1 1 1 1 0 0 0 1 0 0

Now build the Karnaugh maps (remembering Gray code!)


Q1 Q0 → 00 01 11 10 Q1 Q0 → 00 01 11 10
x↓ x↓
For D1 : For D0 :
0 0 1 0 1 0 1 0 0 1
1 1 0 1 0 1 1 0 0 1
whence

D1 = x.(Q0 .Q1 + Q0 .Q1 ) + x.(Q0 .Q1 + Q0 .Q1 ) D 0 = Q0 Z = Q1 .Q0


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Using a ROM to create the combinational logic

You also saw in P2 that a quite easy method of building part of the
combinational logic was to use a PROM instead of discrete logic
gates.

One part of the contents at a particular address tells you


what to do now
The other part of the contents tells you the address of
where to go next
“Next” means after the next clock pulse.
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Using a ROM to create the combinational logic


Same problem as before ... but solved using a PROM

To allow branching we introduce alternative “where next” addresses,


and x chooses one of them.

Address Contents
CLK Where next? What now?
Address
Lines if x=0 if x=1
A0
x } 01 0 0 1 1 1 0 0 1
1 1 1 0 0 0 0 1 0
2 A1 2 1 1 0 1 1 0 0
0
3 0 0 1 0 1 1 0
2 2
Count Z flag
Pair of D−type latches Output Output
Multiplexer with same CLK ROM
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The Moore fsm model


The example just seen was typical of a Moore finite state machine.
In this
The outputs at a particular time depend only on the current state.
The inputs affect which state is reached after the next clock
pulse, but don’t affect the current output.
The current output is defined by the current state.
Inputs
Combi− Delay
national flip−flops PROM Input=I1
B/O2
Logic

A/O1
Input=I
Outputs 2
Combi−
national C/O
3
Moore Model Logic

(The notes contrast this Moore model with a Mealy model. Mealy
uses less hardware, but is harder to understand!)
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Algorithmic State Machine Charts

The graphical state diagram of the sort give for the Moore model is
one method of translating the written description of an fsm into a
formal description.

A more descriptive method is the Algorithmic State Machine (ASM)


chart — like process flow diagrams used in software design.
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Algorithmic State Machine Charts

There are three symbols in ASM diagrams:

1. State definition rectangles: One per state. It gives the name of


the state, the flip-flop values that define the state, and a list of outputs.

2. Decision diamonds: Any number of these for each state. Each


senses an input condition or flag derived from an external sensor or
other device, and takes a binary decision.

3. Conditional output curvy boxes: These occur at the exit lines of


decision diamonds, and describe outputs that become true only when
a condition is satisfied.

NB these outputs cannot “change” the outputs given in the state box. If you need to do that, you
need an extra state.
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ASM Example (see Hill and Peterson for more)


♣When washing finishes, the door remains locked until timer T1 counts up to
a minute. If the door is not open by the user, the washing machine beeps
loudly for 1 minute, and then beeps softly for 4 minutes. Opening the door
puts the machine in a reset state.
To Reset State

Really
Just finished!
finished

DoorLock=1 DoorLock=0

N T1 Y Door Y
finished? opened?

N
N T1
BeepLoud=1 finished?

Y
N T5
BeepSoft=1 finished?

Y
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Separating Data from Control


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Separating Data from Control


There seems an obvious difficulty in both graphical methods ...
... each and every state is represented.

Bad news ... n flip-flops can represent up to 2n states!

While this number is manageable for a few flip-flops, the method


becomes unworkable for a machine with several tens of flip-flops,
let alone several 109 .

Better news ... The vast majority of flip-flops will merely be


storing data ...

... upon which the machine operates in the same way,


irrespective of what the data is exactly.
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Separating Data from Control


Hence, in a sequential machine, it makes sense to split
Data In Data Section Data Out

the data section from


Control Data
the operational control Signals Flags
section. External
Controls Control Section

At times, the control section will need to know something about the
data — eg, to take a different action if a datum is zero rather than
positive.

So there will be two way communication between the control and data
sections ...

but usually only flags about the data need sending.


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Separating Data from Control

Now we could now describe the control section using, say, ASM
charts ...

... but it is more convenient to use a description that has the syntax to
deal with the data section at the same time.

We’ll adopt a “blackboard” hardware description language which


separates data from control — a Register Transfer Language.

Commercial examples of such languages are VHDL


(Very-High-Speed-Integrated-Circuit Hardware Description
Language), and Verilog.
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Register Transfer Language


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Preamble #1: What’s a Register?

D Q D[0] Q[0]
CLK
D[1] Q[1]

D−type flip flop D[2] Q[2]

4−bit register D[3] Q[3]

CLK

An n-bit storage register is a parallel grouping of n 1-bit D-type


flip-flops which have coupled clocks, and transfer input to output on a
receipt of a clock pulse
Q t+1 ← D t

In this example, transfer occurs on a falling edge, indicated by the


circle placed in front of the clock input.
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Preamble #2: What’s a Register Transfer?


A B
D Q Q A[0] B[0]
T R
CLK CLK
A[1] B[1]

D−type flip flop 1−bit transfer A[2] B[2]

Transfer from 4−bit register A to B A[3] B[3]

CLK

The transfer of data between two storage registers is the principal


activity that occurs in the data section of most sequential machines.

In the 1-bit example, clocking register R causes transfer R ← T .

In the 4-bit example B ← A means that B[i] ← A[i] for i = 0, 1, 2, 3.

The receiving register is clocked


NOT the transmitting register.
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Preamble #3: making pathways between registers


Often two different registers A and B need to transfer to the same
register C, although at different times.
We must NOT stuff both into the input of C
(i) C will not know which to choose and (ii) connecting the output
of two registers with different output values (ie 0 and 1) may fry
the output stage of one or both!!
Use either a multiplexer or tri-state buffers.
Both allow us to perform C ← A when s = 0 and C ← B when s = 1.
A Multiplexer A Tristate buffers (4 in parallel)
4 Bus
4
C C
M0 4 4

B M1 B
4 4
0/1
}

s s
Select CLK Select CLK
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What’s RTL? An example ... Step 1

MODULE: DATAMOVER
MEMORY: A[2]; B[2]; C[2]; S
INPUTS: X [2].
OUTPUTS: Z [2]; P.
The first block defines the data
section.
1 A←X
2 C←A; S←A[0] A, B, C are two bit registers, but S
3 B←C is single bit.
4 C←A∨B X is a two bit input wire and Z , P
5 Z = C; S←0; →(1) are two, one bit output wires.
ENDSEQUENCE
ControlReset(1); P = S.
END
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What’s RTL? An example ... Step 2

MODULE: DATAMOVER The numbered lines define the con-


MEMORY: A[2]; B[2]; C[2]; trol section. They are executed at
S successive clock pulses (unless there
INPUTS: X [2]. is branching).
OUTPUTS: Z [2]; P.
On line 1: input X is transferred to A,
so we need to clock register A.
1 A←X
2 C←A; S←A[0] On line 2: inverse of A is transferred to
3 B←C register C, and S is set to A[0],
4 C←A∨B
Lines 3 and 4: More register transfers.
5 Z = C; S←0; →(1)
∨ is a logical OR.
ENDSEQUENCE On line 5: Output Z is conected to C
ControlReset(1); P = S. throughout line 5. The goto arrow →
END sets the next line as 1.
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What’s RTL? An example ... Step 3

MODULE: DATAMOVER
MEMORY: A[2]; B[2]; C[2];
S
INPUTS: X [2].
At the end:
OUTPUTS: Z [2]; P.
ControlReset(1) indicates that a reset
1 A←X pulse should set the control section to
2 C←A; S←A[0] line 1.
3 B←C P = S indicates that an output wire P
4 C←A∨B is permanently soldered to the output
5 Z = C; S←0; →(1) of register S.
ENDSEQUENCE
ControlReset(1); P = S.
END
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Control section: generating Level and Pulses


1 A←X Typically, the activity on each step of the
2 C←A; S←A[0] control section requires
3 B←C a level to select a pathway between
4 C←A∨B registers, and
5 Z = C; S←0; →(1) a pulse to fire register transfers.

These are Control Step Level and Pulse signals —- CSL1, CSP1,
CSL2, CSP2 ... CSL5, CSP5

We need to build a state machine in hardware to deliver these signals.

Any method of building a sequential fsm can be used — eg a PROM


sequencer — but here we will use a slightly wasteful but very intuitive
method called one-hot.
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Control section: generating Level and Pulses


The number of states equals the number
1 A←X of steps — 5 in this case.
2 C←A; S←A[0]
3 B←C Now study the flow from one line to an-
4 C←A∨B other. It is uninterrupted from line 1 to 5,
5 Z = C; S←0; →(1) where there is an unconditional goto indi-
cated by →(1).

CSL1 CSP1 CSL2 CSP2 CSL3 CSP3 CSL4 CSP4 CSL5 CSP5

D Q D Q D Q D Q D Q
1 2 3 4 5
S R R R R

CLK

ControlReset
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Why is this one-hot?


The one flip-flop corresponding to the active line of RTL has output 1
(hence hot) — the remainder have output 0.
On a falling clock edge the output 1 is transferred to D-type 2, then 3,
etc
Notice how the →(1) is achieved by looping the output of D-type 5
into the input of D-type 1.
CSL1 CSP1 CSL2 CSP2 CSL3 CSP3 CSL4 CSP4 CSL5 CSP5

D Q D Q D Q D Q D Q
1 2 3 4 5
S R R R R

CLK

ControlReset
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Why is this one-hot?


The one flip-flop corresponding to the active line of RTL has output 1
(hence hot) — the remainder have output 0.
On a falling clock edge the output 1 is transferred to D-type 2, then 3,
etc
Notice how the →(1) is achieved by looping the output of D-type 5
into the input of D-type 1.
CSL1 CSP1 CSL2 CSP2 CSL3 CSP3 CSL4 CSP4 CSL5 CSP5

D Q D Q D Q D Q D Q
1 2 3 4 5
S R R R R

CLK

ControlReset
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Why is this one-hot?


The one flip-flop corresponding to the active line of RTL has output 1
(hence hot) — the remainder have output 0.
On a falling clock edge the output 1 is transferred to D-type 2, then 3,
etc
Notice how the →(1) is achieved by looping the output of D-type 5
into the input of D-type 1.
CSL1 CSP1 CSL2 CSP2 CSL3 CSP3 CSL4 CSP4 CSL5 CSP5

D Q D Q D Q D Q D Q
1 2 3 4 5
S R R R R

CLK

ControlReset
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Why is this one-hot?


The one flip-flop corresponding to the active line of RTL has output 1
(hence hot) — the remainder have output 0.
On a falling clock edge the output 1 is transferred to D-type 2, then 3,
etc
Notice how the →(1) is achieved by looping the output of D-type 5
into the input of D-type 1.
CSL1 CSP1 CSL2 CSP2 CSL3 CSP3 CSL4 CSP4 CSL5 CSP5

D Q D Q D Q D Q D Q
1 2 3 4 5
S R R R R

CLK

ControlReset
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Why is this one-hot?


The one flip-flop corresponding to the active line of RTL has output 1
(hence hot) — the remainder have output 0.
On a falling clock edge the output 1 is transferred to D-type 2, then 3,
etc
Notice how the →(1) is achieved by looping the output of D-type 5
into the input of D-type 1.
CSL1 CSP1 CSL2 CSP2 CSL3 CSP3 CSL4 CSP4 CSL5 CSP5

D Q D Q D Q D Q D Q
1 2 3 4 5
S R R R R

CLK

ControlReset
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Why is this one-hot?


The one flip-flop corresponding to the active line of RTL has output 1
(hence hot) — the remainder have output 0.
On a falling clock edge the output 1 is transferred to D-type 2, then 3,
etc
Notice how the →(1) is achieved by looping the output of D-type 5
into the input of D-type 1.
CSL1 CSP1 CSL2 CSP2 CSL3 CSP3 CSL4 CSP4 CSL5 CSP5

D Q D Q D Q D Q D Q
1 2 3 4 5
S R R R R

CLK

ControlReset
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Timing details
Falling edge
triggers D−type
in control section

CLK
Level to set up
combinational logic
in data section

CSLn
Falling edge to
trigger register transfer
in data section

CSPn = CLK .AND. CSLn

CSLn+1

CSPn+1
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Data section: (Lines 1)


In the Data Section ...
Basic hardware is defined by the top + bottom block of the module
Pathways are implicitly defined by the control steps.
Line 1
* inputs X connected to input of register A
* clock by CSP1.
A S MODULE: DATAMOVER
P
X[0] D Q D Q MEMORY: A[2]; B[2]; C[2];
CK S
X[1] D Q Z[0]
C INPUTS: X [2].
D Q OUTPUTS: Z [2]; P.
CK Z[1]
1 A←X
D Q
B 2 C←A; S←A[0]
CK
D Q
3 B←C
CK
D Q
4 C←A∨B
CK 5 Z = C; S←0; →(1)
ENDSEQUENCE
ControlReset(1); P = S.
CSP1
END
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Data section: (Lines 2 and 3)


Line 2
* Inverted outputs of A connected to C.
* Output A[0] connected to input of S.
* CSP2 to the CK input of C and S.
Line 3
*
A S P
MODULE: DATAMOVER
X[0] D Q D Q MEMORY: A[2]; B[2]; C[2];
Q S
X[1] D Q Z[0]
Q
INPUTS: X [2].
D Q OUTPUTS: Z [2]; P.
Z[1]
1 A←X
D Q
B 2 C←A; S←A[0]
D Q
C 3 B←C
D Q
4 C←A∨B
5 Z = C; S←0; →(1)
ENDSEQUENCE
CSP1 CSP3 CSP2
ControlReset(1); P = S.
END
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Data section: (Line 4): modifications needed now


Line 4:
* C must be clocked on line 4 and line 2
⇒C’s clock input is CSP2∨CPS4.
* On line 2, input to C is A but on line 4 input to C is A ∨ B.
⇒insert AND gates, ANDing with CSL2 and CSL4 respectively, and
then OR the inputs into C.

A CSL2 MODULE: DATAMOVER


S P
X[0] D Q D Q MEMORY: A[2]; B[2]; C[2];
Q CK S
Z[0]
X[1] D Q INPUTS: X [2].
Q
D Q OUTPUTS: Z [2]; P.
Z[1] 1 A←X
D Q
B 2 C←A; S←A[0]
D Q 3 B←C
C
4 C←A∨B
D Q
5 Z = C; S←0; →(1)
ENDSEQUENCE
CSP1 CSP3 CSL4 CSP4 CSP2
ControlReset(1); P = S.
END
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Data section: (Line 5)

5 Z = C; S←0; →(1)
A CSL2 S P
X[0] D Q D Q
Q CK
X[1] D Q Z[0]
Q
D Q
Z[1]
D Q
B
D Q
C
D Q

CSP1 CSP3 CSL4 CSP4 CSP2


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Data section: (Line 5)

5 Z = C; S←0; →(1)
A CSL2 S P
X[0] D Q D Q
Q CK
X[1] D Q Z[0]
Q
D Q
Z[1]
D Q
B
D Q
C
D Q

CSP1 CSP3 CSL4 CSP4 CSP2 CSL5


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Data section: (Line 5)

5 Z = C; S←0; →(1)
A CSL2 S P
X[0] D Q D Q
Q CK
X[1] D Q Z[0]
Q
D Q
Z[1]
D Q
B
D Q
C
D Q

CSP1 CSP3 CSL4 CSP4 CSP2 CSL5


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Data section: (Line 5)

5 Z = C; S←0; →(1)
A CSL2 S P
X[0] D Q D Q
Q CK
X[1] D Q Z[0]
Q
D Q
Z[1]
D Q
B
D Q
C
D Q

CSP1 CSP3 CSL4 CSP4 CSP2 CSL5


CSP5
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Conditional gotos in RTL

We’ve seen the unconditional goto

→(S1 )

In our RTL, a conditional goto is written as follows:

→(L1 , ..., Ln )/(S1 , ..., Sn )

This evaluates logical expressions L1 , L2 , ... in turn. The very first


found to be true causes a jump to the corresponding control step S.
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Using conditionals with data flags to control flow

At step 4, if A[1] is 1 control passes to 5, if A[1] is 0, it goes to step 6.


MODULE: DATAMOVER
MEMORY: A[2]; B[2]; C[2]; S MODULE: OLD-DATAMOVER
INPUTS: X [2]. MEMORY: A[2]; B[2]; C[2]; S
OUTPUTS: Z [2]; P. INPUTS: X [2].
OUTPUTS: Z [2]; P.
1 A←X 1 A←X
2 C←A; S←A[0] 2 C←A; S←A[0]
3 B←C 3 B←C
4 C←A∨B; →(A[1], A[1])/(5, 6) 4 C←A∨B
5 Z = C; S←0; →(1)
5 Z = C; S←1; →(1)
6 Z = C; S←0; →(1) ENDSEQUENCE
ENDSEQUENCE ControlReset(1); P = S.
END
ControlReset(1); P = S.
END
µcontroller systems 50 / 57

Implementation of the new control section

The revised controller must have 6 flip-flops, and a connection from


A[1] into the control unit is needed. A[1] provides the selection signal
in a multiplexer.
CSP1 CSP2 CSP3 CSP4 A[1] CSP5
CSL1 CSL2 CSL3 CSL4 CSL5

D Q D Q D Q D Q D Q
1 2 3 4 5 CSP6
S R R R R CSL6
CLK
Control
Reset
D Q
6
R

NB: OR gate handles the multiple ways of arriving back at Line 1.


µcontroller systems 51 / 57

Implementation of the new control section

CSP1 CSP2 CSP3 CSP4 A[1] CSP5


CSL1 CSL2 CSL3 CSL4 CSL5

D Q D Q D Q D Q D Q
1 2 3 4 5 CSP6
S R R R R CSL6
CLK
Control
Reset
D Q
6
R
µcontroller systems 51 / 57

Implementation of the new control section

CSP1 CSP2 CSP3 CSP4 A[1] CSP5


CSL1 CSL2 CSL3 CSL4 CSL5

D Q D Q D Q D Q D Q
1 2 3 4 5 CSP6
S R R R R CSL6
CLK
Control
Reset
D Q
6
R
µcontroller systems 51 / 57

Implementation of the new control section

CSP1 CSP2 CSP3 CSP4 A[1] CSP5


CSL1 CSL2 CSL3 CSL4 CSL5

D Q D Q D Q D Q D Q
1 2 3 4 5 CSP6
S R R R R CSL6
CLK
Control
Reset
D Q
6
R
µcontroller systems 51 / 57

Implementation of the new control section

CSP1 CSP2 CSP3 CSP4 A[1] CSP5


CSL1 CSL2 CSL3 CSL4 CSL5

D Q D Q D Q D Q D Q
1 2 3 4 5 CSP6
S R R R R CSL6
CLK
Control
Reset
D Q
6
R
µcontroller systems 51 / 57

Implementation of the new control section

CSP1 CSP2 CSP3 CSP4 A[1] CSP5


CSL1 CSL2 CSL3 CSL4 CSL5

D Q D Q D Q D Q D Q
1 2 3 4 5 CSP6
S R R R R CSL6
CLK
Control
Reset
D Q
6
R
µcontroller systems 51 / 57

Implementation of the new control section

CSP1 CSP2 CSP3 CSP4 A[1] CSP5


CSL1 CSL2 CSL3 CSL4 CSL5

D Q D Q D Q D Q D Q
1 2 3 4 5 CSP6
S R R R R CSL6
CLK
Control
Reset
D Q
6
R
µcontroller systems 52 / 57

Timing

X0
1 A←X
X1
2 C←A; S←A[0]
etc CLK
HOT 1 2 3 4 6 1 2 3 4 5

Do check the A0

example of the A1

variation over time of C0


the various register
C1
outputs for particular
(but arbitrary) inputs B0

X ... ... useful for B1


one of the tute sheet S
examples if nothing
else. Z0

Z1
µcontroller systems 53 / 57

Two notes
Combinational and sequential “black boxes”
“Black boxes” with names can be used in data section. Read
H&P Sections 10.7.
The assumption is that these are defined elsewhere in your code
or elsewhere in a library of hardware
Step numbering when developing
Without “goto”, control passes from line S to line S + 1 on a clock
tick, so all the steps 1,2,3...Smax should be present.
While developing ideas, let’s allow gaps in the numbering, so the
control passes to the next highest number.
Eg, if there is no line 4, line 3 would pass to line 5.
1 A←X
2 C←A; S←A[0]
3 B←C
5 →(1)

Once complete, it is trivial to clean up.


µcontroller systems 54 / 57

Data, Control, and the CPU


µcontroller systems 55 / 57

So far ...

We’ve seen that separating data from control helps clarify and
simplify the design of sequential circuits.

We’ve also just seen how a single bit of data (A[1]) from the data
section can alter the flow in the control section ... ... effectively
changing what the module does.

Now we want to extend that idea to the central processing unit


(CPU) of a simple computer.
+ We’ll develop a von Neumann architecture,
— data section is connected via a bus to a single main
memory
+ But µcontrollers mostly adopt a Harvard architecture
— two memories, one for the program, the other for the data.
µcontroller systems 56 / 57

Data, Control, and the CPU


Central Processing Unit Main Memory
Data Section Data In/Out

Control Data Plain Data


Signals Flags Program Data
External
Controls Control Section

Data is read from the memory into the CPU via a bus.
The CPUs’ data section contains registers and interconnecting
pathways, and an Arithmetic Logic Unit.
The result of a computation may be stored temporarily on CPU
registers or written back to Main Memory.
The CPU’s control section is an fsm — we’ll use a one hot
sequencer — which sends CSL’s and CSP’s to the data section
to set pathways and to fire register transfers.
µcontroller systems 57 / 57

Data, Control, and the CPU


Central Processing Unit Main Memory
Data Section Data In/Out

Control Data Plain Data


Signals Flags Program Data
External
Controls Control Section

As well as holding regular (grey) data, the Memory holds a set of


(red) instructions that together form the program to execute.
The control section (CU) performs register transfers to fetch an
instruction from memory. The CU turns the instruction into the
sequence of CSLs and CSPs needed to execute the instruction.
Once the execution of one instruction is finished, the next
instruction is fetched, and so on.