COMSATS Institute of Information

Technology Abbottabad

Course Code: EEE344

Course Title: Digital System Design
Credit Hours: 4(3 , 1)
Pre-Requisites: EEE241, CSC141

Goals:
This course (EEE344) introduces the student to the design of digital logic circuits, both
combinational and sequential, and the design of digital systems. The student is also introduced to
the use of computer-aided design tools to develop complex digital circuits. The behavioral level
design of a digital system is often performed using hardware description languages (HDLs) such
as Verilog.

Students taking this course will learn how to use Verilog to describe behavior and
functionalities of any complex digital systems. The gate level implementation of a digital system
is mapped to a Field programmable gate array (FPGA) device for verification. Therefore,
students will go through the entire design process of describing hardware using software
languages, mapping it into gates and simulating the gate level design, and finally load the
schematic design on to a silicon chip to verify the functionality of the system in hardware.

Objectives:
1. Ability to use computer-aided design tools for design of complex digital logic circuits.
2. Ability to model, simulate, verify, and synthesize with hardware description languages.
3. Ability to design and prototype with programmable logic.

Text book:

1. FPGA prototyping by Verilog examples Xilinx spartantm-3 version by Pong P. Chu, John
Wiley & sons.

Recommended Text(s)/Reference Books:

1. Advanced Digital Design with Verilog HDL by Michael D. Ciletti, Prentice Hall
Publisher.
2. Verilog HDL-A guide to digital design and synthesis by Samir Palnitkar, Prentice Hall
Publisher.
3. Digital Design of Signal Processing Systems by Shoab A. Khan
Course Outline & Contents:

Week 01  Introduction to digital system design , Hardware description languages,

Verilog HDL
Week 02  Introduction to logic design with Verilog HDL, structural models of
combinational logic
Week 03  Logic simulation, Design verification and test methodology, Propagation
delay.
Week 04  Design, analysis and testing of adder circuits. Ripple carry adder, Carry
look ahead adder.
Week 05  Carry select adder, Conditional sum adder. Comparison on the basis of
speed and area.
Week 06  Basic multiplier circuit. Partial product reduction techniques for
multipliers. Carry save, Dual carry save and Wallace tree reduction
techniques.
Week 07  Dada tree reduction technique. String property, Modified booth recoding
algorithm.
Week 08  Number system, Floating point and fixed point formats, Addition and
multiplication in Qn.m format. Bit growth in fixed point arithmetic.
Overview of FPGA and EDA software.
Week 09  Introduction to FSM, FSM representation, FSM code development.
Week 10  Design examples for FSM, Rising edge detector, Mealy, Moore based
design, Direct implementation and comparison.
Week 11  Design examples contd…. Bouncing circuit and testing circuit
Week 12  Introduction to FSMD, ASMD chart, Code development of an FSMD
Week 13  Design examples.
Week 14  Selected topics of Verilog HDL, Blocking versus non blocking
assignments, Alternating coding style for sequential circuit, Use of sign
data type, Use of function is synthesis
Week 15  Design and implementation of a very simple CPU.
Week 16  Design verification.

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