Code: 9A04306 SS

B.Tech II Year II Semester (R09) Regular & Supplementary Examinations June 2014
DIGITAL LOGIC DESIGN
(Computer Science & Engineering)
Time: 3 hours Max. Marks: 70
Answer any FIVE questions
All questions carry equal marks
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1 (a) Perform the subtraction operation using 1’s complement representation.
(i)
(ii)
(b) Determine the value of ‘x’ in the following:
(i)
(ii)

2 (a) State and prove the following for Boolean algebra.

(i) Redundant Literal Rule (RLR).
(ii) Consensus theorem.
(b) Using consensus theorem, show that .
(c) State and prove De-Morgan’s theorem with an example.

3 (a) Realize all logic gates using only NAND gate.

(b) Reduce the expression f (a, b, c) = (0, 2, 3, 4, 5, 6) using mapping
technique and implement it using only NAND gates.

4 (a) Compare combinational logic and sequential logic circuits.

(b) Explain the operation of a 4-bit binary parallel adder-subtractor circuit using
suitable example for addition and subtraction operations.

5 (a) Implement the following using 3 X 4 X 2 PLA: F1 (0, 1, 3, 5) , F2

(3, 5, 7).
(b) Compare the three programmable logic devices i.e., PROM, PLA and PAL.

6 (a) Explain the following parameters of flip-flops:

(i) Set-up time.
(ii) Hold time.
(iii) Propagation delay.
(b) Convert the following flip-flops into JK flip-flop and also give its truth table,
excitation table and logic diagram.

7 (a) Design a synchronous BCD counter using JK flip flop.

(b) Compare the Moore and Mealy models of sequential circuits and also give
suitable examples.

8 (a) Explain in detail the procedure of analysis of asynchronous sequential

circuits.
(b) Explain in detail about how hazards can be removed in combinational and
sequential circuits.

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