Motorola

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
MC14051B
Analog
MC14052B
Multiplexers/Demultiplexers
MC14053B
The MC14051B, MC14052B, and MC14053B analog multiplexers are
digitally–controlled analog switches. The MC14051B effectively implements
an SP8T solid state switch, the MC14052B a DP4T, and the MC14053B a
Triple SPDT. All three devices feature low ON impedance and very low OFF
leakage current. Control of analog signals up to the complete supply voltage L SUFFIX
range can be achieved. CERAMIC
• Triple Diode Protection on Control Inputs CASE 620
• Switch Function is Break Before Make
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• Analog Voltage Range (VDD – VEE) = 3.0 to 18 V P SUFFIX
Note: VEE must be VSSv PLASTIC
CASE 648
• Linearized Transfer Characteristics
• Low–noise – 12 nV/√Cycle, f ≥ 1.0 kHz Typical
• Pin–for–Pin Replacement for CD4051, CD4052, and CD4053
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
D SUFFIX
• For 4PDT Switch, See MC14551B
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SOIC
• For Lower RON, Use the HC4051, HC4052, or HC4053 High–Speed CASE 751B
CMOS Devices
ORDERING INFORMATION
MAXIMUM RATINGS*
MC14XXXBCP Plastic
Symbol Parameter Value Unit MC14XXXBCL Ceramic
VDD DC Supply Voltage (Referenced to VEE, MC14XXXBD SOIC
VSS ≥ VEE) – 0.5 to + 18.0 V TA = – 55° to 125°C for all packages.
Vin, Vout Input or Output Voltage (DC or Transient)
(Referenced to VSS for Control Inputs and
VEE for Switch I/O) – 0.5 to VDD + 0.5 V
Iin Input Current (DC or Transient),
per Control Pin ± 10 mA
Isw Switch Through Current ± 25 mA
PD Power Dissipation. per Package† 500 mW
Tstg Storage Temperature – 65 to + 150 _C
TL Lead Temperature (8–Second Soldering) 260 _C
* Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:“P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C
MC14051B MC14052B MC14053B
8–Channel Analog Dual 4–Channel Analog Triple 2–Channel Analog
Multiplexer/Demultiplexer Multiplexer/Demultiplexer Multiplexer/Demultiplexer
6 INHIBIT 6 INHIBIT 6 INHIBIT
11 A CONTROLS 10 A 11 A X 14
CONTROLS X 13 CONTROLS
10 B 9 B 10 B
9 C 12 X0 9 C
13 X0 14 X1 12 X0 Y 15 COMMONS
COMMONS
14 X1 15 X2 13 X1 OUT/IN
X 3 OUT/IN
15 X2 SWITCHES 11 X3 SWITCHES 2 Y0
COMMON
SWITCHES 12 X3 IN/OUT 1 Y0 IN/OUT 1 Y1
OUT/IN Y 3 Z 4
IN/OUT 1 X4 5 Y1 5 Z0
5 X5 2 Y2 3 Z1
2 X6 4 Y3
4 X7
VDD = PIN 16 VDD = PIN 16 VDD = PIN 16

VSS = PIN 8 VSS = PIN 8 VSS = PIN 8
VEE = PIN 7 VEE = PIN 7 VEE = PIN 7
Note: Control Inputs referenced to VSS, Analog Inputs and Outputs reference to VEE. VEE must be ≤ VSS.
REV 3
1/94
MOTOROLA CMOS LOGIC DATA

Motorola, Inc. 1995 MC14051B MC14052B MC14053B
1
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ELECTRICAL CHARACTERISTICS
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ – 55_C 25_C 125_C
Characteristic
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Symbol
ÎÎÎÎÎÎÎÎ
VDD Test Conditions Min Max Min Typ # Max Min Max Unit
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SUPPLY REQUIREMENTS (Voltages Referenced to VEE)
Power Supply Voltage VDD — VDD – 3.0 ≥ VSS ≥ VEE 3.0 18 3.0 — 18 3.0 18 V
Range
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
v ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Quiescent Current Per IDD 5.0 Control Inputs: — 5.0 — 0.005 5.0 — 150 µA
Package 10 Vin = VSS or VDD, — 10 — 0.010 10 — 300
v ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ 15 Switch I/O: VEE VI/O — 20 — 0.015 20 — 600
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
VDD, and
v ∆Vswitch 500 mV**
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Total Supply Current ID(AV) 5.0 TA = 25_C only (The µA
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
(0.07 µA/kHz) f + IDD
(Dynamic Plus 10 channel component,
Typical (0.20 µA/kHz) f + IDD
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Quiescent, Per Package 15 (Vin – Vout)/Ron, is
(0.36 µA/kHz) f + IDD
not included.)
CONTROL INPUTS — INHIBIT, A, B, C (Voltages Referenced to VSS)
Low–Level Input Voltage VIL 5.0 Ron = per spec, — 1.5 — 2.25 1.5 — 1.5 V
10 Ioff = per spec — 3.0 — 4.50 3.0 — 3.0
15 — 4.0 — 6.75 4.0 — 4.0
High–Level Input Voltage VIH 5.0 Ron = per spec, 3.5 — 3.5 2.75 — 3.5 — V
10 Ioff = per spec 7.0 — 7.0 5.50 — 7.0 —
15 11 — 11 8.25 — 11 —
Input Leakage Current Iin 15 Vin = 0 or VDD — ± 0.1 — ± 0.00001 ± 0.1 — 1.0 µA
Input Capacitance Cin — — — — 5.0 7.5 — — pF
SWITCHES IN/OUT AND COMMONS OUT/IN — X, Y, Z (Voltages Referenced to VEE)
Recommended VI/O — Channel On or Off 0 VDD 0 — VDD 0 VDD VPP
Peak–to–Peak Voltage
Into or Out of the Switch
Recommended Static or ∆Vswitch — Channel On 0 600 0 — 600 0 300 mV
Dynamic Voltage Across
the Switch** (Figure 5)
Output Offset Voltage VOO — Vin = 0 V, No Load — — — 10 — — — µV
ON Resistance v Ron 5.0 ∆Vswitch 500 mV**, — 800 — 250 1050 — 1200 Ω
10 Vin = VIL or VIH — 400 — 120 500 — 520
15 (Control), and Vin = — 220 — 80 280 — 300
0 to VDD (Switch)
∆ON Resistance Between ∆Ron 5.0 — 70 — 25 70 — 135 Ω
Any Two Channels in the 10 — 50 — 10 50 — 95
Same Package 15 — 45 — 10 45 — 65
Off–Channel Leakage Ioff 15 Vin = VIL or VIH — ± 100 — ± 0.05 ± 100 — ± 1000 nA
Current (Figure 10) (Control) Channel to
Channel or Any One
Channel
Capacitance, Switch I/O CI/O — Inhibit = VDD — — — 10 — — — pF
Capacitance, Common O/I CO/I — Inhibit = VDD pF
(MC14051B) — — — 60 — — —
(MC14052B) — — — 32 — — —
(MC14053B) — — — 17 — — —
Capacitance, Feedthrough CI/O — Pins Not Adjacent — — — 0.15 — — — pF
(Channel Off) — Pins Adjacent — — — 0.47 — — —
#Data labeled “Typ” is not to be used for design purposes, but is intended as an indication of the IC’s potential performance.
* For voltage drops across the switch (∆Vswitch) > 600 mV ( > 300 mV at high temperature), excessive VDD current may be drawn, i.e. the
current out of the switch may contain both VDD and switch input components. The reliability of the device will be unaffected unless the Maximum
Ratings are exceeded. (See first page of this data sheet.)
MC14051B MC14052B MC14053B MOTOROLA CMOS LOGIC DATA

2
v ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS* (CL = 50 pF, TA = 25_C) (VEE VSS unless otherwise indicated)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ VDD – VEE Typ #
Characteristic Symbol Vdc All Types Max Unit
Propagation Delay Times (Figure 6) tPLH, tPHL ns
Switch Input to Switch Output (RL = 10 kΩ)
MC14051
tPLH, tPHL = (0.17 ns/pF) CL + 26.5 ns 5.0 35 90
tPLH, tPHL = (0.08 ns/pF) CL + 11 ns 10 15 40
tPLH, tPHL = (0.06 ns/pF) CL + 9.0 ns 15 12 30
MC14052 ns
MC14053 ns
tPLH, tPHL = (0.08 ns/pF) CL + 4.0 ns 10 8.0 20
tPLH, tPHL = (0.06 ns/pF) CL + 3.0 ns 15 6.0 15
Inhibit to Output (RL = 10 kΩ, VEE = VSS) tPHZ, tPLZ, ns
Output “1” or “0” to High Impedance, or tPZH, tPZL
High Impedance to “1” or “0” Level
MC14051B 5.0 350 700
10 170 340
15 140 280
MC14052B 5.0 300 600 ns
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ 10 155 310
15 125 250
MC14053B 5.0 275 550 ns
10 140 280
15 110 220
Control Input to Output (RL = 10 kΩ, VEE = VSS) tPLH, tPHL ns
MC14051B 5.0 360 720
10 160 320
15 120 240
MC14052B 5.0 325 650 ns
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ 10 130 260
15 90 180
MC14053B 5.0 300 600 ns
10 120 240
15 80 160
Second Harmonic Distortion — 10 0.07 — %
(RL = 10KΩ, f = 1 kHz) Vin = 5 VPP
Bandwidth (Figure 7) BW 10 17 — MHz
(RL = 1 kΩ, Vin = 1/2 (VDD–VEE) p–p, CL = 50pF
20 Log (Vout/Vin) = – 3 dB)
Off Channel Feedthrough Attenuation (Figure 7) — 10 – 50 — dB
RL = 1KΩ, Vin = 1/2 (VDD – VEE) p–p
fin = 4.5 MHz — MC14051B
fin = 30 MHz — MC14052B
fin = 55 MHz — MC14053B
Channel Separation (Figure 8) — 10 – 50 — dB
(RL = 1 kΩ, Vin = 1/2 (VDD–VEE) p–p,
fin = 3.0 MHz
Crosstalk, Control Input to Common O/I (Figure 9) — 10 75 — mV
(R1 = 1 kΩ, RL = 10 kΩ
Control tTLH = tTHL = 20 ns, Inhibit = VSS)
* The formulas given are for the typical characteristics only at 25_C.
#Data labelled “Typ” is not lo be used for design purposes but In intended as an indication of the IC’s potential performance.
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However,
precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance
circuit. For proper operation, Vin and Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS, VEE, or VDD). Unused outputs
must be left open.
MOTOROLA CMOS LOGIC DATA MC14051B MC14052B MC14053B

3
VDD VDD V
DD
IN/OUT OUT/IN
VEE
VDD
LEVEL
CONVERTED
IN/OUT OUT/IN
CONTROL
CONTROL
VEE
Figure 1. Switch Circuit Schematic
TRUTH TABLE 16 VDD
Control Inputs INH 6 BINARY TO 1–OF–8

Select ON Switches A 11 LEVEL
DECODER WITH
B 10 CONVERTER
Inhibit C* B A MC14051B MC14052B MC14053B C 9 INHIBIT
0 0 0 0 X0 Y0 X0 Z0 Y0 X0
0 0 0 1 X1 Y1 X1 Z0 Y0 X1 8 VSS 7 VEE
X0 13
0 0 1 0 X2 Y2 X2 Z0 Y1 X0
0 0 1 1 X3 Y3 X3 Z0 Y1 X1 X1 14
X2 15
0 1 0 0 X4 Z1 Y0 X0
0 1 0 1 X5 Z1 Y0 X1 X3 12 3 X
0 1 1 0 X6 Z1 Y1 X0 X4 1
0 1 1 1 X7 Z1 Y1 X1 X5 5
1 x x x None None None X6 2
* Not applicable for MC14052 X7 4
x = Don’t Care
Figure 2. MC14051B Functional Diagram
16 VDD
16 VDD
INH 6 BINARY TO 1–OF–4
LEVEL
A 10 DECODER WITH INH 6 BINARY TO 1–OF–2
CONVERTER A 11 LEVEL
B 9 INHIBIT DECODER WITH
B 10 CONVERTER
C 9 INHIBIT
8 VSS 7 VEE
X0 12 8 VSS 7 VEE
X1 14
13 X
X2 15 X0 12
14 X
X3 11 X1 13
Y0 1 Y0 2
15 Y
Y1 5 Y1 1
3 Y
Y2 2 Z0 5
4 Z
Y3 4 Z1 3
Figure 3. MC14052B Functional Diagram Figure 4. MC14053B Functional Diagram

4
TEST CIRCUITS
ON SWITCH
CONTROL A
PULSE
SECTION B
GENERATOR
OF IC C
LOAD Vout
V CL
INH RL
SOURCE
VDD VEE VEE VDD
Figure 5. ∆V Across Switch Figure 6. Propagation Delay Times,

Control and Inhibit to Output
A, B, and C inputs used to turn ON or OFF

the switch under test.
A RL
B A
C B ON
Vout
C
VSS INH RL CL = 50 pF
INH OFF
Vout
Vin RL CL = 50 pF
VDD – VEE
2 VDD – VEE Vin
2
Figure 7. Bandwidth and Off–Channel Figure 8. Channel Separation

Feedthrough Attenuation (Adjacent Channels Used For Setup)
OFF CHANNEL UNDER TEST

VDD
VEE
A CONTROL
B SECTION OTHER
C CHANNEL(S)
Vout OF IC VEE
INH RL CL = 50 pF VDD
R1
VEE
COMMON
VDD
Figure 9. Crosstalk, Control Input to Figure 10. Off Channel Leakage

Common O/I
NOTE: See also Figures 7 and 8 on Page 6–51.

5
VDD KEITHLEY 160
DIGITAL
MULTIMETER
10 k
1 kΩ
VDD RANGE X–Y
PLOTTER
VEE = VSS
Figure 11. Channel Resistance (RON) Test Circuit
TYPICAL RESISTANCE CHARACTERISTICS

350 350
300 300
R ON , “ON” RESISTANCE (OHMS)

250 250
200 200
150 150 TA = 125°C

TA = 125°C
100 100 25°C
25°C
– 55°C – 55°C
50 50
0 0
– 10 – 8.0 – 6.0 – 4.0 – 2.0 0 0.2 4.0 6.0 8.0 10 – 10 – 8.0 – 6.0 – 4.0 – 2.0 0 0.2 4.0 6.0 8.0 10
Vin, INPUT VOLTAGE (VOLTS) Vin, INPUT VOLTAGE (VOLTS)
Figure 12. VDD = 7.5 V, VEE = – 7.5 V Figure 13. VDD = 5.0 V, VEE = – 5.0 V
700 350
TA = 25°C
600 300
RON , “ON” RESISTANCE (OHMS)
500 250 VDD = 2.5 V
400 200
300 150
TA = 125°C 5.0 V
200 100
25°C 7.5 V
100 – 55°C 50
0 0
– 10 – 8.0 – 6.0 – 4.0 – 2.0 0 0.2 4.0 6.0 8.0 10 – 10 – 8.0 – 6.0 – 4.0 – 2.0 0 0.2 4.0 6.0 8.0 10
Vin, INPUT VOLTAGE (VOLTS) Vin, INPUT VOLTAGE (VOLTS)
Figure 14. VDD = 2.5 V, VEE = – 2.5 V Figure 15. Comparison at 25°C, VDD = – VEE
PIN ASSIGMENT
MC14051B MC14052B MC14053B
X4 1 16 VDD Y0 1 16 VDD Y1 1 16 VDD
X6 2 15 X2 Y2 2 15 X2 Y0 2 15 Y
X 3 14 X1 Y 3 14 X1 Z1 3 14 X
X7 4 13 X0 Y3 4 13 X Z 4 13 X1
X5 5 12 X3 Y1 5 12 X0 Z0 5 12 X0
INH 6 11 A INH 6 11 X3 INH 6 11 A
VEE 7 10 B VEE 7 10 A VEE 7 10 B
VSS 8 9 C VSS 8 9 B VSS 8 9 C

6
APPLICATIONS INFORMATION
Figure A illustrates use of the on–chip level converter de- above VDD and/or below VEE are anticipated on the analog
tailed in Figures 2, 3, and 4. The 0–to–5 V Digital Control sig- channels, external diodes (Dx) are recommended as shown
nal is used to directly control a 9 Vp–p analog signal. in Figure B. These diodes should be small signal types able
The digital control logic levels are determined by VDD and to absorb the maximum anticipated current surges during
V SS. The V DD voltage is the logic high voltage; the V SS volt- clipping.
age is logic low. For the example, V DD = + 5 V = logic high at The absolute maximum potential difference between V DD
the control inputs; VSS = GND = 0 V = logic low. and VEE is 18.0 V. Most parameters are specified up to 15 V
The maximum analog signal level is determined by V DD which is the recommended maximum difference between
and V EE. The V DD voltage determines the maximum recom- V DD and V EE.
mended peak above V SS. The V EE voltage determines the Balanced supplies are not required. However, V SS must
maximum swing below V SS. For the example, V DD – VSS = be greater than or equal to V EE. For example, V DD = + 10 V,
5 V maximum swing above V SS ; V SS – V EE = 5 V maximum V SS = + 5 V, and V EE – 3 V is acceptable. See the Table
swing below VSS. The example shows a ± 4.5 V signal which below.
allows a 1/2 volt margin at each peak. If voltage transients
+5 V –5 V
VDD VSS VEE
+ 4.5 V
9 Vp–p SWITCH
ANALOG SIGNAL I/O COMMON 9 Vp–p
GND
+5 V MC14051B O/I ANALOG SIGNAL
MC14052B
MC14053B
– 4.5 V
EXTERNAL 0–TO–5 V DIGITAL INHIBIT,
CMOS A, B, C
CONTROL SIGNALS
DIGITAL
CIRCUITRY
Figure A. Application Example
VDD VDD
DX DX
ANALOG COMMON
I/O O/I
DX DX
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
VEE VEE
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Figure B. External Germanium or Schottky Clipping Diodes
POSSIBLE SUPPLY CONNECTIONS
Control Inputs
VDD VSS VEE Logic High/Logic Low Maximum Analog Signal Range
In Volts In Volts In Volts In Volts In Volts
+8 0 –8 + 8/0 + 8 to – 8 = 16 Vp–p
+5 0 – 12 + 5/0 + 5 to – 12 = 17 Vp–p
+5 0 0 + 5/0 + 5 to 0 = 5 Vp–p
+5 0 –5 + 5/0 + 5 to – 5 = 10 Vp–p
+ 10 +5 –5 + 10/ + 5 + 10 to – 5 = 15 Vp–p

7
OUTLINE DIMENSIONS
L SUFFIX
CERAMIC DIP PACKAGE
CASE 620–10
ISSUE V
–A–
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
16 9
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
–B– FORMED PARALLEL.
1 8 4. DIMENSION F MAY NARROW TO 0.76 (0.030)
WHERE THE LEAD ENTERS THE CERAMIC
C L BODY.
INCHES MILLIMETERS
DIM MIN MAX MIN MAX
A 0.750 0.785 19.05 19.93
B 0.240 0.295 6.10 7.49
–T– C ––– 0.200 ––– 5.08
N K D 0.015 0.020 0.39 0.50
SEATING
PLANE E 0.050 BSC 1.27 BSC
F 0.055 0.065 1.40 1.65
G 0.100 BSC 2.54 BSC
E M H 0.008 0.015 0.21 0.38
K 0.125 0.170 3.18 4.31
F G J 16 PL
L 0.300 BSC 7.62 BSC
D 16 PL 0.25 (0.010) M T B S M 0_ 15 _ 0_ 15 _
N 0.020 0.040 0.51 1.01
0.25 (0.010) M T A S
P SUFFIX
PLASTIC DIP PACKAGE
CASE 648–08
ISSUE R
NOTES:
–A– 1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
16 9 3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
B 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
1 8 5. ROUNDED CORNERS OPTIONAL.
INCHES MILLIMETERS
DIM MIN MAX MIN MAX
F C L A 0.740 0.770 18.80 19.55
B 0.250 0.270 6.35 6.85
S C 0.145 0.175 3.69 4.44
D 0.015 0.021 0.39 0.53
SEATING F 0.040 0.70 1.02 1.77
–T– PLANE G 0.100 BSC 2.54 BSC
H 0.050 BSC 1.27 BSC
H K M J 0.008 0.015 0.21 0.38
J K 0.110 0.130 2.80 3.30
G L 0.295 0.305 7.50 7.74
D 16 PL
M 0_ 10 _ 0_ 10 _
0.25 (0.010) M T A M S 0.020 0.040 0.51 1.01

8
OUTLINE DIMENSIONS
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B–05
ISSUE J
–A–
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
16 9 2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
–B– MOLD PROTRUSION.
P 8 PL
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
1 8
0.25 (0.010) M B S PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
G
MILLIMETERS INCHES
DIM MIN MAX MIN MAX
F A 9.80 10.00 0.386 0.393
K R X 45 _ B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.054 0.068
D 0.35 0.49 0.014 0.019
C F 0.40 1.25 0.016 0.049
–T– SEATING G 1.27 BSC 0.050 BSC
PLANE
M J J 0.19 0.25 0.008 0.009
K 0.10 0.25 0.004 0.009
D 16 PL M 0_ 7_ 0_ 7_
P 5.80 6.20 0.229 0.244
0.25 (0.010) M T B S A S R 0.25 0.50 0.010 0.019
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,
and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided
in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters,
including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent
rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant
into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a
situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application,
Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or
unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered
trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
How to reach us:

USA/EUROPE/Locations Not Listed: Motorola Literature Distribution; JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, 6F Seibu–Butsuryu–Center,
P.O. Box 20912; Phoenix, Arizona 85036. 1–800–441–2447 or 602–303–5454 3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 03–81–3521–8315
MFAX: RMFAX0@email.sps.mot.com – TOUCHTONE 602–244–6609 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park,
INTERNET: http://Design–NET.com 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298
*MC14051B/D*
◊
MC14051B/D
9

Motorola - MC14053B PDF

Загружено:

Сведения о документе

Оригинальное название

Авторское право

Доступные форматы

Поделиться этим документом

Поделиться или встроить документ

Параметры публикации

Этот документ был вам полезен?

Это неприемлемый материал?

Авторское право:

Доступные форматы

Motorola - MC14053B PDF

Загружено:

Авторское право:

Доступные форматы

SEMICONDUCTOR TECHNICAL DATA

VDD = PIN 16 VDD = PIN 16 VDD = PIN 16

MOTOROLA CMOS LOGIC DATA

MC14051B MC14052B MC14053B MOTOROLA CMOS LOGIC DATA

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ VDD – VEE Typ #

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ 10 155 310

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ 10 130 260

MOTOROLA CMOS LOGIC DATA MC14051B MC14052B MC14053B

Figure 1. Switch Circuit Schematic

TRUTH TABLE 16 VDD

Control Inputs INH 6 BINARY TO 1–OF–8

Figure 3. MC14052B Functional Diagram Figure 4. MC14053B Functional Diagram

MC14051B MC14052B MC14053B MOTOROLA CMOS LOGIC DATA

VDD VEE VEE VDD

Figure 5. ∆V Across Switch Figure 6. Propagation Delay Times,

A, B, and C inputs used to turn ON or OFF

Figure 7. Bandwidth and Off–Channel Figure 8. Channel Separation

OFF CHANNEL UNDER TEST

Figure 9. Crosstalk, Control Input to Figure 10. Off Channel Leakage

NOTE: See also Figures 7 and 8 on Page 6–51.

MOTOROLA CMOS LOGIC DATA MC14051B MC14052B MC14053B

Figure 11. Channel Resistance (RON) Test Circuit

TYPICAL RESISTANCE CHARACTERISTICS

R ON , “ON” RESISTANCE (OHMS)

150 150 TA = 125°C

500 250 VDD = 2.5 V

MC14051B MC14052B MC14053B MOTOROLA CMOS LOGIC DATA

VDD VSS VEE

Figure A. Application Example

MOTOROLA CMOS LOGIC DATA MC14051B MC14052B MC14053B

MC14051B MC14052B MC14053B MOTOROLA CMOS LOGIC DATA

How to reach us:

Вам также может понравиться