Exploring DFT Methodologies for 3D Integration Chip

Chen-An Chen, Yee-Wen Chen, Ming-Hsueh Wu,

Kun-Lun Luo, Liang-Chia Cheng

Industrial Technology Research Institute

Hsinchu, Taiwan

www.itri.org.tw

ABSTRACT

Comparing to the existing 2D chips, three dimensional integration chips (3D ICs) have been
developed to provide higher band-width, smaller delay, smaller form factor, and lower power
consumption. Practically, to realize the 3D ICs, one has to face not only the difficulty of stacking
technology during manufacture process but also serious testing issues derived. In literature, many
test methodologies, such as boundary scan, core-based wrapper, interconnection testing, and test
integration methods have been proposed to test 3D ICs. However, without the support of proper
design flow and EDA tools, design-for-test (DfT) circuits and testing requirements of 3D ICs are
difficult to implement. Many test methodologies proposed for 3D ICs didn’t consider the realistic
situation from the feature of EDA tools. In this paper, we describe the challenges while develop-
ing the DFT in 3D IC design. Moreover, we present a reference design flow and realistic metho-
dologies to address the issue of “How to realize DFT circuit on 3D ICs?”. We use a processor-to-
memory stacking as an example to demonstrate a useful and easier way to implement 3D ICs
with our proposed methods by extending current conventional EDA DFT tools.
 Table of Contents
1. Introduction ............................................................................................................................. 3
2. Three Dimensional Integration Chips Testing ........................................................................ 3
3. Efficient and Realistic DFT Implementation Flow ................................................................. 4

3.1. DfT Architecture .................................................................................................... 5

3.2. 3D DFT Architecture ............................................................................................. 6

3.3. Test Pattern Generation ........................................................................................ 7

4. Experimental Results .............................................................................................................. 8
5. Conclusions ............................................................................................................................. 8
6. References ............................................................................................................................... 9
Table of Figures
Figure 1 Evolution of 3D IC testing ............................................................................................... 4
Figure 2 3D ICs Implementation Flow ........................................................................................... 4
Figure 3 Core Wrapper and CODEC Architecture ......................................................................... 5
Figure 4 Scan Architecture.............................................................................................................. 6
Figure 5 3D Test Access Mechanism Architecture ......................................................................... 6
Figure 6 Our Proposed DFT Architecture ....................................................................................... 7
Figure 7 3D IC Test Pattern Generation Flow ................................................................................ 7

Table of Tables
Table 1 Detail Information of DFTMAX Configuration ................................................................ 5
Table 2 Realistic compression ratio in PAC design ........................................................................ 8

SNUG 2011 2 Exploring DFT Methodologies for 3D Integration Chip

1. Introduction
Because of the limitation of process technology and the complexity of circuit design, it is dif-
ficult to keep the increasing rate of transistor density under the Moores’ Law. Besides, as the die
size increases, longer routing distance also seriously damages electrical characteristics, such as
power consumption, interconnection delay and signal integrity. In order to solve these problems,
three dimensional integration technologies have been proposed to become a next generation
technology and provided an opportunity to realize a realistic and complicated system-on-a-chip.
Although a complex and powerful design can be realized by 3D IC, it’s a big challenge to im-
plement the testing circuit for 3D IC. In a word, we have to consider the die testing before bond-
ing and post-bond testing after die stacking. To satisfy the testing requirements, there are many
new challenges to test 3D ICs. Many researchers have proposed some design-for-testing (DfT)
methodologies for 3D ICs, however most of these methods couldn’t be easily and directly rea-
lized by present EDA tools. For 3D IC design, many DFT technologies only focus on the specific
test issues such as TSV testing, test access mechanisms, and scan clock architecture, instead of
the overall consideration based on integration of EDA tools.
In this paper, we explore some DFT methodologies and implement them in a 3D IC design.
We propose a DFT implementation flow which can be applied to 3D ICs design, and further
show experimental results to share our experience. We use DFTMAX to build up an automatic
DFT implementation flow, and generate test pattern in TetraMax for 3D IC testing. The rest of
the paper is organized as follows. In section 2, we briefly describe an overview of previous re-
lated-work for 3D IC testing. In section 3, we explain our proposal of DFT architecture and im-
plementation flow. In section 4, the experimental results are shown. Finally, in section 5, we con-
clude the paper.

2. Three Dimensional Integration Chips Testing

With the increasing of die size and chip complexity, 3D integration chip (3D IC) has been pro-
posed to overcome problems of routing resource, delay slack, and power consumption. Although
3D IC has many benefits, it’s also with many challenges such as stacking process technology,
design partition, and circuit testing. Especially, for the issue of testing 3D ICs, we have to solve
problems in both 2D dies and stacking dies. We have to consider harsher test conditions like
probing count, power consumption, testing time and circuit architecture. Many researchers
pointed out test challenges and provided solutions for 3D ICs since 2007 [2]. Afterwards, many
other advanced researchers continuously proposed variety of methodologies for 3D IC testing.
One of the topics focused on the test access architecture which is a key point to meet testing re-
quirement for 3D ICs. An useful test-access-mechanism (TAM) effectively provides convenient
and powerful methods to test die around stacking. Therefore, in 2010, researchers started to
make use of JTAG or wrapper technologies and proposed IEEE 1149.1/1500 compliant TAM
designs [5][6] for 3D ICs. In 2011, some companies have even announced their design-for-
testing (DfT) strategies for 3D ICs. However, up to now, most of their methodologies only con-
sider the design of test access interface, but not a realistic and complete enough strategy to real-
ize a generic 3D IC.
In addition to TAM designs, testing interconnection in through silicon via (TSV) is also a pop-
ular topic. Many researchers preferred to identify failure TSV and made sure its slack is within a
correct region [3][4]. Because there is serious area overhead in test circuit design, these are not
realistic and necessary methodologies. It’s difficult to realize TSV parameter testing in various
products.

SNUG 2011 3 Exploring DFT Methodologies for 3D Integration Chip

 Mentor announces
Self test TSVmethods Core-based and 1500 3D DieStack Many- Tessent Platform for 3D Cadence proposes
First paper for 3D-SICs testing before bonding compatible TAM Core Processor IC testing Encounter Test 3D test

2007 2008 2009 2010 2011

Test-Access Mechanism Optimization Hierarchical WIR CMC announces a 3D test chip

mechanism (boundary scan insertion)
GOPEL electronics support JTAG/Boundary
scan for 3D integration system

Figure 1 Evolution of 3D IC testing

3. Efficient and Realistic DFT Implementation Flow

In this section, we present a low-power DFT architecture and implementation flow for 3D ICs.
A 3D IC flow is built by using DFTMAX and TetraMAX tools. This flow is partitioned into
three portions and implemented in a bottom-up methodology. Generally, the DFT framework is
affected by many factors, and we have to consider scan chain number, scan chain length, test port
usage, and plug-and-play design, etc based on the limitation of test resource. In 3D IC DFT ar-
chitectures, we implement DFT circuits in three stages (block level, die level, and die-to-die lev-
el). In the block level, we start to plan test scheme according to function characteristic as for 2D
ICs. Afterwards, we plan to use the boundary scan design as test access interface for 3D IC and
improve controllability and observability of inputs/outputs for pre-bond testing. Finally, we use
ATPG tool to generate test patterns for post-bond testing.

Block Design
3D ICs Hierarchical DfT Integration Flow

block level

Scan Configuration

Core Wrapper Insertion

Scan Compression/Serializer

Scan Extraction
intra-die

Boundary Scan Insertion

Pre-bond Test Pattern Gen.

inter-die

Inter-die Integration by JTAG

Post-bond Test Pattern Gen.

Figure 2 3D ICs Implementation Flow

SNUG 2011 4 Exploring DFT Methodologies for 3D Integration Chip

3.1. DfT Architecture
Our design is a multi-media platform with dual DSP processors in bottom die and stacking
memories. We apply core-wrapper, CODEC (compressor/de-compressor) and scan serializer me-
thodologies for the DSP processor based on its reusable feature. 80 internal scan chains which
include wrapper chains are planned for scan compressor, and the longest scan chain contains 342
scan elements. Fewer scan data input/output pins are required and test time is reduced for CO-
DEC design. In order to identify KNG (know good die) before die stacking, there are only a few
available testing probes in CP (circuit probing) test. DFTMAX scan architecture becomes a use-
ful solution to overcome this problem, and it obviously reduces test cost for complicated 3D IC
testing. The DFTMAX scan architecture is depicted in Figure 3.
Besides the DSP processor, this scan compression architecture is also applied to other peri-
pheral circuits. Unlike DSP processor, boundary scan circuit is inserted instead to enhance testa-
bility. As depicted in Figure 4, boundary scan cells are inserted for all IOs and all clocks are con-
trolled by TAP controller. Table 1 shows detail information of our DFT architecture.

DfT Configuration Peripheral DSP Code

# Serializer Chain 1 1
# CODEC Chains 6 5
# Internal Scan Chains 192 80
Max Internal Chain Length 1658 342
Wrapper Design False True
Boundary Scan Design True False
Table 1 Detail Information of DFTMAX Configuration

scan data in
Deserializer
serial_clk
Update Stage

Decompressor
Wrapper Chain

Scan Chain

Scan Chain

Scan Chain

Scan Chain

Scan Chain

Scan Chain

Scan Chain

∙∙∙
80

Compressor

Serializer scan data out

Core Wrapper & CODEC Architecture
Figure 3 Core Wrapper and CODEC Architecture

SNUG 2011 5 Exploring DFT Methodologies for 3D Integration Chip

 TDI TDI
Deserializer Deserializer
serial_clk serial_clk
Update Stage Update Stage

Decompressor Decompressor

Scan Chain
Scan Chain
Scan Chain
Scan Chain

Scan Chain
Scan Chain
Scan Chain

Scan Chain
Scan Chain
Scan Chain
Scan Chain

Scan Chain
Scan Chain
Scan Chain
Wrapper
Wrapper

Wrapper
Wrapper
∙∙∙ ∙∙∙
80 scan_clk 80

Compressor Compressor

scan data out scan data out

Serializer Serializer

TDI
scan data in
Deserializer
TDI Serializer
serial_clk
Clock
TCK IEEE Update Stage
Controller
1149.1
TMS JTAG Decompressor
TRSTN
Scan Chain
Scan Chain
Scan Chain
Scan Chain
Scan Chain
Scan Chain

Scan Chain
Scan Chain
Scan Chain

Wrapper
Wrapper
BSR
scan_clk

∙∙∙
192

Compressor

scan data out TDO

Serializer

Figure 4 Scan Architecture

3.2. 3D DFT Architecture

Last year, we proposed a boundary scan based design as test access mechanism (TAM) for 3D
IC testing. In this design, we have successfully realized the TAM and built an automatic imple-
mentation flow. Here, we combine the boundary scan design with the CODEC scan architecture
and compliable IEEE 1149.1 standard. As illustrated in Figure 5, we create boundary scan in-
structions to match requirements of 3D IC testing. There are two instruction categories, pre-bond
and post-bond instructions, to control multiplexers and propagate test results to TDO. The in-
structions also decide different kinds of scan test to be performed. Besides, all boundary scan
register(s) can be included into internal scan chains and be compressed by CODEC circuits. No-
wadays, this technology can’t be realized by any existing EDA tools.

Scan Chain Scan Chain Scan Chain

Scan Chain Scan Chain Scan Chain
Scan Chain Scan Chain Scan Chain

Core 1 Core 2 Core 3

PAD_TDI PAD_TDI

TSV_TDI TSV_TDI
PAD_TDI Up_TDO Up_TDO
PAD_TDO

IR Down_TDO
IR Down_TDO
IR
Bypass Bypass Bypass

PAD_TDO
PAD_TDO
TAP Controller TAP Controller TAP Controller

TCK TMS TRSTN TCK TMS TRSTN TCK TMS TRSTN

Figure 5 3D Test Access Mechanism Architecture

SNUG 2011 6 Exploring DFT Methodologies for 3D Integration Chip

 Figure 6 shows DFT architecture for our realistic multi-media platform. In bottom die, we use
CODEC, serializer, core-based wrapper and boundary scan design to test logic circuits. Boun-
dary scan design not only supports pre-bond, post-bond, multi-mode INTEST and EXTEST, but
also controls memory BIST circuits to test SRAM.

MEM MEM
ID Gen

BIST

MEM MEM

DSP DSP
MEM MEM

MEM BIST TAPC

Figure 6 Our Proposed DFT Architecture

3.3. Test Pattern Generation

It is well known that test pattern generation is also a problem for 3D IC testing, and not many
EDA venders can provide convenient enough methods to generate suitable test protocol file for
ATPG tools. Most of test patterns are generated by user-designed programs even if manual mod-
ification. We use commercial tool to insert DFT circuits, so we can use some work-around me-
thods to generate test patterns in TetraMAX.
Generally, the test protocol file should be provided for ATPG tools to generate test patterns, so
it’s important that the test protocol file can be generated in an efficient way. As depicted in Fig-
ure 7, we build a test pattern generation flow for 3DIC. The test_setup part is first generated after
boundary scan insertion, and then it’s combined with the test protocol file after CO-
DEC/serializer insertion in DFTCMAX, The final combined test protocol file is read into Tetra-
Max for pattern generation.
Scan
Configuration

Wrapper/Boundary Scan Insertion

Boundary Scan
UDI Test Setup

Multi-mode CODEC/Serializer

Multi-mode Test
Protocol File

TetraMAX

Multi-mode 3D
IC Test Pattern

Figure 7 3D IC Test Pattern Generation Flow

SNUG 2011 7 Exploring DFT Methodologies for 3D Integration Chip

4. Experimental Results
From the experimental results shown in Table 2, with the same fault coverage, there is a slight
increase in the pattern number, but the test time and the test pin number are greatly reduced.
Thus, the test cost to test KGD is also greatly reduced. For 3D IC testing, test time, test pin count
are important factors to impact test costs. With the increasing of the circuit complexity, more test
patterns are generated in order to keep the same fault coverage. Although the compression ratio
is lower than inner/outer chain number ratio as expected, it’s still a useful mechanism.
# IC: Internal chain number
FC: fault coverage
TC: test cycle time

DSP FC (95%) Length # Pattern Test Cycle # IC TC Reduction Compression Ratio

full scan 8546 1376 11759296 4 21.4 (times) 85.7
serializer 342 1604 548568 80
Platform FC (95%) Length # Pattern Test Cycle # IC TC Reduction Compression Ratio
full scan 7849 1408 11051392 40 2.9 (times) 116.9
serializer 1658 2279 3778582 192
Table 2 Realistic compression ratio in PAC design

5. Conclusions
In this project, a complete DFT implementation flow is presented with a realistic 3DIC design.
IEEE 1149.1, core wrapper, and CODEC methodologies are integrated into a 3D DFT methodol-
ogy. In this DFT methodology, we make use of consumer tools to realize and provide a low-
power and cost-aware 3DIC DFT implementation flow. In our 3D DfT scheme, boundary scan
design doesn’t need to be modified for parallel scan access, and core-based wrapper doesn’t need
to support die level testing [8]. In summary, the DFT scheme provides a suitable and useful
thinking for EDA vendor to build a 3D IC testing flow.

SNUG 2011 8 Exploring DFT Methodologies for 3D Integration Chip

6. References
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on the Alpha 21364 processor," VLSI Test Symposium, 2002. (VTS 2002). Proceedings 20th IEEE ,
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[3] Menglin Tsai; Klooz, A.; Leonard, A.; Appel, J.; Franzon, P.; , "Through Silicon Via(TSV) defect/
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[6] Marinissen, E.J.; Verbree, J.; Konijnenburg, M.; , "A structured and scalable test access architecture
for TSV-based 3D stacked ICs," VLSI Test Symposium (VTS), 2010 28th , pp.269-274, 19-22 April
2010
[7] Jiang, L.; Liu, Y.; Duan, L.; Xie, Y.; Xu, Q.; , "Modeling TSV Open Defects in 3D-Stacked DRAM,"
International Test Conference, IEEE International Conference, 2010.
[8] TSMC Reference Flow 12.0
[9] Design Compiler User Guide Version D-2010.03, March 2010
[10] DFT Compiler Scan User Guide Version D-2010.03, March 2010
[11] BSD Compiler User Guide Version D-2010.03, March 2010
[12] TetraMAX ATPG User Guide Version D-2010.03, March 2010
[13] Synopsys SolvNet, https://solvnet.synopsys.com/