module gcd(num1,num2,rst,z);

input [3:0]num1,num2;
input rst;
output reg[3:0]z;
integer i;
always @(rst)
begin
if(rst==1)
z=0;
else
begin
for(i=1;((i<=num1)&&(i<=num2));i=i+1)
if((num1%i==0)&&(num2%i==0))
begin
z=i;
end
end
end
endmodule

module fft(x0,x1,x2,x3,y0,y1_r,y1_i,y2,y3_r,y3_i);
input [1:0]x0,x1,x2,x3;
output [1:0]y0,y1_r,y1_i,y2,y3_r,y3_i;
parameter w0=2'b01;
parameter w1=2'b11;
wire[1:0]a,b,c,d;
assign a=x0+(w0*x2);
assign b=x0-(w0*x2);
assign c=x1+(w0*x3);
assign d=x1-(w0*x3);
assign y0=a+(w0*c);
assign y1_r=b;
assign y1_i=(w1*d);
assign y2=a-(w0*c);
assign y3_r=b;
assign y3_i=(~(w1*d)+1);
endmodule

module ifft_4pt(y0,y1_r,y1_i,y2,y3_r,y3_i,x0_r,x0_i,x1_r,x1_i,x2_r,x2_i,x3_r,x3_i);
input [1:0]y0,y1_r,y1_i,y2,y3_r,y3_i;
output [1:0]x0_r,x0_i,x1_r,x1_i,x2_r,x2_i,x3_r,x3_i;
parameter w0=2'b01;
parameter w1=2'b11;
parameter n=4;
wire [1:0]a,b,c_r,c_i,d_r,d_i,y1_i_conj,y3_i_conj,dt_r,dt_i;
assign y1_i_conj=((~y1_i)+1);
assign y3_i_conj=((~y3_i)+1);
assign a=y0+(w0*y2);
assign b=y0-(w0*y2);
assign c_r=(y1_r+(y3_r*w0));
assign c_i=y1_i_conj+(y3_i_conj*w0);
assign d_r=y1_r-(y3_r*w0);
assign d_i=y1_i_conj-(y3_i_conj*w0);
assign dt_r=(~(w1*d_i)+1);
assign dt_i=w1*d_r;
assign x0_r=(a+(w0*c_r))/n;
assign x0_i=(0+(w0*c_i))/n;//0 for a img
assign x1_r=(b+(dt_r))/n;
assign x1_i=(0+(dt_i))/n;
assign x2_r=(a-(w0*c_r))/n;
assign x2_i=(0-(w0*c_i))/n;
assign x3_r=(b-(dt_r))/n;
assign x3_i=(0-(dt_i))/n;
endmodule

module carryselect1(a,b,cin,sum,cout);
input [3:0]a,b;
input cin;
output reg[3:0]sum;
output reg cout;
reg [3:1]c;
always @(a or b or cin)
begin
if(cin==0)
begin
sum[0]=a[0]^b[0]^cin;
c[1]=((a[0]&b[0])|(b[0]&cin)|(cin&a[0]));
sum[1]=a[1]^b[1]^cin;
c[2]=((a[1]&b[1])|(b[1]&cin)|(cin&a[1]));
sum[2]=a[2]^b[2]^cin;
c[3]=((a[2]&b[2])|(b[2]&cin)|(cin&a[2]));
sum[3]=a[3]^b[3]^cin;
cout=((a[3]&b[3])|(b[3]&cin)|(cin&a[3]));
end
else
begin
sum[0]=a[0]^b[0]^cin;
c[1]=((a[0]&b[0])|(b[0]&cin)|(cin&a[0]));
sum[1]=a[1]^b[1]^cin;
c[2]=((a[1]&b[1])|(b[1]&cin)|(cin&a[1]));
sum[2]=a[2]^b[2]^cin;
c[3]=((a[2]&b[2])|(b[2]&cin)|(cin&a[2]));
sum[3]=a[3]^b[3]^cin;
cout=((a[3]&b[3])|(b[3]&cin)|(cin&a[3]));
end
end
endmodule

module brawn2(x,y,p);
input [3:0]x;
input [3:0]y;
output [7:0]p;
wire [15:0]w;
wire [11:0]s;
wire [11:0]c;
assign p[0]=w[0];
assign p[1]=s[0];
assign p[2]=s[3];
assign p[3]=s[6];
assign p[4]=s[9];
assign p[5]=s[10];
assign p[6]=s[11];
assign p[7]=c[11];
assign w[0]=x[0]&y[0];
assign w[1]=x[1]&y[0];
assign w[2]=x[2]&y[0];
assign w[3]=x[3]&y[0];
assign w[4]=x[0]&y[1];
assign w[5]=x[1]&y[1];
assign w[6]=x[2]&y[1];
assign w[7]=x[3]&y[1];
assign w[8]=x[0]&y[2];
assign w[9]=x[1]&y[2];
assign w[10]=x[2]&y[2];
assign w[11]=x[3]&y[2];
assign w[12]=x[0]&y[3];
assign w[13]=x[1]&y[3];
assign w[14]=x[2]&y[3];
assign w[15]=x[3]&y[3];
assign s[0]=w[1]^w[4]^1'b0;
assign c[0]=((w[1]&w[4])|(w[4]&1'b0)|(1'b0&w[1]));
assign s[1]=w[2]^w[5]^1'b0;
assign c[1]=((w[2]&w[5])|(w[5]&1'b0)|(1'b0&w[2]));
assign s[2]=w[3]^w[6]^1'b0;
assign c[2]=((w[3]&w[6])|(w[6]&1'b0)|(1'b0&w[3]));
assign s[3]=s[1]^w[8]^c[0];
assign c[3]=((s[1]&w[8])|(w[8]&c[0])|(c[0]&s[1]));
assign s[4]=s[2]^w[9]^c[1];
assign c[4]=((s[2]&w[9])|(w[9]&c[1])|(c[1]&s[2]));
assign s[5]=w[7]^w[10]^c[2];
assign c[5]=((w[7]&w[10])|(w[10]&c[2])|(c[2]&w[7]));
assign s[6]=s[4]^c[3]^w[12];
assign c[6]=((s[4]&c[3])|(c[3]&w[12])|(w[12]&s[4]));
assign s[7]=s[5]^c[4]^w[13];
assign c[7]=((s[5]&c[4])|(c[4]&w[13])|(w[13]&s[5]));
assign s[8]=w[11]^w[14]^c[5];
assign c[8]=((w[11]&w[14])|(w[14]&c[5])|(c[5]&w[11]));
assign s[9]=s[7]^c[6]^1'b0;
assign c[9]=((s[7]&c[6])|(c[6]&1'b0)|(1'b0&s[7]));
assign s[10]=s[8]^c[7]^c[9];
assign c[10]=((s[8]&c[7])|(c[7]&c[9])|(c[9]&s[8]));
assign s[11]=w[15]^c[8]^c[10];
assign c[11]=((w[15]&c[8])|(c[8]&c[10])|(c[10]&w[15]));
endmodule

module gcd(clk,rst,start,P,Q,R,valid, state_Y);

input clk,rst,start;
input [3:0]P,Q;
output [3:0]R;
output valid;
output [1:0]state_Y;
wire valid,ldp,ldq,ldr,selp,selq, sela,selb,eq,gth;
wire [3:0]R;
datapath dp(clk,rst,ldp,ldq,ldr,selp, selq,sela,selb,P,Q,eq,gth,R);
controlunit cu(clk,rst,start,eq,gth,valid, ldp,ldq,ldr,selp,selq,sela,
selb,state_Y);
endmodule

module datapath(clk,rst,ldp,ldq,ldr, selp,selq,sela,selb,P,Q,eq, gth,R);

input clk,rst,ldp,ldq,ldr,selp,selq, sela,selb;
input [3:0]P,Q;
output eq,gth;
output reg[3:0]R;
reg [3:0]pbus,qbus,alu,abus,bbus;
always @ (posedge rst or posedge clk)
begin
if(rst)
pbus<=0;
else if(ldp)
begin
if(selp) pbus<=P;
else pbus<=alu;
end
end
always @ (posedge rst or posedge clk)
begin
if(rst)
qbus<=0;
else if(ldq)
begin
if(selq) qbus<=Q;
else qbus<=alu;
end
end
always @ (posedge clk)
begin
if(ldr) R<=pbus;
else R<=R;
end
always @ (pbus or qbus or sela)
begin
if(sela==1) abus=pbus;
else abus=qbus;
end
always @ (pbus or qbus or selb)
begin
if(selb==1) bbus=qbus;
else bbus=pbus;
end
always @ (abus or bbus)
begin
alu=abus-bbus;
end
assign eq=(pbus==qbus)?1:0;
assign gth=(pbus>qbus)?1:0;
endmodule

module controlunit(clk,rst,start,eq, gth,valid,ldp,ldq,ldr,selp,

selq,sela,selb,state_Y);
input clk,rst,start,eq,gth;
output valid,ldp,ldq,ldr,selp,selq, sela,selb;
output [1:0]state_Y;
reg [7:0]cv;
reg [1:0]y,Y;
wire valid,ldp,ldq,ldr,selp,selq, sela,selb;
parameter s0=0,s1=1,s2=2,s3=3;
assign selp=cv[7];
assign selq=cv[6];
assign sela=cv[5];
assign selb=cv[4];
assign ldp=cv[3];
assign ldq=cv[2];
assign ldr=cv[1];
assign valid=cv[0];
assign state_Y=Y;
always @ (y or start or eq or gth)
begin
case(y)
s0: if(!start) Y=s0; else if(eq) Y=s1; else if(gth) Y=s2;else Y=s3;
s1: Y=s0;
s2: if(eq) Y=s1; else if(gth) Y=s2;else Y=s3;
s3: if(eq) Y=s1; else if(gth) Y=s2;else Y=s3;
endcase
end
always @ (posedge rst or negedge clk)
begin
if(rst) y<=s0; else y<=Y;
end
always @ (y)
begin
case(y)
s0:cv=8'b11001100;
s1:cv=8'b00000011;
s2:cv=8'b00111000;
s3:cv=8'b00000100;
endcase
end
endmodule